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ORCIDCarl Ebeling
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- affiliation: University of Washington, Seattle, Washington, USA
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2020 – today
- 2020
[i1]Jesmin Jahan Tithi, Fabrizio Petrini, Hongbo Rong, Andrei Valentin, Carl Ebeling:
Mapping Stencils on Coarse-grained Reconfigurable Spatial Architecture. CoRR abs/2011.05160 (2020)
2010 – 2019
- 2016
- [c41]Carl Ebeling, Dana How
, David M. Lewis, Herman Schmit:
Stratix™ 10 High Performance Routable Clock Networks. FPGA 2016: 64-73 - 2012
- [c40]Corey B. Olson, Maria Kim, Cooper Clauson, Boris Kogon, Carl Ebeling, Scott Hauck, Walter L. Ruzzo:
Hardware Acceleration of Short Read Mapping. FCCM 2012: 161-168 - [c39]Robin Panda, Carl Ebeling, Scott Hauck:
Adding dataflow-driven execution control to a Coarse-Grained Reconfigurable Array. FPL 2012: 353-360 - 2011
- [c38]Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck:
Energy-efficient specialization of functional units in a coarse-grained reconfigurable array. FPGA 2011: 107-110 - [c37]Jacob Nelson, Brandon Myers, A. H. Hunter, Preston Briggs, Luis Ceze, Carl Ebeling, Dan Grossman, Simon Kahan, Mark Oskin:
Crunching Large Graphs with Commodity Processors. HotPar 2011 - 2010
- [c36]Brian Van Essen, Robin Panda, Aaron Wood, Carl Ebeling, Scott Hauck:
Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays. FPL 2010: 380-387
2000 – 2009
- 2009
- [c35]Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck:
SPR: an architecture-adaptive CGRA mapping tool. FPGA 2009: 191-200 - [c34]Brian Van Essen, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck:
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays. FPL 2009: 268-275 - 2007
- [c33]Carl Ebeling, Brian French:
Abstract Verilog: A Hardware Description Language for Novice Students. MSE 2007: 105-106 - 2006
- [j13]Akshay Sharma, Carl Ebeling, Scott Hauck:
PipeRoute: a pipelining-aware router for reconfigurable architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 518-532 (2006) - [c32]Carl Ebeling:
Configurable Computing Platforms - Promises, Promises. ASAP 2006: 3-4 - [c31]Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling:
A Type Architecture for Hybrid Micro-Parallel Computers. FCCM 2006: 99-110 - [c30]Benjamin Ylvisaker, Brian Van Essen, Carl Ebeling:
A type architecture for hybrid micro-parallel computers. FPGA 2006: 227 - [c29]Allan Carroll, Carl Ebeling:
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding. FPL 2006: 1-6 - 2005
- [c28]Akshay Sharma, Carl Ebeling, Scott Hauck:
Architecture Adaptive Routability-Driven Placement for FPGAs (abstract only). FPGA 2005: 266 - [c27]Akshay Sharma, Carl Ebeling, Scott Hauck:
Architecture-Adaptive Routability-Driven Placement for FPGAs. FPL 2005: 427-432 - 2004
- [j12]Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu:
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. IEEE Trans. Computers 53(11): 1436-1448 (2004) - [c26]Akshay Sharma, Katherine Compton, Carl Ebeling, Scott Hauck:
Exploration of pipelined FPGA interconnect structures. FPGA 2004: 13-22 - [c25]John F. Keane, Christopher Bradley, Carl Ebeling:
A compiled accelerator for biological cell signaling simulations. FPGA 2004: 233-241 - [c24]Song Li, Carl Ebeling:
QuickRoute: a fast routing algorithm for pipelined architectures. FPT 2004: 73-80 - 2003
- [c23]Akshay Sharma, Carl Ebeling, Scott Hauck:
PipeRoute: a pipelining-aware router for FPGAs. FPGA 2003: 68-77 - [c22]Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu:
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. FPL 2003: 21-30 - 2001
- [c21]Chris Fisher, Kevin Rennie, Guanbin Xing, Stefan G. Berg, Kevin Bolding, John H. Naegle, Daniel Parshall, Dmitriy Portnov, Adnan Sulejmanpasic, Carl Ebeling:
An Emulator for Exploring RaPiD Configurable Computing Architectures. FPL 2001: 17-26 - 2000
- [j11]Pak K. Chan, Martine D. F. Schlag, Carl Ebeling, Larry McMurchie:
Distributed-memory parallel routing for field-programmable gatearrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 850-862 (2000)
1990 – 1999
- 1999
- [c20]Darren C. Cronquist, Chris Fisher, Miguel E. Figueroa, Paul Franklin, Carl Ebeling:
Architecture Design of Reconfigurable Pipelined Datapaths. ARVLSI 1999: 23-41 - 1998
- [j10]Scott Hauck, Gaetano Borriello, Carl Ebeling:
Mesh routing topologies for multi-FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 400-408 (1998) - [c19]Darren C. Cronquist, Paul Franklin, Stefan G. Berg, Carl Ebeling:
Specifying and Compiling Applications for RaPiD. FCCM 1998: 116-125 - [c18]Soha Hassoun, Carl Ebeling:
Using precomputation in architecture and logic resynthesis. ICCAD 1998: 316-323 - 1997
- [j9]William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg:
Seeking Solutions in Configurable Computing. Computer 30(12): 38-43 (1997) - [c17]Carl Ebeling, Darren C. Cronquist, Paul Franklin:
Configurable computing: the catalyst for high-performance architectures. ASAP 1997: 364-373 - [c16]Carl Ebeling, Darren C. Cronquist, Paul Franklin, Jason Secosky, Stefan G. Berg:
Mapping applications to the RaPiD configurable architecture. FCCM 1997: 106-115 - [c15]Carl Ebeling:
Whither Configurable Computing? HICSS (1) 1997: 713 - [c14]Neil R. McKenzie, Kevin Bolding, Carl Ebeling, Lawrence Snyder:
ChaosLAN: Design and Implementation of a Gigabit LAN Using Chaotic Routing. PCRCW 1997: 247-260 - [e2]Carl Ebeling:
Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, FPGA 1997, Monterey, CA, USA, February 9-11, 1997. ACM 1997, ISBN 0-89791-801-0 [contents] - 1996
- [c13]Soha Hassoun, Carl Ebeling:
Architectural Retiming: Pipelining Latency-Constrained Circuts. DAC 1996: 708-713 - [c12]Carl Ebeling, Darren C. Cronquist, Paul Franklin:
RaPiD - Reconfigurable Pipelined Datapath. FPL 1996: 126-135 - [e1]Jonathan Rose, Carl Ebeling:
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, FPGA 1996, Monterey, CA, USA, February 11-13, 1996. ACM 1996, ISBN 0-89791-773-1 [contents] - 1995
- [j8]Carl Ebeling, Larry McMurchie, Scott Hauck, Steven M. Burns:
Placement and routing tools for the Triptych FPGA. IEEE Trans. Very Large Scale Integr. Syst. 3(4): 473-482 (1995) - [j7]Gaetano Borriello, Carl Ebeling, Scott Hauck, Steven M. Burns:
The Triptych FPGA architecture. IEEE Trans. Very Large Scale Integr. Syst. 3(4): 491-501 (1995) - [c11]Carl Ebeling, Brian Lockyear:
On the performance of level-clocked circuits. ARVLSI 1995: 342-357 - [c10]Larry McMurchie, Carl Ebeling:
PathFinder: A Negotiation-based Performance-driven Router for FPGAs. FPGA 1995: 111-117 - 1994
- [j6]Scott Hauck, Steven M. Burns, Gaetano Borriello, Carl Ebeling:
An FPGA for Implementing Asynchronous Circuits. IEEE Des. Test Comput. 11(3): 60-69 (1994) - [j5]Brian Lockyear, Carl Ebeling:
Optimal retiming of level-clocked circuits using symmetric clock schedules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9): 1097-1109 (1994) - [c9]Scott Hauck, Gaetano Borriello, Carl Ebeling:
Mesh Routing Topologies for Multi-FPGA Systems. ICCD 1994: 170-177 - [c8]Neil R. McKenzie, Kevin Bolding, Carl Ebeling, Lawrence Snyder:
CRANIUM: An Interface for Message Passing on Adaptive Packet Routing Networks. PCRCW 1994: 266-280 - 1993
- [c7]Miles Ohlrich, Carl Ebeling, Eka Ginting, Lisa Sather:
SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm. DAC 1993: 31-37 - [c6]Brian Lockyear, Carl Ebeling:
The practical application of retiming to the design of high-performance systems. ICCAD 1993: 288-295 - [c5]Kevin Bolding, Sen-Ching S. Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo, Robert Wille:
The chaos router chip: design and implementation of an adaptive router. VLSI 1993: 311-320 - 1992
- [c4]Scott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling:
MONTAGNE: An FPL for Synchronous and Asynchronous Circuits. FPL 1992: 44-51 - 1990
- [j4]Hans J. Berliner, Gordon Goetsch, Murray Campbell, Carl Ebeling:
Measuring the Performance Potential of Chess Programs. Artif. Intell. 43(1): 7-20 (1990)
1980 – 1989
- 1989
- [j3]Hans J. Berliner, Carl Ebeling:
Pattern Knowledge and Search: The SUPREM Architecture. Artif. Intell. 38(2): 161-198 (1989) - [j2]Tony DeRose, Mary L. Bailey, Bill Barnard, Robert Cypher, David Dobrikin, Carl Ebeling, Smaragda Konstantinidou, Larry McMurchie, Haim Mizrahi, Bill Yost:
Apex: two architectures for generating parametric curves and surfaces. Vis. Comput. 5(5): 264-276 (1989) - [c3]Carl Ebeling, Zhanbing Wu:
WireLisp: combining graphics and procedures in a circuit specification language. ICCAD 1989: 322-325 - 1988
- [c2]Carl Ebeling:
GeminiII: a second generation layout validation program. ICCAD 1988: 322-325 - 1986
- [j1]Hans J. Berliner, Carl Ebeling:
The SUPREM Architecture: A New Intelligent Paradigm. Artif. Intell. 28(1): 3-8 (1986) - 1984
- [c1]Carl Ebeling, Andrew J. Palay:
The Design and Implementation of a VLSI Chess Move Generator. ISCA 1984: 74-80
Coauthor Index
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