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ORCID2. FPL 1992: Vienna, Austria
- Herbert Grünbacher, Reiner W. Hartenstein:
Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31 - September 2, 1992, Selected Papers. Lecture Notes in Computer Science 705, Springer 1993, ISBN 3-540-57091-8
Invited Papers
- Günter Biehl:
Overview of Complex Array-Based PLDs. 1-10 - Jouni Isoaho, Arto Nummela, Hannu Tenhunen:
Technologies and Utilization fo Field Programmable Gate Arrays. 11-25 - Alberto L. Sangiovanni-Vincentelli:
Some Considerations on Field-Programmable Gate Arrays and Their Impact on System Design. 26-34
Architectures
- Bradly K. Fawcett:
SRAM-Based FPLs Ease System Verification. 35-43 - Scott Hauck, Gaetano Borriello, Steven M. Burns, Carl Ebeling:
MONTAGNE: An FPL for Synchronous and Asynchronous Circuits. 44-51 - Dwight D. Hill, Barry K. Britton, William Oswald, Nam Sung Woo, Satwant Singh, Che-Tsung Chen, Bob Krambeck:
ORCA: A New Architecture for High-Performance FPLs. 52-60
Tools
- Masahiro Fujita, Yuji Kukimoto:
Patching Method for Lookup-Table Type FPLs. 61-70 - Dave Allen:
Automatic One-Hot Re-Encoding for FPLs. 71-77 - Li-Fei Wu, Marek A. Perkowski:
Minimization of Permuted Reed-Muller Trees for Cellular Logic. 78-87 - David C. Blight, Robert D. McLeod:
Self-Organizing Kohonen Maps for FPL Placement. 88-95 - Peter Poechmueller, Hans-Jürgen Herpel, Manfred Glesner, Fang Longsen:
High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment. 96-105
Rapid Prototyping
- Naohisa Ohta, Kazuhisa Yamada, Akihiro Tsutsui, Hiroshi Nakada:
New Application of FPLs to Programmable Digital Communication Cirucits. 106-111 - Georg J. Kempa, Peter Jung:
FPL Based Logic Synthesis of Squarers Using VHDL. 112-123 - Hartmut Surmann, Ansgar Ungering, Karl Goser:
Optimized Fuzzy Controller Architecture for Field Programmable Gate Arrays. 124-133 - Lennart Lindh, Klaus D. Müller-Glaser, Hans Rauch, Frank Stanischewski:
A Real-Time Kernel - Rapid Prototyping with VHDL and FPLs. 134-145 - Herbert Grünbacher, Alexander Jaud:
JAPROC - An 8 bit Micro Controller Design and Its Test Environment. 146-151
FPGA-Based Computer Architecture and Accelerators
- Beat Heeb, Cuno Pfister:
Chameleon: A Workstation of a Different Colour. 152-161 - Paul Shaw, George J. Milne:
A Highly Parallel FPL-Based Machine and Its Formal Verification. 162-173 - Arno Kunzmann:
FPL Based Self-Test with Deterministic Test Patterns. 174-182 - Dzung T. Hoang, Daniel P. Lopresti:
FPGA Implementation of Systolic Sequence Alignment. 183-191 - Erik Brunvand:
Using FPLs to Prototoype a Self-Timed Computer. 192-198 - Arne Linde, Tomas Nordström, Mikael Taveniku:
Using FPLs to Implement a Reconfigurable Highly Parallel Computer. 199-210 - Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt:
Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. 211-217
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