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ORCIDYuji Kukimoto
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2020 – today
- 2024
[c18]Wuxi Li
, Yuji Kukimoto, Grégory Servel, Ismail Bustany, Mehrdad E. Dehkordi:
Calibration-Based Differentiable Timing Optimization in Non-linear Global Placement. ISPD 2024: 31-39
2000 – 2009
- 2002
- [c17]Pinhong Chen, Yuji Kukimoto, Kurt Keutzer:
Refining switching window by time slots for crosstalk noise calculation. ICCAD 2002: 583-586 - [c16]Pinhong Chen, Yuji Kukimoto, Chin-Chi Teng, Kurt Keutzer:
On convergence of switching windows computation in presence of crosstalk noise. ISPD 2002: 84-89
1990 – 1999
- 1999
- [c15]Yuji Kukimoto, Robert K. Brayton:
Timing-safe false path removal for combinational modules. ICCAD 1999: 544-550 - 1998
- [c14]Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar:
Delay-Optimal Technology Mapping by DAG Covering. DAC 1998: 348-351 - [c13]Yuji Kukimoto, Robert K. Brayton:
Hierarchical Functional Timing Analysis. DAC 1998: 580-585 - [c12]Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton:
Combinational Verification based on High-Level Functional Specifications. DATE 1998: 803-808 - 1997
- [c11]Yuji Kukimoto, Robert K. Brayton:
Exact Required Time Analysis via False Path Detection. DAC 1997: 220-225 - [c10]Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton:
Approximate timing analysis of combinational circuits under the XBD0 model. ICCAD 1997: 176-181 - 1996
- [c9]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS: A System for Verification and Synthesis. CAV 1996: 428-432 - [c8]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS. FMCAD 1996: 248-256 - 1994
- [c7]Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton:
A redesign technique for combinational circuits based on gate reconnections. ICCAD 1994: 632-637 - 1992
- [c6]Masahiro Fujita, Yuji Kukimoto:
Patching Method for Lookup-Table Type FPLs. FPL 1992: 61-70 - [c5]Yuji Kukimoto, Masahiro Fujita:
Rectification method for lookup-table type FPGA's. ICCAD 1992: 54-61 - 1991
- [c4]Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen:
Application of Boolean Unification to Combinational Logic Synthesis. ICCAD 1991: 510-513 - 1990
- [c3]Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka:
A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. CAV 1990: 76-85 - [c2]Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka:
A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio. CAV (DIMACS/AMS volume) 1990: 493-504 - [c1]Hiroshi Nakamura, Yuji Kukimoto, Masahiro Fujita, Hidehiko Tanaka:
Practical design assistance at register transfer level using a data path verifier. ICCD 1990: 99-102
Coauthor Index
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