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Adnan Aziz
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2020 – today
- 2024
- [c74]Danning Xie, Jiannan Wang, Hung Viet Pham, Lin Tan, Yu Guo, Adnan Aziz, Erik Meijer:
CEDAR: Continuous Testing of Deep Learning Libraries. SANER 2024: 371-382 - 2023
- [i3]Yueming Hao, Xu Zhao, Bin Bao, David Berard, Will Constable, Adnan Aziz, Xu Liu:
TorchBench: Benchmarking PyTorch with High API Surface Coverage. CoRR abs/2304.14226 (2023) - 2022
- [i2]Newsha Ardalani, Carole-Jean Wu, Zeliang Chen, Bhargav Bhushanam, Adnan Aziz:
Understanding Scaling Laws for Recommendation Models. CoRR abs/2208.08489 (2022) - 2021
- [j17]Lukasz Wesolowski, Bilge Acun, Valentin Andrei, Adnan Aziz, Gisle Dankel, Christopher Gregg, Xiaoqiao Meng, Cyril Meurillon, Denis Sheahan, Lei Tian, Janet Yang, Peifeng Yu, Kim M. Hazelwood:
Datacenter-Scale Analysis and Optimization of GPU Machine Learning Workloads. IEEE Micro 41(5): 101-112 (2021)
2010 – 2019
- 2018
- [c73]Waldemar Hartwig, Christina Klüver, Adnan Aziz, Dirk Hoffstadt:
Classification of SIP Attack Variants with a Hybrid Self-enforcing Network. ICANN (2) 2018: 456-466 - [c72]Ekaterina Volodina, Adnan Aziz, Erwin P. Rathgeb, Tobias Hoßfeld:
Application of Visual Analysis to Detect and Analyze Patterns in VoIP Attack Traffic. TrustCom/BigDataSE 2018: 260-268 - 2016
- [r4]Adnan Aziz, Amit Prakash:
Binary Decision Graph. Encyclopedia of Algorithms 2016: 216-220 - [r3]Adnan Aziz, Amit Prakash:
Symbolic Model Checking. Encyclopedia of Algorithms 2016: 2178-2182 - 2015
- [c71]Markus Gruber, Dirk Hoffstadt, Adnan Aziz, Florian Fankhauser, Christian Schanes, Erwin P. Rathgeb, Thomas Grechenig:
Global VoIP security threats - large scale validation based on independent honeynets. Networking 2015: 1-9 - 2014
- [c70]Adnan Aziz, Dirk Hoffstadt, Erwin P. Rathgeb, Thomas Dreibholz:
A distributed infrastructure to analyse SIP attacks in the Internet. Networking 2014: 1-9 - 2013
- [c69]Adnan Aziz, Dirk Hoffstadt, Sebastian Ganz, Erwin P. Rathgeb:
Development and Analysis of Generic VoIP Attack Sequences Based on Analysis of Real Attack Traffic. TrustCom/ISPA/IUCC 2013: 675-682
2000 – 2009
- 2009
- [c68]Stephen Bijansky, Sae Kyu Lee, Adnan Aziz:
TuneLogic: Post-silicon tuning of dual-Vdd designs. ISQED 2009: 394-400 - 2008
- [c67]Stephen Bijansky, Adnan Aziz:
TuneFPGA: post-silicon tuning of dual-Vdd FPGAs. DAC 2008: 796-799 - [c66]Jason Baumgartner, Hari Mony, Adnan Aziz:
Optimal Constraint-Preserving Netlist Simplification. FMCAD 2008: 1-9 - [c65]Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham:
Adaptive SRAM memory for low power and high yield. ICCD 2008: 176-181 - [r2]Amit Prakash, Adnan Aziz:
Binary Decision Graph. Encyclopedia of Algorithms 2008 - [r1]Amit Prakash, Adnan Aziz:
Symbolic Model Checking. Encyclopedia of Algorithms 2008 - 2007
- [c64]Fadi A. Zaraket, John Pape, Adnan Aziz, Margarida F. Jacome, Sarfraz Khurshid:
Global Optimization of Compositional Systems. FMCAD 2007: 93-100 - [c63]Hani H. Saleh, Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.:
Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine. ICCD 2007: 7-12 - [c62]Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid:
Sequential Circuits for Relational Analysis. ICSE 2007: 13-22 - [c61]Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, Yehia Massoud:
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations. ISQED 2007: 873-878 - [c60]Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid:
Sequential circuits for program analysis. ASE 2007: 114-123 - [c59]Ashish Kumar Singh, Hady Ali Zeineddine, Adnan Aziz, Sriram Vishwanath, Michael Orshansky:
A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions. NANOARCH 2007: 15-20 - [c58]Xiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud:
Implementing DSP Algorithms with On-Chip Networks. NOCS 2007: 307-316 - [c57]Bassam Jamil Mohd, Earl E. Swartzlander Jr., Adnan Aziz:
The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm. VLSI-SoC (Selected Papers) 2007: 1-22 - [c56]Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr.:
The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. VLSI-SoC 2007: 194-199 - [i1]Ashish Kumar Singh, Adnan Aziz, Sriram Vishwanath, Michael Orshansky:
Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies. CoRR abs/cs/0703102 (2007) - 2006
- [b1]Jun Yuan, Carl Pixley, Adnan Aziz:
Constraint-based verification. Springer 2006, ISBN 978-0-387-25947-5, pp. I-XII, 1-253 - [c55]Xiang Wu, Amit Prakash, Marghoob Mohiyuddin, Adnan Aziz:
Scheduling Traffic Matrices On General Switch Fabrics. Hot Interconnects 2006: 87-92 - [c54]Mosin Mondal, Xiang Wu, Adnan Aziz, Yehia Massoud:
Reliability Analysis for On-chip Networks under RC Interconnect Delay Variation. Nano-Net 2006: 1-5 - [c53]Baker Mohammad, Paul Bassett, Jacob A. Abraham, Adnan Aziz:
Cache Organization for Embeded Processors: CAM-vs-SRAM. SoCC 2006: 299-302 - 2005
- [c52]Hari Mony, Jason Baumgartner, Adnan Aziz:
Exploiting Constraints in Transformation-Based Verification. CHARME 2005: 269-284 - [c51]Fadi A. Zaraket, Jason Baumgartner, Adnan Aziz:
Scalable compositional minimization via static analysis. ICCAD 2005: 1060-1067 - 2004
- [j16]Jun Yuan, Adnan Aziz, Carl Pixley, Ken Albin:
Simplifying Boolean constraint solving for random simulation-vector generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3): 412-420 (2004) - [c50]Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Wayne H. Wolf:
Synthesizing interconnect-efficient low density parity check codes. DAC 2004: 488-491 - [c49]Amit Prakash, Adnan Aziz, Vijaya Ramachandran:
Randomized Parallel Schedulers for Switch-Memory-Switch Routers: Analysis and Numerical Studies. INFOCOM 2004: 2026-2037 - 2003
- [j15]Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal:
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. Formal Methods Syst. Des. 22(3): 205-224 (2003) - [j14]Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz:
An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists. Formal Methods Syst. Des. 23(1): 39-65 (2003) - [j13]Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz:
A high-performance architecture and BDD-based synthesis methodology for packet classification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 698-709 (2003) - [j12]Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton:
Sequential optimization in the absence of global reset. ACM Trans. Design Autom. Electr. Syst. 8(2): 222-251 (2003) - [c48]Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley:
Constraint synthesis for environment modeling in functional verification. DAC 2003: 296-299 - [c47]Jun Yuan, Carl Pixley, Adnan Aziz, Ken Albin:
A Framework for Constrained Functional Verification. ICCAD 2003: 142-145 - [c46]Adnan Aziz, Amit Prakash, Vijaya Ramachandran:
A near optimal scheduler for switch-memory-switch routers. SPAA 2003: 343-352 - 2002
- [j11]Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Formula-Dependent Equivalence for Compositional CTL Model Checking. Formal Methods Syst. Des. 21(2): 193-224 (2002) - [c45]Shashank Gupta, Adnan Aziz:
Multicast Scheduling for Switches with Multiple Input-Queues. Hot Interconnects 2002: 28-36 - [c44]Amit Prakash, Adnan Aziz:
A Middle Ground between CAMs and DAGs for High-Speed Packet Classification. Hot Interconnects 2002: 89-94 - [c43]Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley:
Simplifying Boolean constraint solving for random simulation-vector generation. ICCAD 2002: 123-127 - [c42]Sadia Sharif, Adnan Aziz, Amit Prakash:
An O(log2N) parallel algorithm for output queuing. INFOCOM 2002: 1623-1629 - [c41]Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz:
A Reconfigurable Architecture and Associated Synthesis Methodology for High Speed Packet Classification. IWLS 2002: 97-102 - [c40]Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley:
Simplifying Constraint Solving in Random Simulation Generation. IWLS 2002: 185-190 - [c39]Jun Yuan, Kurt Shultz, John Havlicek, Ken Albin, Adnan Aziz:
A Method for Synthesizing Boolean Constrains. IWLS 2002: 351-353 - [c38]Malay K. Ganai, Adnan Aziz:
Improved SAT-Based Bounded Reachability Analysis. ASP-DAC/VLSI Design 2002: 729-734 - 2001
- [j10]Malay K. Ganai, Praveen Yalagandula, Adnan Aziz, Andreas Kuehlmann, Vigyan Singhal:
SIVA: A System for Coverage-Directed State Space Search. J. Electron. Test. 17(1): 11-27 (2001) - [j9]Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton:
Theory of safe replacements for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 249-265 (2001) - [j8]Adnan Aziz, James H. Kukula, Thomas R. Shiple, Jun Yuan:
Efficient control state-space search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 332-336 (2001) - [j7]Hai Zhou, Adnan Aziz:
Buffer minimization in pass transistor logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 693-697 (2001) - [j6]Tai-Hung Liu, Adnan Aziz, Vigyan Singhal:
Optimizing designs containing black boxes. ACM Trans. Design Autom. Electr. Syst. 6(4): 591-601 (2001) - [c37]I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong:
Integrated power supply planning and floorplanning. ASP-DAC 2001: 589-594 - [c36]Malay K. Ganai, Adnan Aziz:
Rarity based guided state space search. ACM Great Lakes Symposium on VLSI 2001: 97-102 - [c35]Amit Prakash, Adnan Aziz:
OC-3072 packet classification using BDDs and pipelined SRAMs. Hot Interconnects 2001: 15-20 - 2000
- [j5]Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz:
Automatic Vector Generation Using Constraints and Biasing. J. Electron. Test. 16(1-2): 107-120 (2000) - [j4]Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz:
Simultaneous routing and buffer insertion with restrictions onbuffer locations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7): 819-824 (2000) - [j3]Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential synthesis using S1S. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(10): 1149-1162 (2000) - [j2]Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton:
Model-checking continous-time Markov chains. ACM Trans. Comput. Log. 1(1): 162-170 (2000) - [c34]Jason Baumgartner, Anson Tripp, Adnan Aziz, Vigyan Singhal, Flemming Andersen:
An Abstraction Algorithm for the Verification of Generalized C-Slow Designs. CAV 2000: 5-19 - [c33]Praveen Yalagandula, Adnan Aziz, Vigyan Singhal:
Automatic Lighthouse Generation for Directed State Space Search. DATE 2000: 237-242 - [c32]I-Min Liu, Adnan Aziz, D. F. Wong:
Meeting Delay Constraints in DSM by Minimal Repeater Insertion. DATE 2000: 436-440 - [c31]I-Min Liu, Adnan Aziz:
Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing. ICCD 2000: 209-214 - [c30]I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong:
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. ISPD 2000: 33-38 - [c29]Hai Zhou, Adnan Aziz:
Buffer minimization in pass transistor logic. ISPD 2000: 105-110
1990 – 1999
- 1999
- [j1]Adnan Aziz, Felice Balarin, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Equivalences for Fair Kripke Structures. Chic. J. Theor. Comput. Sci. 1999 (1999) - [c28]Jason Baumgartner, Tamir Heyman, Vigyan Singhal, Adnan Aziz:
Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists. CAV 1999: 72-83 - [c27]Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz:
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. DAC 1999: 96-99 - [c26]Malay K. Ganai, Adnan Aziz, Andreas Kuehlmann:
Enhancing Simulation with BDDs and ATPG. DAC 1999: 385-390 - [c25]Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz:
Modeling design constraints and biasing in simulation using BDDs. ICCAD 1999: 584-590 - [c24]I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou:
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. ICCD 1999: 210-215 - [c23]Srivatsan Srinivasan, Parminder Singh Chhabra, Praveen Kumar Jaini, Adnan Aziz, Lizy Kurian John:
Formal Verification of a Snoop-Based Cache Coherence Protocol Using Symbolic Model Checking. VLSI Design 1999: 288-293 - [c22]Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns:
Performance Driven Synthesis for Pass-Transistor Logic. VLSI Design 1999: 372-377 - 1998
- [c21]Anuj Goel, Khurram Sajid, Hai Zhou, Adnan Aziz, Vigyan Singhal:
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. CAV 1998: 244-255 - [c20]Adnan Aziz, James H. Kukula, Thomas R. Shiple:
Hybrid Verification Using Saturated Simulation. DAC 1998: 615-618 - [c19]Yufeng Luo, Tjahjadi Wongsonegoro, Adnan Aziz:
Hybrid Techniques for Fast Functional Simulation. DAC 1998: 664-667 - [c18]James H. Kukula, Thomas R. Shiple, Adnan Aziz:
Techniques for Implicit State Enumeration of EFSMs. FMCAD 1998: 469-482 - [c17]Rajat Chaudhry, Tai-Hung Liu, Adnan Aziz, Jeffrey L. Burns:
Area-oriented synthesis for pass-transistor logic. ICCD 1998: 160-167 - 1997
- [c16]Jun Yuan, Jian Shen, Jacob A. Abraham, Adnan Aziz:
On Combining Formal and Informal Verification. CAV 1997: 376-387 - [c15]Tai-Hung Liu, Khurram Sajid, Adnan Aziz, Vigyan Singhal:
Optimizing Designs Containing Black Boxes. DAC 1997: 113-116 - [c14]Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert K. Brayton, Adnan Aziz, Alberto L. Sangiovanni-Vincentelli:
Sequential optimisation without state space exploration. ICCAD 1997: 208-215 - 1996
- [c13]Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton:
Verifying Continuous Time Markov Chains. CAV 1996: 269-276 - [c12]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS: A System for Verification and Synthesis. CAV 1996: 428-432 - [c11]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS. FMCAD 1996: 248-256 - 1995
- [c10]Adnan Aziz, Vigyan Singhal, Felice Balarin:
It Usually Works: The Temporal Logic of Stochastic Systems. CAV 1995: 155-165 - [c9]Adnan Aziz, Felice Balarin, Robert K. Brayton, Marika Domenica Di Benedetto, Alexander Saldanha:
Supervisory Control of Finite State Machines. CAV 1995: 279-292 - [c8]Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton:
Exploiting power-up delay for sequential optimization. EURO-DAC 1995: 54-59 - [c7]Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential synthesis using S1S. ICCAD 1995: 612-617 - 1994
- [c6]Adnan Aziz, Thomas R. Shiple, Vigyan Singhal:
Formula-Dependent Equivalence for Compositional CTL Model Checking. CAV 1994: 324-337 - [c5]Adnan Aziz, Serdar Tasiran, Robert K. Brayton:
BDD Variable Ordering for Interacting Finite State Machines. DAC 1994: 283-288 - [c4]Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
HSIS: A BDD-Based Environment for Formal Verification. DAC 1994: 454-459 - [c3]Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Equivalences for Fair Kripke Structures. ICALP 1994: 364-375 - [c2]Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton:
Multi-level synthesis for safe replaceability. ICCAD 1994: 442-449 - [c1]Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton:
Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. ICCD 1994: 255-261
Coauthor Index
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