default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID34th DAC 1997: Anaheim, California, USA
- Ellen J. Yoffa, Giovanni De Micheli, Jan M. Rabaey:
Proceedings of the 34st Conference on Design Automation, Anaheim, California, USA, Anaheim Convention Center, June 9-13, 1997. ACM Press 1997, ISBN 0-89791-920-3
Panel: An Executive View of EDA Industry
Sequential Synthesis
- Naresh Maheshwari, Sachin S. Sapatnekar:
An Improved Algorithm for Minimum-Area Retiming. 2-7 - Ellen Sentovich, Horia Toma, Gérard Berry:
Efficient Latch Optimization Using Exclusive Sets. 8-11 - Diana Marculescu
, Radu Marculescu, Massoud Pedram:
Sequence Compaction for Probabilistic Analysis of Finite-State Machines. 12-15 - Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella:
Synthesis of Speed-Independent Circuits from STG-Unfolding Segment. 16-21 - Luca Benini, Enrico Macii, Massimo Poncino:
Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control. 22-27
Interconnect Modeling
- Ibrahim M. Elfadel, David D. Ling:
Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect Networks. 28-33 - Kevin J. Kerns, Andrew T. Yang:
Preservation of Passivity During RLC Network Reduction via Split Congruence Transformations. 34-39 - Keith Nabors, Tze-Ting Fang, Hung-Wen Chang, Kenneth S. Kundert:
Lumped Interconnect Models Via Gaussian Quadrature. 40-45 - Florentin Dartu, Lawrence T. Pileggi:
Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. 46-51
Novel Techniques for Software Scheduling
- Felice Balarin, Alberto L. Sangiovanni-Vincentelli:
Schedule Validation for Embedded Reactive Real-Time Systems. 52-57 - Yosef Gavriel Tirat-Gefen, Diógenes Cecilio da Silva Jr., Alice C. Parker:
Incorporating Imprecise Computation into System-Level Design of Application-Specific Heterogeneous Multiprocessors. 58-63 - Marleen Adé, Rudy Lauwereins, J. A. Peperstraete:
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets. 64-69 - Stan Y. Liao, Steven W. K. Tjiang, Rajesh K. Gupta:
An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment. 70-75
Embedded Tutorial: Tools and Methodologies for Low Power Design
- Jerry Frenkil:
Tools and Methodologies for Low Power Design. 76-81
Panel: Low-Power Design Tools - Where Is the Impact?
Simulation Techniques for Microprocessors
- Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung:
A C-Based RTL Design Verification Methodology for Complex Microprocessor. 83-88 - Jörg A. Walter, Jens Leenstra, Gerhard Döttling, Bernd Leppla, Hans-Jürgen Münster, Kevin W. Kark, Bruce Wile:
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors. 89-94 - Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh:
Efficient Testing of Clock Regenerator Circuits in Scan Designs. 95-100 - Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen:
A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications. 101-106
Combinational Logic Synthesis
- Yibin Ye, Kaushik Roy:
A Graph-Based Synthesis Algorithm for AND/XOR Networks. 107-112 - Tai-Hung Liu, Khurram Sajid, Adnan Aziz, Vigyan Singhal:
Optimizing Designs Containing Black Boxes. 113-116 - Stan Y. Liao, Srinivas Devadas:
Solving Covering Problems Using LPR-Based Lower Bounds. 117-120 - Olivier Coudert:
Exact Coloring of Real-Life Graphs is Easy. 121-126
Interconnect Parasitic Extraction
- E. Aykut Dengi, Ronald A. Rohrer:
Hierarchical 2-D Field Solution for Capacitance Extraction for VLSI Interconnect Modeling. 127-132 - Michael W. Beattie, Lawrence T. Pileggi:
Bounds for BEM Capacitance Extraction. 133-136 - Zhijiang He, Mustafa Celik, Lawrence T. Pileggi:
SPIE: Sparse Partial Inductance Extraction. 137-140 - Sharad Kapur, Jinsong Zhao:
A Fast Method of Moments Solver for Efficient Parameter Extraction of MCMs. 141-146
Advances in Timing Analysis for Embedded Software
- Sharad Malik, Margaret Martonosi, Yau-Tsun Steven Li:
Static Timing Analysis of Embedded Software. 147-152 - Yanbing Li, Wayne H. Wolf:
A Task-Level Hierarchical Memory Model for System Synthesis of Multiprocessors. 153-156 - Rajeshkumar S. Sambandam, Xiaobo Hu:
Predicting Timing Behavior in Architectural Design Exploration of Real-Time Embedded Systems. 157-160
Applications of Formal Verification
- Kyle L. Nelson, Alok Jain, Randal E. Bryant:
Formal Verification of a Superscalar Execution Unit. 161-166 - Manish Pandey, Richard Raimi, Randal E. Bryant, Magdy S. Abadir:
Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation. 167-172 - Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl Pixley:
Formal Verification of FIRE: A Case Study. 173-177
System-Level Exploration and Refinement
- James A. Rowson, Alberto L. Sangiovanni-Vincentelli:
Interface-Based Design. 178-183 - Robert H. Klenke, Moshe Meyassed, James H. Aylor, Barry W. Johnson, Ramesh Rao, Anup Ghosh:
An Integrated Design Environment for Performance and Dependability Analysis. 184-189 - Ole Bentz, Jan M. Rabaey, David Lidsky:
A Dynamic Design Estimation and Exploration Environment. 190-195
Binary Decision Diagrams
- Srilatha Manne, Dirk Grunwald, Fabio Somenzi:
Remembrance of Things Past: Locality and Memory in BDDs. 196-201 - Christoph Meinel, Fabio Somenzi, Thorsten Theobald:
Linear Sifting of Decision Diagrams. 202-207 - Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan:
Safe BDD Minimization Using Don't Cares. 208-213
Timing Analysis
- John Lillis, Chung-Kuan Cheng:
Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion. 214-219 - Yuji Kukimoto, Robert K. Brayton:
Exact Required Time Analysis via False Path Detection. 220-225 - Tod Amon, Gaetano Borriello, Taokuan Hu, Jiwen Liu:
Symbolic Timing Verification of Timing Diagrams using Presburger Formulas. 226-231
Tutorial: Code Generation for Core Processors
- Peter Marwedel:
Code Generation for Core Processors. 232-237
Panel: Physical Design and Synthesis: Merge or Die!
System-Level Optimization and Verification
- Ajay J. Daga, Peter Suaris:
Interface Timing Verification Drives System Design. 240-245 - Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura:
Memory-CPU Size Optimization for Embedded System Designs. 246-251 - Miodrag Potkonjak, Kyosun Kim, Ramesh Karri:
Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study. 252-257
Formal Verification
- Robert P. Kurshan:
Formal Verification in a Commercial Setting. 258-262 - Andreas Kuehlmann, Florian Krohm:
Equivalence Checking Using Cuts and Heaps. 263-268
Analog Simulation
- Jaijeet S. Roychowdhury:
Efficient Methods for Simulating Highly Nonlinear Multi-Rate Circuits. 269-274 - Michael W. Tian, Chuanjin Richard Shi:
Rapid Frequency-Domain Analog Fault Simulation Under Parameter Tolerances. 275-280 - Salvador Mir, Adoración Rueda, Thomas Olbrich, Eduardo J. Peralías, José Luis Huertas:
SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems. 281-286
Software Synthesis for Embedded Systems
- Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas:
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures. 287-292 - Markus Willems, Volker Bürsgens, Holger Keding, Thorsten Grötker, Heinrich Meyr:
System Level Fixed-Point Design Based on an Interpolative Approach. 293-298 - George Hadjiyiannis, Silvina Hanono, Srinivas Devadas:
ISDL: An Instruction Set Description Language for Retargetability. 299-302 - Mark R. Hartoog, James A. Rowson, Prakash D. Reddy, Soumya Desai, Douglas D. Dunlop, Edwin A. Harcourt, Neeti Khullar:
Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign. 303-306
Experiences in System Design and Education at Universities
- Hugo De Man:
Education for the Deep Submicron Age: Business as Usual? 307-312 - Robert W. Brodersen:
InfoPad - An Experiment in System Level Design and Integration. 313-314 - Asim Smailagic, Daniel P. Siewiorek, Richard L. Martin, John Stivoric:
Very Rapid Prototyping of Wearable Computers: A Case Study of Custom versus Off-the-Shelf Design Methodologies. 315-320
Standard Cell and Physical Design Methods
- Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz:
CAD at the Design-Manufacturing Interface. 321-326 - Mohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernandez, Larry G. Jones:
CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries. 327-332 - Donald G. Baltus, Thomas Varga, Robert C. Armstrong, John Duh, T. G. Matheson:
Developing a Concurrent Methodology for Standard-Cell Library Generation. 333-336 - John F. Croix, D. F. Wong:
A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis. 337-340
Modeling and Transformations in Synthesis
- Jian Li, Rajesh K. Gupta:
Limited Exception Modeling and Its Use in Presynthesis Optimizations. 341-346 - Inki Hong, Darko Kirovski, Miodrag Potkonjak:
Potential-Driven Statistical Ordering of Transformations. 347-352 - Kyosun Kim, Ramesh Karri, Miodrag Potkonjak:
Synthesis of Application Specific Programmable Processors. 353-358 - Jeffrey Walrath, Ranga Vemuri:
Symbolic Evaluation of Performance Models for Tradeoff Visualization. 359-364
Statistical Power Estimation Techniques
- Subodh Gupta, Farid N. Najm:
Power Macromodeling for High Level Power Estimation. 365-370 - Chih-Shun Ding, Qing Wu, Cheng-Ta Hsieh, Massoud Pedram:
Statistical Estimation of the Cumulative Distribution Function for Power Dissipation in VLSI Cirucits. 371-376 - Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang:
Statistical Estimation of Average Power Dissipation in Sequential Circuits. 377-382 - Angela Krstic, Kwang-Ting Cheng:
Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits. 383-388
Co-Simulation
- Claudio Passerone, Luciano Lavagno, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli:
Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis. 389-394 - Ken Hines, Gaetano Borriello:
Dynamic Communication Models in Embedded System Co-Simulation. 395-400
Panel: Challenges in Worldwide IP Reuse with Embedded Tutorial: Applying VSIA Standards to System on Chip Design
Emerging Technologies and Architectures for Low Power
- Pankaj Pant, Vivek De, Abhijit Chatterjee:
Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks. 403-408 - James T. Kao, Anantha P. Chandrakasan, Dimitri A. Antoniadis:
Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology. 409-414 - Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha P. Chandrakasan:
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT. 415-420 - Chi-Ying Tsui, Kai-Keung Chan, Qing Wu, Chih-Shun Ding, Massoud Pedram:
A Power Estimation Framework for Designing Low Power Portable Video Applications. 421-424 - Qi Wang, Sarma B. K. Vrudhula, Shantanu Ganguly:
An Investigation of Power Delay Trade-Offs on PowerPC Circuits. 425-428
High Level Synthesis for Low Power
- Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi:
Power Management Techniques for Control-Flow Intensive Designs. 429-434 - Catherine H. Gebotys:
Low Energy Memory and Register Allocation Using Network Flow. 435-440 - Daehong Kim, Kiyoung Choi:
Power-conscious High Level Synthesis Using Loop Folding. 441-445
Module Generation
- Martin Lefebvre, David Marple, Carl Sechen:
The Future of Custom Cell Generation in Physical Synthesis. 446-451 - Avaneendra Gupta, John P. Hayes:
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells. 452-455 - Jaewon Kim, Sung-Mo Kang:
An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design. 456-459 - John Lakos:
Technology Retargeting for IC Layout. 460-465
BIST and DFT
- Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng:
A Test Synthesis Approach to Reducing BALLAST DFT Overhead. 466-471 - Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska:
STARBIST: Scan Autocorrelated Random Pattern Generation. 472-477 - Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Sudipta Bhawmik:
A Hybrid Algorithm for Test Point Selection for Scan-Based BIST. 478-483
Panel: Hardware/Software Co-Verification
DSP & Telecommunication System Design
- Wolfgang Meyer, Andrew Seawright, Fumiya Tada:
Design and Synthesis of Array Structured Telecommunication Processing Applications. 486-491 - C. Hein, J. Pridgen, W. Kline:
RASSP Virtual Prototyping of DSP Systems. 492-497 - Claus Schneider:
A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders. 498-503
Embedded Tutorial: High-Level Power Modeling, Estimation, and Optimization
- Enrico Macii, Massoud Pedram, Fabio Somenzi:
High-Level Power Modeling, Estimation, and Optimization. 504-511
Advances in Partitioning
- Ming-Ter Kuo, Chung-Kuan Cheng:
A Network Flow Approach for Hierarchical Tree Partitioning. 512-517 - Wen-Jong Fang, Allen C.-H. Wu:
Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. 518-521 - Helena Krupnova, Ali Abbara, Gabriele Saucier:
A Hierarchy-Driven FPGA Partitioning Method. 522-525 - George Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar:
Multilevel Hypergraph Partitioning: Application in VLSI Domain. 526-529 - Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng:
Multilevel Circuit Partitioning. 530-533
Processor Test techniques
- Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. 534-539 - Laurence Goodby, Alex Orailoglu:
Frequency-Domain Compatibility in Digital Filter BIST. 540-545 - Mehrdad Nourani, Joan Carletta, Christos A. Papachristou:
A Scheme for Integrated Controller-Datapath Fault Testing. 546-551
Panel: The Next Generation HDL
Design Processes and Frameworks
- Hemang Lavana, Amit Khetawat, Franc Brglez, Krzysztof Kozminski:
Executable Workflows: A Paradigm for Collaborative Design on the Internet. 553-558 - Donald R. Cottrell:
Electronic Component Information Exchange (ECIX). 559-563 - Bernd Schürmann, Joachim Altmeyer:
Modeling Design Tasks and Tools: The Link Between Product and Flow Model. 564-569
Probabilistic Models of Input Data for Efficient Power Estimation
- Radu Marculescu, Diana Marculescu, Massoud Pedram:
Hierarchical Sequence Compaction for Power Estimation. 570-575 - Cheng-Ta Hsieh, Massoud Pedram, Gaurav Mehta, Fred Rastgar:
Profile-Driven Program Synthesis for Evaluation of System Power Dissipation. 576-581 - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Analytical Estimation of Transition Activity From Word-Level Signal Statistics. 582-587
Hot Topics in Routing
- Charles J. Alpert, Anirudh Devgan:
Wire Segmenting for Improved Buffer Insertion. 588-593 - Andrew B. Kahng, Chung-Wen Albert Tsao:
More Practical Bounded-Skew Clock Routing. 594-599 - Chin-Chih Chang, Jason Cong:
An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization. 600-603 - Chung-Ping Chen, D. F. Wong:
Optimal Wire-Sizing Function with Fringing Capacitance Consideration. 604-607
Test Generation and Fault Simulation
- Irith Pomeranz, Sudhakar M. Reddy:
Fault Simulation under the Multiple Observation Time Approach using Backward Implications. 608-613 - Seongmoon Wang, Sandeep K. Gupta:
ATPG for Heat Dissipation Minimization During Scan Testing. 614-619 - Oriol Roig, Jordi Cortadella, Marco A. Peña, Enric Pastor:
Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits. 620-625
Panel: The Road Ahead in CPLD & FPGA Design Methodology
Deep Submicron Modeling and Analysis
- Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen:
Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. 627-632 - Cristiano Forzan, Bruno Franzini, Carlo Guardiani:
Accurate and Efficient Macromodel of Submicron Digital Standard Cells. 633-637 - Howard H. Chen, David D. Ling:
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design. 638-643
Technology-Dependent Optimization for Performance and Power
- Jason Cong, Chang Wu:
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. 644-649 - Rajendran Panda, Farid N. Najm:
Technology-Dependent Transformations for Low-Power Synthesis. 650-655 - Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Low Power FPGA Design - A Re-engineering Approach. 656-661 - Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska:
Post-Layout Logic Restructuring for Performance Optimization. 662-665 - Masako Murofushi, Takashi Ishioka, Masami Murakata, Takashi Mitsuhashi:
Layout Driven Re-synthesis for Low Power Consumption LSIs. 666-669
CAD Issues for Micro-Electro-Mechanical Systems
- William C. Tang:
Overview of Microelectromechanical Systems and Design Processes. 670-673 - Jean-Michel Karam, Bernard Courtois, Hicham Boutamine, P. Drake, András Poppe, Vladimír Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner:
CAD and Foundries for Microsystems. 674-679 - Tamal Mukherjee, Gary K. Fedder:
Structured Design of Microelectromechanical Systems. 680-685 - Narayan R. Aluru, James White:
Algorithms for Coupled Domain MEMS Simulation. 686-690
Hardware/Software Partitioning
- Jörg Henkel, Rolf Ernst:
A Hardware/Software Partitioner Using a Dynamically Determined Granularity. 691-696 - Darko Kirovski, Miodrag Potkonjak:
System-Level Synthesis of Low-Power Hard Real-Time Systems. 697-702 - Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha:
COSYN: Hardware-Software Co-Synthesis of Embedded Systems. 703-708 - Samir Agrawal, Rajesh K. Gupta:
Data-Flow Assisted Behavioral Partitioning for Embedded Systems. 709-712 - Smita Bakshi, Daniel Gajski:
Hardware/Software Partitioning and Pipelining. 713-716
Embedded Tutorial: Chip Parasitic Extraction and Signal Integrity Verification
- Wayne Wei-Ming Dai:
Chip Parasitic Extraction and Signal Integrity Verification (Extended Abstract). 717-719
Panel: Noise and Signal Integrity in Deep Submicron Design
Designing High Performance and Low Power Microprocessors Using Full Custom Techniques
- William J. Grundmann, Dan Dobberpuhl, Randy L. Allmon, Nicholas L. Rethman:
Designing High Performance CMOS Microprocessors Using Full Custom Techniques. 722-727
Formal Verification techniques
- Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer:
Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits. 728-733 - Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee:
An Efficient Assertion Checker for Combinational Properties. 734-739 - Aarti Gupta, Sharad Malik, Pranav Ashar:
Toward Formalizing a Validation Methodology Using Simulation Coverage. 740-745
Placement Techniques
- Jens Vygen:
Algorithms for Large-Scale Flat Placement. 746-751 - Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Igor L. Markov, Kenneth Yan:
Quadratic Placement Revisited. 752-757 - Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez:
Unification of Budgeting and Placement. 758-761 - Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng:
Cluster Refinement for Block Placement. 762-765
Panel: The EDA Startup Experience: Financing the Venture
Heterogeneous System Analysis
- Steven P. Levitan, Philippe J. Marchand, Timothy P. Kurzweg, M. A. Rempel, Donald M. Chiarulli, C. Fan, F. B. McCormick:
Computer-Aided Design of Free-Space Opto-Electronic Systems. 768-773 - Matthias Bauer, Wolfgang Ecker:
Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach. 774-779 - Clifford Liem, Marco Cornero, Miguel Santana, Pierre G. Paulin, Ahmed Amine Jerraya, Jean-Marc Gentit, Jean Lopez, Xavier Figari, Laurent Bergher:
Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio Processor. 780-785
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-19 22:18 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
