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ORCIDRobert K. Brayton
Person information
- affiliation: University of California, Berkeley, USA
- award (2006): Paris Kanellakis Award
- award (2006): IEEE Emanuel R. Piore Award
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2020 – today
- 2024
[i4]Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli, Robert K. Brayton:
Practical Boolean Decomposition for Delay-driven LUT Mapping. CoRR abs/2406.06241 (2024)- 2022
- [j61]Siang-Yun Lee
, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli:
A Simulation-Guided Paradigm for Logic Synthesis and Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2573-2586 (2022) - 2021
- [c249]He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amarù, Alan Mishchenko, Robert K. Brayton:
Deep Integration of Circuit Simulator and SAT Solver. DAC 2021: 877-882 - 2020
- [i3]Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli:
Simulation-Guided Boolean Resubstitution. CoRR abs/2007.02579 (2020)
2010 – 2019
- 2019
- [j60]Yu-Yun Dai, Robert K. Brayton:
Verification and Synthesis of Clock-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 366-379 (2019) - 2018
- [c248]Bruno de O. Schmitt, Alan Mishchenko, Robert K. Brayton:
SAT-based area recovery in structural technology mapping. ASP-DAC 2018: 586-591 - [c247]Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton:
Efficient computation of ECO patch functions. DAC 2018: 51:1-51:6 - [c246]Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic:
Canonical computation without canonical representation. DAC 2018: 52:1-52:6 - [c245]Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli:
Practical exact synthesis. DATE 2018: 309-314 - [c244]Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Improvements to boolean resynthesis. DATE 2018: 755-760 - [p2]Yu-Yun Dai, Robert K. Brayton:
Identifying Transparent Logic in Gate-Level Circuits. Advanced Logic Synthesis 2018: 103-124 - 2017
- [c243]Bruno de O. Schmitt, Alan Mishchenko, Victor N. Kravets, Robert K. Brayton, André Inácio Reis:
Fast-extract with cube hashing. ASP-DAC 2017: 145-150 - [c242]Yen-Sheng Ho, Alan Mishchenko, Robert K. Brayton:
Property directed reachability with word-level abstraction. FMCAD 2017: 132-139 - [c241]Yu-Yun Dai, Robert K. Brayton:
Circuit recognition with deep learning. HOST 2017: 162 - [c240]Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Enabling exact delay synthesis. ICCAD 2017: 352-359 - 2016
- [j59]Hamid Savoj, Alan Mishchenko, Robert K. Brayton:
m-Inductive Property of Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(6): 919-930 (2016) - [c239]Yen-Sheng Ho, Pankaj Chauhan, Pritam Roy, Alan Mishchenko, Robert K. Brayton:
Efficient uninterpreted function abstraction and refinement for word-level model checking. FMCAD 2016: 65-72 - [c238]Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne:
Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD 2016: 4 - [c237]Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli:
Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT 2016: 212-227 - [c236]Valeriy Balabanov, Jie-Hong Roland Jiang, Christoph Scholl, Alan Mishchenko, Robert K. Brayton:
2QBF: Challenges and Solutions. SAT 2016: 453-469 - 2015
- [j58]Robert K. Brayton, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa:
Design Automation of Electronic Systems: Past Accomplishments and Challenges Ahead [Scanning the Issue]. Proc. IEEE 103(11): 1952-1957 (2015) - [j57]Tiziano Villa, Alexandre Petrenko, Nina Yevtushenko, Alan Mishchenko, Robert K. Brayton:
Component-Based Design by Solving Language Equations. Proc. IEEE 103(11): 2152-2167 (2015) - [c235]Yu-Yun Dai, Kei-Yong Khoo, Robert K. Brayton:
Sequential equivalence checking of clock-gated circuits. DAC 2015: 51:1-51:6 - [c234]Anna Bernasconi, Robert K. Brayton, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
Bi-Decomposition Using Boolean Relations. DSD 2015: 72-78 - [c233]Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton:
Simulation Graphs for Reverse Engineering. FMCAD 2015: 152-159 - [c232]Alan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene:
Technology Mapping into General Programmable Cells. FPGA 2015: 70-73 - [c231]Giovanni Castagnetti, Matteo Piccolo, Tiziano Villa, Nina Yevtushenko, Robert K. Brayton, Alan Mishchenko:
Automated Synthesis of Protocol Converters with BALM-II. SEFM Workshops 2015: 281-296 - 2014
- [j56]Hamid Savoj, Alan Mishchenko, Robert K. Brayton:
Sequential Equivalence Checking for Clock-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 305-317 (2014) - [c230]Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury:
ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. ASP-DAC 2014: 250-255 - [c229]Aadithya V. Karthik, David Soloveichik, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury:
NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract). BCB 2014: 623-624 - 2013
- [c228]Alan Mishchenko, Niklas Eén, Robert K. Brayton, Michael L. Case, Pankaj Chauhan, Nikhil Sharma:
A semi-canonical form for sequential AIGs. DATE 2013: 797-802 - [c227]Alan Mishchenko, Niklas Eén, Robert K. Brayton, Jason Baumgartner, Hari Mony, Pradeep Kumar Nalla:
GLA: gate-level abstraction revisited. DATE 2013: 1399-1404 - [c226]Jiang Long, Robert K. Brayton, Michael L. Case:
LEC: Learning Driven Data-path Equivalence Checking. DIFTS@FMCAD 2013 - [c225]Sayak Ray, Robert K. Brayton:
Ranking structure in communication fabrics. MEMOCODE 2013: 65-74 - 2012
- [c224]Sayak Ray, Robert K. Brayton:
Scalable progress verification in credit-based flow-control systems. DATE 2012: 905-910 - [c223]Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen:
Mapping into LUT structures. DATE 2012: 1579-1584 - 2011
- [j55]Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton:
Automating Logic Transformations With Approximate SPFDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 651-664 (2011) - [j54]Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis. ACM Trans. Reconfigurable Technol. Syst. 4(4): 34:1-34:23 (2011) - [c222]Niklas Eén, Alan Mishchenko, Robert K. Brayton:
Efficient implementation of property directed reachability. FMCAD 2011: 125-134 - [c221]Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton:
Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. DIFTS@FMCAD 2011 - [c220]Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets:
Delay optimization using SOP balancing. ICCAD 2011: 375-382 - 2010
- [j53]Robert K. Brayton, Jason Cong:
NSF Workshop on EDA: Past, Present, and Future (Part 1). IEEE Des. Test Comput. 27(2): 68-74 (2010) - [j52]Robert K. Brayton, Jason Cong:
NSF Workshop on EDA: Past, Present, and Future (Part 2). IEEE Des. Test Comput. 27(3): 62-74 (2010) - [c219]Robert K. Brayton, Alan Mishchenko:
ABC: An Academic Industrial-Strength Verification Tool. CAV 2010: 24-40 - [c218]Hamid Savoj, David Berthelot, Alan Mishchenko, Robert K. Brayton:
Combinational techniques for sequential equivalence checking. FMCAD 2010: 145-149 - [c217]Alan Mishchenko, Robert K. Brayton, Stephen Jang:
Global delay optimization using structural choices. FPGA 2010: 181-184 - [p1]Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Yves Crama, Peter L. Hammer:
Synthesis of Multilevel Boolean Networks. Boolean Models and Methods 2010: 675-722
2000 – 2009
- 2009
- [c216]Hari Mony, Jason Baumgartner, Alan Mishchenko, Robert K. Brayton:
Speculative reduction-based scalable redundancy identification. DATE 2009: 1674-1679 - [c215]Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith:
Sequential logic rectifications with approximate SPFDs. DATE 2009: 1698-1703 - [c214]Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis. FPGA 2009: 151-160 - [c213]Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton:
SmartOpt: an industrial strength framework for logic synthesis. FPGA 2009: 237-240 - 2008
- [j51]Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli:
Compositionally Progressive Solutions of Synchronous FSM Equations. Discret. Event Dyn. Syst. 18(1): 51-89 (2008) - [c212]Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton:
Scalable min-register retiming under timing and initializability constraints. DAC 2008: 534-539 - [c211]Michael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton:
Merging nodes under sequential observability. DAC 2008: 540-545 - [c210]Michael L. Case, Alan Mishchenko, Robert K. Brayton, Jason Baumgartner, Hari Mony:
Invariant-Strengthened Elimination of Dependent State Elements. FMCAD 2008: 1-9 - [c209]Alan Mishchenko, Robert K. Brayton:
Recording Synthesis History for Sequential Verification. FMCAD 2008: 1-8 - [c208]Alan Mishchenko, Robert K. Brayton, Satrajit Chatterjee:
Boolean factoring and decomposition of logic networks. ICCAD 2008: 38-44 - [c207]Alan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang:
Scalable and scalably-verifiable sequential synthesis. ICCAD 2008: 234-241 - [c206]Fan Mo, Robert K. Brayton:
Placement based multiplier rewiring for cell-based designs. ICCAD 2008: 430-433 - 2007
- [j50]Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
Improvements to Technology Mapping for LUT-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 240-253 (2007) - [c205]Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton:
Automating Logic Rectification by Approximate SPFDs. ASP-DAC 2007: 402-407 - [c204]Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann:
On Resolution Proofs for Combinational Equivalence. DAC 2007: 600-605 - [c203]Michael L. Case, Alan Mishchenko, Robert K. Brayton:
Automated Extraction of Inductive Invariants to Aid Model Checking. FMCAD 2007: 165-172 - [c202]Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton:
Fast Minimum-Register Retiming via Binary Maximum-Flow. FMCAD 2007: 181-187 - [c201]Tiziano Villa, Svetlana Zharikova, Nina Yevtushenko, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
A new algorithm for the largest compositionally progressive solution of synchronous language equations. ACM Great Lakes Symposium on VLSI 2007: 441-444 - [c200]Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton:
Combinational and sequential mapping with priority cuts. ICCAD 2007: 354-361 - [c199]Fan Mo, Robert K. Brayton:
A simultaneous bus orientation and bused pin flipping algorithm. ICCAD 2007: 386-389 - [c198]Fan Mo, Robert K. Brayton:
Semi-detailed bus routing with variation reduction. ISPD 2007: 143-150 - [i2]Alan Mishchenko, Robert K. Brayton:
SAT-Based Complete Don't-Care Computation for Network Optimization. CoRR abs/0710.4695 (2007) - [i1]Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations. CoRR abs/0710.4743 (2007) - 2006
- [j49]Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske:
Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 743-755 (2006) - [j48]Alan Mishchenko, Robert K. Brayton:
A theory of nondeterministic networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 977-999 (2006) - [j47]Jie-Hong Roland Jiang, Robert K. Brayton:
Retiming and Resynthesis: A Complexity Perspective. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2674-2686 (2006) - [j46]Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam:
Reducing Structural Bias in Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2894-2903 (2006) - [c197]Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske:
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. DAC 2006: 510-515 - [c196]Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
DAG-aware AIG rewriting a fresh look at combinational logic synthesis. DAC 2006: 532-535 - [c195]Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
Improvements to technology mapping for LUT-based FPGAs. FPGA 2006: 41-49 - [c194]Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton:
Factor cuts. ICCAD 2006: 143-150 - [c193]Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén:
Improvements to combinational equivalence checking. ICCAD 2006: 836-843 - 2005
- [c192]Yinghua Li, Alex Kondratyev, Robert K. Brayton:
Gaining Predictability and Noise Immunity in Global Interconnects. ACSD 2005: 176-185 - [c191]Alan Mishchenko, Robert K. Brayton:
SAT-Based Complete Don't-Care Computation for Network Optimization. DATE 2005: 412-417 - [c190]Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations. DATE 2005: 418-423 - [c189]Yinghua Li, Alex Kondratyev, Robert K. Brayton:
Synthesis methodology for built-in at-speed testing. ICCAD 2005: 183-188 - [c188]Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam:
Reducing structural bias in technology mapping. ICCAD 2005: 519-526 - 2004
- [j45]Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
SPFD-based wire removal in standard-cell and network-of-PLA circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1020-1030 (2004) - [c187]Jie-Hong Roland Jiang, Robert K. Brayton:
Functional Dependency for Verification Reduction. CAV 2004: 268-280 - [c186]Fan Mo, Robert K. Brayton:
A timing-driven module-based chip design flow. DAC 2004: 67-70 - [c185]Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
On breakable cyclic definitions. ICCAD 2004: 411-418 - [c184]Satrajit Chatterjee, Robert K. Brayton:
A new incremental placement algorithm and its application to congestion-aware divisor extraction. ICCAD 2004: 541-548 - 2003
- [j44]Jie-Hong Roland Jiang, Robert K. Brayton:
On the verification of sequential equivalence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 686-697 (2003) - [j43]Fan Mo, Robert K. Brayton:
PLA-based regular structures and their synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 723-729 (2003) - [j42]Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert K. Brayton:
Sequential optimization in the absence of global reset. ACM Trans. Design Autom. Electr. Syst. 8(2): 222-251 (2003) - [c183]Yunjian Jiang, Robert K. Brayton:
Don't cares in logic minimization of extended finite state machines. ASP-DAC 2003: 809-815 - [c182]Yunjian Jiang, Slobodan Matic, Robert K. Brayton:
Generalized cofactoring for logic function evaluation. DAC 2003: 155-158 - [c181]Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary. DATE 2003: 10752-10757 - [c180]Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli:
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. DATE 2003: 11154-11155 - [c179]Alan Mishchenko, Robert K. Brayton:
A Theory of Non-Deterministic Networks. ICCAD 2003: 709-717 - [c178]Fan Mo, Robert K. Brayton:
Fishbone: a block-level placement and routing scheme. ISPD 2003: 204-209 - 2002
- [j41]Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Formula-Dependent Equivalence for Compositional CTL Model Checking. Formal Methods Syst. Des. 21(2): 193-224 (2002) - [c177]Massimo Baleani, Frank Gennari, Yunjian Jiang, Yatish Patel, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform. CODES 2002: 151-156 - [c176]Fan Mo, Robert K. Brayton:
River PLAs: a regular circuit structure. DAC 2002: 201-206 - [c175]Yunjian Jiang, Robert K. Brayton:
Software synthesis from synchronous specifications using logic simulation techniques. DAC 2002: 319-324 - [c174]Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton:
Using Problem Symmetry in Search Based Satisfiability Algorithms. DATE 2002: 134-141 - [c173]Fan Mo, Robert K. Brayton:
Whirlpool PLAs: a regular logic structure and their synthesis. ICCAD 2002: 543-550 - [c172]Alan Mishchenko, Robert K. Brayton:
Simplification of non-deterministic multi-valued networks. ICCAD 2002: 557-562 - [c171]Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton:
Topologically constrained logic synthesis. ICCAD 2002: 679-686 - [c170]Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa:
Optimization of Multi-Valued Multi-Level Networks. ISMVL 2002: 168-179 - [c169]Fan Mo, Robert K. Brayton:
Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design. IWLS 2002: 7-12 - [c168]Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton:
Topologically Constrained Logic Synthesis. IWLS 2002: 13-20 - [c167]Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli:
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. IWLS 2002: 45-50 - [c166]Alan Mishchenko, Robert K. Brayton:
A Boolean Paradigm in Multi-Valued Logic Synthesis. IWLS 2002: 173-177 - [c165]Jie-Hong Roland Jiang, Robert K. Brayton:
On the Verification of Sequential Equivalence. IWLS 2002: 307-314 - [c164]Yunjian Jiang, Robert K. Brayton:
Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic. IWLS 2002: 327-332 - [c163]Alan Mishchenko, Robert K. Brayton:
Simplification of Non-Deterministic Multi-Valued Networks. IWLS 2002: 333-338 - [c162]Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary. IWLS 2002: 339-344 - 2001
- [j40]Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani:
Partial-Order Reduction in Symbolic State-Space Exploration. Formal Methods Syst. Des. 18(2): 97-116 (2001) - [j39]Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton:
Theory of safe replacements for sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 249-265 (2001) - [c161]Yunjian Jiang, Robert K. Brayton:
Logic optimization and code generation for embedded control applications. CODES 2001: 225-229 - [c160]Evguenii I. Goldberg, Mukul R. Prasad, Robert K. Brayton:
Using SAT for combinational equivalence checking. DATE 2001: 114-121 - [c159]Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton:
Sequential SPFDs. ICCAD 2001: 84-90 - [c158]Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli:
Solution of Parallel Language Equations for Logic Synthesis. ICCAD 2001: 103- - [c157]Fan Mo, Abdallah Tabbara, Robert K. Brayton:
A Force-Directed Maze Router. ICCAD 2001: 404-407 - [c156]Robert K. Brayton:
Compatible Observability Don't Cares Revisited. ICCAD 2001: 618- - [c155]Fan Mo, Abdallah Tabbara, Robert K. Brayton:
A Timing-Driven Macro-Cell Placement Algorithm. ICCD 2001: 322-327 - 2000
- [j38]Stefano Quer, Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Ellen Sentovich, Robert K. Brayton:
Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks. Formal Methods Syst. Des. 17(2): 107-134 (2000) - [j37]Ralph H. J. M. Otten, Robert K. Brayton:
Performance planning. Integr. 29(1): 1-24 (2000) - [j36]Abdallah Tabbara, Bassam Tabbara, Robert K. Brayton, A. Richard Newton:
Integration of retiming with architectural floorplanning. Integr. 29(1): 25-43 (2000) - [j35]Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Negative thinking in branch-and-bound: the case of unate covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3): 281-294 (2000) - [j34]Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential synthesis using S1S. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(10): 1149-1162 (2000) - [j33]Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton:
Model-checking continous-time Markov chains. ACM Trans. Comput. Log. 1(1): 162-170 (2000) - [c154]Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten:
Area and search space control for technology mapping. DAC 2000: 86-91 - [c153]Fan Mo, Abdallah Tabbara, Robert K. Brayton:
A Force-Directed Macro-Cell Placer. ICCAD 2000: 177-180 - [c152]Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. ICCAD 2000: 412-418 - [c151]Yunjian Jiang, Robert K. Brayton:
Don't Cares and Multi-Valued Logic Network Minimization. ICCAD 2000: 520-525 - [c150]Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. ICCD 2000: 494-503
1990 – 1999
- 1999
- [j32]Adnan Aziz, Felice Balarin, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Equivalences for Fair Kripke Structures. Chic. J. Theor. Comput. Sci. 1999 (1999) - [c149]Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli:
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. DAC 1999: 491-496 - [c148]Abdallah Tabbara, Robert K. Brayton, A. Richard Newton:
Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints. DAC 1999: 725-730 - [c147]Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton:
Using Combinational Verification for Sequential Circuits. DATE 1999: 138-144 - [c146]Yuji Kukimoto, Robert K. Brayton:
Timing-safe false path removal for combinational modules. ICCAD 1999: 544-550 - [c145]Andreas Kuehlmann, Kenneth L. McMillan, Robert K. Brayton:
Probabilistic state space search. ICCAD 1999: 574-579 - [c144]Luca P. Carloni, Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems. VLSI 1999: 346-361 - [c143]Robert K. Brayton, Sunil P. Khatri:
Multi-Valued Logic Synthesis. VLSI Design 1999: 196-105 - [c142]Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential Multi-Valued Network Simplification using Redundancy Removal. VLSI Design 1999: 206-211 - 1998
- [j31]Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Theory and algorithms for face hypercube embedding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(6): 472-488 (1998) - [c141]Zhongcheng Li, Yinghua Min, Robert K. Brayton:
A New Low-Cost Method for Identifying Untestable Path Delay Faults. Asian Test Symposium 1998: 76-81 - [c140]Gurmeet Singh Manku, Ramin Hojati, Robert K. Brayton:
Structural Symmetry and Model Checking. CAV 1998: 159-171 - [c139]Adrian J. Isles, Ramin Hojati, Robert K. Brayton:
Computing Reachable Control States of Systems Modeled with Uninterpreted Functions and Infinite Memory. CAV 1998: 256-267 - [c138]Ralph H. J. M. Otten, Robert K. Brayton:
Planning for Performance. DAC 1998: 122-127 - [c137]Yuji Kukimoto, Robert K. Brayton, Prashant Sawkar:
Delay-Optimal Technology Mapping by DAG Covering. DAC 1998: 348-351 - [c136]Yuji Kukimoto, Robert K. Brayton:
Hierarchical Functional Timing Analysis. DAC 1998: 580-585 - [c135]Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton:
Combinational Verification based on High-Level Functional Specifications. DATE 1998: 803-808 - [c134]Wilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Wireplanning in logic synthesis. ICCAD 1998: 26-33 - [c133]Subarnarekha Sinha, Robert K. Brayton:
Implementation and use of SPFDs in optimizing Boolean networks. ICCAD 1998: 103-110 - [c132]Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton:
On the optimization power of retiming and resynthesis transformations. ICCAD 1998: 402-407 - [c131]Gitanjali Swamy, Stephen A. Edwards, Robert K. Brayton:
Efficient Verification and Synthesis using Design Commonalities. VLSI Design 1998: 542-551 - 1997
- [j30]Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Implicit computation of compatible sets for state minimization of ISFSMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 657-676 (1997) - [j29]Tiziano Villa, Timothy Kam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Explicit and implicit algorithms for binate covering problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 677-691 (1997) - [j28]Tiziano Villa, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Symbolic two-level minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 692-708 (1997) - [j27]Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Theory and algorithms for state minimization of nondeterministic FSMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1311-1322 (1997) - [c130]Serdar Tasiran, Robert K. Brayton:
STARI: A Case Study in Compositional and Hierarchical Timing Verification. CAV 1997: 191-201 - [c129]Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani:
Partial-Order Reduction in Symbolic State Space Exploration. CAV 1997: 340-351 - [c128]Yuji Kukimoto, Robert K. Brayton:
Exact Required Time Analysis via False Path Detection. DAC 1997: 220-225 - [c127]Evguenii I. Goldberg, Luca P. Carloni, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Negative thinking by incremental problem solving: application to unate covering. ICCAD 1997: 91-98 - [c126]Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton:
Approximate timing analysis of combinational circuits under the XBD0 model. ICCAD 1997: 176-181 - [c125]Amit Mehrotra, Shaz Qadeer, Vigyan Singhal, Robert K. Brayton, Adnan Aziz, Alberto L. Sangiovanni-Vincentelli:
Sequential optimisation without state space exploration. ICCAD 1997: 208-215 - [c124]Evguenii I. Goldberg, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
A fast and robust exact algorithm for face embedding. ICCAD 1997: 296-303 - [c123]Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Reachability analysis using partitioned-ROBDDs. ICCAD 1997: 388-393 - [c122]Rajeev K. Ranjan, Wilsin Gosti, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions. ICCD 1997: 344-351 - [c121]Zhongcheng Li, Yuhong Zhao, Yinghua Min, Robert K. Brayton:
Timed Binary Decision Diagrams. ICCD 1997: 352-357 - [c120]Zhongcheng Li, Robert K. Brayton, Yinghua Min:
Efficient Identification of Non-Robustly Untestable Path Delay Faults. ITC 1997: 992-997 - 1996
- [j26]Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton:
Permissible functions for multioutput components in combinational logic optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7): 732-744 (1996) - [j25]William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Valid clock frequencies and their computation in wavepipelined circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7): 791-807 (1996) - [j24]Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Combinational test generation using satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1167-1176 (1996) - [c119]Adnan Aziz, Kumud Sanwal, Vigyan Singhal, Robert K. Brayton:
Verifying Continuous Time Markov Chains. CAV 1996: 269-276 - [c118]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS: A System for Verification and Synthesis. CAV 1996: 428-432 - [c117]Serdar Tasiran, Rajeev Alur, Robert P. Kurshan, Robert K. Brayton:
Verifying Abstractions of Timed Systems. CONCUR 1996: 546-562 - [c116]Sunil P. Khatri, Amit Narayan, Sriram C. Krishnan, Kenneth L. McMillan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Engineering Change in a Non-Deterministic FSM Setting. DAC 1996: 451-456 - [c115]Jagesh V. Sanghavi, Rajeev K. Ranjan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
High Performance BDD Package By Exploiting Memory Hiercharchy. DAC 1996: 635-640 - [c114]Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer, Robert K. Brayton, Ellen Sentovich:
Incremental re-encoding for symbolic traversal of product machines. EURO-DAC 1996: 158-163 - [c113]Ramin Hojati, Adrian J. Isles, Desmond Kirkpatrick, Robert K. Brayton:
Verification Using Uninterpreted Functions and Finite Instantiations. FMCAD 1996: 218-232 - [c112]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu-Tsung Cheng, Stephen A. Edwards, Sunil P. Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali Swamy, Tiziano Villa:
VIS. FMCAD 1996: 248-256 - [c111]Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita:
Decomposition Techniques for Efficient ROBDD Construction. FMCAD 1996: 419-434 - [c110]Vigyan Singhal, Sharad Malik, Robert K. Brayton:
The case for retiming with explicit reset circuitry. ICCAD 1996: 618-625 - [c109]Ramin Hojati, Sriram C. Krishnan, Robert K. Brayton:
Early Quantification and Partitioned Transition Relations. ICCD 1996: 12-19 - [c108]Rajeev K. Ranjan, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Binary decision diagrams on network of workstation. ICCD 1996: 358-364 - [c107]Shaz Qadeer, Robert K. Brayton, Vigyan Singhal:
Latch Redundancy Removal Without Global Reset. ICCD 1996: 432-439 - [c106]Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design 1996: 249-253 - 1995
- [j23]Ramin Hojati, Robert K. Brayton:
An Environment for Formal Verification Based on Symbolic Computations. Formal Methods Syst. Des. 6(2): 191-216 (1995) - [j22]Hervé J. Touati, Robert K. Brayton, Robert P. Kurshan:
Testing Language Containment for omega-Automata Using BDD's. Inf. Comput. 118(1): 101-109 (1995) - [j21]Robert K. Brayton, Ellen M. Sentovich:
Network Hierarchies and Node Minimization. IEICE Trans. Inf. Syst. 78-D(3): 199-208 (1995) - [j20]William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Delay fault coverage, test set size, and performance trade-offs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1): 32-44 (1995) - [j19]Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
An efficient heuristic procedure for solving the state assignment problem for event-based specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1): 45-60 (1995) - [c105]Ramin Hojati, Robert K. Brayton:
Automatic Datapath Abstraction In Hardware Systems. CAV 1995: 98-113 - [c104]Sriram C. Krishnan, Anuj Puri, Robert K. Brayton, Pravin Varaiya:
The Rabin Index and Chain Automata, with Applications to Automatas and Games. CAV 1995: 253-266 - [c103]Adnan Aziz, Felice Balarin, Robert K. Brayton, Marika Domenica Di Benedetto, Alexander Saldanha:
Supervisory Control of Finite State Machines. CAV 1995: 279-292 - [c102]Serdar Tasiran, Ramin Hojati, Robert K. Brayton:
Language containment of non-deterministic omega-automata. CHARME 1995: 261-277 - [c101]Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton:
The Validity of Retiming Sequential Circuits. DAC 1995: 316-321 - [c100]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Decomposition of logic functions for minimum transition activity. ED&TC 1995: 404-410 - [c99]Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton:
Exploiting power-up delay for sequential optimization. EURO-DAC 1995: 54-59 - [c98]Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential synthesis using S1S. ICCAD 1995: 612-617 - [c97]Huey-Yih Wang, Robert K. Brayton:
Multi-level logic optimization of FSM networks. ICCAD 1995: 728-735 - [c96]Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Implicit state minimization of non-deterministic FSMs. ICCD 1995: 250-257 - [c95]Gitanjali Swamy, Robert K. Brayton, Vigyan Singhal:
Incremental methods for FSM traversal. ICCD 1995: 590-595 - [c94]Vigyan Singhal, Robert K. Brayton, Carl Pixley:
Power-Up Delay for Retiming Digital Circuits. ISCAS 1995: 566-569 - [c93]Sriram C. Krishnan, Anuj Puri, Robert K. Brayton:
Structural Complexity of Omega-Automata. STACS 1995: 143-156 - [c92]Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Functional clock schedule optimization. VLSI Design 1995: 93-98 - 1994
- [b2]William K. C. Lam, Robert K. Brayton:
Timed Boolean functions - a unified formalism for exact timing analysis. The Kluwer international series in engineering and computer science 270, Kluwer 1994, ISBN 978-0-7923-9454-9, pp. I-XX, 1-273 - [j18]Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Satisfaction of input and output encoding constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5): 589-602 (1994) - [j17]Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Circuit structure relations to redundancy and delay. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(7): 875-883 (1994) - [j16]Cho W. Moon, Paul R. Stephan, Robert K. Brayton:
Specification, synthesis, and verification of hazard-free asynchronous circuits. J. VLSI Signal Process. 7(1-2): 85-100 (1994) - [c91]William K. C. Lam, Robert K. Brayton:
Criteria for the Simple Path Property in Timed Automata. CAV 1994: 27-40 - [c90]Ramin Hojati, Robert B. Mueller-Thuns, Robert K. Brayton:
Improving Language Containment Using Fairness Graphs. CAV 1994: 391-403 - [c89]William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Exact Minimum Cycle Times for Finite State Machines. DAC 1994: 100-105 - [c88]Thomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton:
Heuristic Minimization of BDDs Using Don't Cares. DAC 1994: 225-231 - [c87]Adnan Aziz, Serdar Tasiran, Robert K. Brayton:
BDD Variable Ordering for Interacting Finite State Machines. DAC 1994: 283-288 - [c86]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Optimum Functional Decomposition Using Encoding. DAC 1994: 408-414 - [c85]Alexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Performance Optimization Using Exact Sensitization. DAC 1994: 425-429 - [c84]Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
HSIS: A BDD-Based Environment for Formal Verification. DAC 1994: 454-459 - [c83]Huey-Yih Wang, Robert K. Brayton:
Permissible Observability Relations in FSM Networks. DAC 1994: 677-683 - [c82]Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
A Fully Implicit Algorithm for Exact State Minimization. DAC 1994: 684-690 - [c81]Yosinori Watanabe, Robert K. Brayton:
State Minimization of Pseudo Non-Deterministic FSM's. EDAC-ETC-EUROASIC 1994: 184-191 - [c80]Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Equivalences for Fair Kripke Structures. ICALP 1994: 364-375 - [c79]Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton:
Multi-level synthesis for safe replaceability. ICCAD 1994: 442-449 - [c78]Gitanjali Swamy, Robert K. Brayton:
Incremental formal design verification. ICCAD 1994: 458-465 - [c77]Yuji Kukimoto, Masahiro Fujita, Robert K. Brayton:
A redesign technique for combinational circuits based on gate reconnections. ICCAD 1994: 632-637 - [c76]Ellen Sentovich, Robert K. Brayton:
An Exact Optimization of Two-Level Acyclic Sequential Circuits. ICCD 1994: 242-249 - [c75]Adnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton:
Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. ICCD 1994: 255-261 - [c74]Sriram C. Krishnan, Anuj Puri, Robert K. Brayton:
Deterministic w Automata vis-a-vis Deterministic Buchi Automata. ISAAC 1994: 378-386 - 1993
- [j15]Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Two-Level Minimization of Multivalued Functions with Large Offsets. IEEE Trans. Computers 42(11): 1325-1342 (1993) - [j14]Hervé J. Touati, Robert K. Brayton:
Computing the initial states of retimed circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1): 157-162 (1993) - [j13]Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5): 568-578 (1993) - [j12]Yosinori Watanabe, Robert K. Brayton:
Heuristic minimization of multiple-valued relations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(10): 1458-1472 (1993) - [j11]Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
ESPRESSO-SIGNATURE: a new exact minimizer for logic functions. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 432-440 (1993) - [c73]Robert K. Brayton:
Logic Synthesis and Design Verification. CAV 1993: 1-2 - [c72]Ramin Hojati, Robert K. Brayton, Robert P. Kurshan:
BDD-Based Debugging Of Design Using Language Containment and Fair CTL. CAV 1993: 41-58 - [c71]William K. C. Lam, Robert K. Brayton:
Alternating RQ Timed Automata. CAV 1993: 237-252 - [c70]Cho W. Moon, Robert K. Brayton:
Elimination of Dynamic hazards by Factoring. DAC 1993: 7-13 - [c69]William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions. DAC 1993: 128-134 - [c68]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential Synthesis for Table Look Up Programmable Gate Arrays. DAC 1993: 224-229 - [c67]Yusuke Matsunaga, Patrick C. McGeer, Robert K. Brayton:
On Computing the Transitive Closure of a State Transition Relation. DAC 1993: 260-265 - [c66]William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Delay Fault Coverage and Performance Tradeoffs. DAC 1993: 446-452 - [c65]Ramin Hojati, Thomas R. Shiple, Robert K. Brayton, Robert P. Kurshan:
A Unified Approach to Language Containment and Fair CTL Model Checking. DAC 1993: 475-481 - [c64]Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Resynthesis of Multi-Phase Pipelines. DAC 1993: 490-496 - [c63]Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Espresso-Signature: A New Exact Minimizer for Logic Functions. DAC 1993: 618-624 - [c62]Eric Felt, Gary York, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Dynamic variable reordering for BDD minimization. EURO-DAC 1993: 130-135 - [c61]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Cube-packing and two-level minimization. ICCAD 1993: 115-122 - [c60]Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Minimum padding to satisfy short path constraints. ICCAD 1993: 156-161 - [c59]Yosinori Watanabe, Robert K. Brayton:
The maximum set of permissible behaviors for FSM networks. ICCAD 1993: 316-320 - [c58]Huey-Yih Wang, Robert K. Brayton:
Input don't care sequences in FSM networks. ICCAD 1993: 321-328 - [c57]Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton:
Logic Optimization with Multi-Output Gates. ICCD 1993: 416-420 - [c56]Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton:
Heuristic Minimization of Synchronous Relations. ICCD 1993: 428-433 - [c55]Paul R. Stephan, Robert K. Brayton:
Physically Realizable Gate Models. ICCD 1993: 442-445 - [c54]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. ICCD 1993: 505-512 - [c53]Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Minimization of Logic Functions Using Essential Signature Sets. VLSI Design 1993: 323-328 - 1992
- [j10]Sharad Malik, Luciano Lavagno, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Symbolic minimization of multilevel logic and the input encoding problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(7): 825-843 (1992) - [c52]Thomas R. Shiple, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton:
Automatic Reduction in CTL Compositional Model Checking. CAV 1992: 234-247 - [c51]Ramin Hojati, Hervé J. Touati, Robert P. Kurshan, Robert K. Brayton:
Efficient omega-Regular Language Containment. CAV 1992: 396-409 - [c50]Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation. DAC 1992: 173-176 - [c49]Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited. DAC 1992: 245-248 - [c48]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
An Improved Synthesis Algorithm for Multiplexor-Based PGA's. DAC 1992: 380-386 - [c47]Narendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
On the Temporal Equivalence of Sequential Circuits. DAC 1992: 405-409 - [c46]Luciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Solving the State Assignment Problem for Signal Transition Graphs. DAC 1992: 568-572 - [c45]Hamid Savoj, Mário J. Silva, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Boolean matching in logic synthesis. EURO-DAC 1992: 168-174 - [c44]Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Graph algorithms for clock schedule optimization. ICCAD 1992: 132-136 - [c43]Massimiliano Chiodo, Thomas R. Shiple, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton:
Automatic compositional minimization in CTL model checking. ICCAD 1992: 172-178 - [c42]William K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Valid clocking in wavepipelined circuits. ICCAD 1992: 518-525 - [c41]Ellen Sentovich, Kanwar Jit Singh, Cho W. Moon, Hamid Savoj, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential Circuit Design Using Synthesis and Optimization. ICCD 1992: 328-333 - [c40]William K. C. Lam, Robert K. Brayton:
On Relationship Between ITE and BDD. ICCD 1992: 448-451 - [c39]Paul T. Gutwin, Patrick C. McGeer, Robert K. Brayton:
Delay Prediction for Technology-Independent Logic Equations. ICCD 1992: 468-471 - 1991
- [j9]Sharad Malik, Ellen M. Sentovich, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Retiming and resynthesis: optimizing sequential networks with combinational techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(1): 74-84 (1991) - [j8]Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Reduced offsets for minimization of binary-valued functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4): 413-426 (1991) - [c38]Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
A Framework for Satisfying Input and Output Encoding Constraints. DAC 1991: 170-175 - [c37]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
On Clustering for Minimum Delay/Area. ICCAD 1991: 6-9 - [c36]Yosinori Watanabe, Robert K. Brayton:
Heuristic Minimazation of Multiple-Valued Relations. ICCAD 1991: 126-129 - [c35]Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. ICCAD 1991: 180-183 - [c34]Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Sartaj Sahni:
Performance Enhancement through the Generalized Bypass Transform. ICCAD 1991: 184-187 - [c33]Hervé J. Touati, Hamid Savoj, Robert K. Brayton:
Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing. ICCAD 1991: 188-191 - [c32]Cho W. Moon, Paul R. Stephan, Robert K. Brayton:
Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications. ICCAD 1991: 322-325 - [c31]Hamid Savoj, Robert K. Brayton, Hervé J. Touati:
Extracting Local Don't Cares for Network Optimization. ICCAD 1991: 514-517 - [c30]Hamid Savoj, Robert K. Brayton:
Observability Relations and Observability Don't Cares. ICCAD 1991: 518-521 - [c29]Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Improved Logic Synthesis Algorithms for Table Look Up Architectures. ICCAD 1991: 564-567 - [c28]Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. ICCAD 1991: 572-575 - [c27]Yosinori Watanabe, Robert K. Brayton:
Incremental Synthesis for Engineering Changes. ICCD 1991: 40-43 - [c26]Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Retiming of Circuits with Single Phase Transparent Latches. ICCD 1991: 86-89 - [c25]Abdul A. Malik, David Harrison, Robert K. Brayton:
Three-Level Decomposition with Application to PLDs. ICCD 1991: 628-633 - [c24]Ellen Sentovich, Robert K. Brayton:
Preserving Don't Care Conditions During Retiming. VLSI 1991: 461-470 - 1990
- [j7]Robert K. Brayton, Gary D. Hachtel, Alberto L. Sangiovanni-Vincentelli:
Multilevel logic synthesis. Proc. IEEE 78(2): 264-300 (1990) - [c23]Patrick C. McGeer, Robert K. Brayton:
Timing Analysis in Precharge/Unate Networks. DAC 1990: 124-129 - [c22]Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
Reduced Offsets for Two-Level Multi-Valued Logic Minimization. DAC 1990: 290-296 - [c21]Hamid Savoj, Robert K. Brayton:
The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks. DAC 1990: 297-301 - [c20]Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Logic Synthesis for Programmable Gate Arrays. DAC 1990: 620-625 - [c19]Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton:
Algorithms for Discrete Function Manipulation. ICCAD 1990: 92-95 - [c18]Hervé J. Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Implicit State Enumeration of Finite State Machines Using BDDs. ICCAD 1990: 130-133 - [c17]Sharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Performance Optimization of Pipelined Circuits. ICCAD 1990: 410-413 - [c16]Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng:
Timing Optimization with Testability Considerations. ICCAD 1990: 460-463 - [c15]Luciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. ICCAD 1990: 560-563 - [c14]Patrick C. McGeer, Robert K. Brayton:
The observability don't-care set and its approximations. ICCD 1990: 45-48
1980 – 1989
- 1989
- [c13]Patrick C. McGeer, Robert K. Brayton:
Efficient Prime Factorization of Logic Expressions. DAC 1989: 221-225 - [c12]Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Multi-level Logic Simplification Using Don't Cares and Filters. DAC 1989: 277-282 - [c11]Patrick C. McGeer, Robert K. Brayton:
Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network. DAC 1989: 561-567 - [c10]Mark Beardslee, Chuck Kring, Rajeev Murgai, Hamid Savoj, Robert K. Brayton, A. Richard Newton:
SLIP: a software environment for system level interactive partitioning. ICCAD 1989: 280-283 - [c9]Robert K. Brayton, Fabio Somenzi:
An exact minimizer for Boolean relations. ICCAD 1989: 316-319 - [c8]Patrick C. McGeer, Robert K. Brayton:
Consistency and observability invariance in multi-level logic synthesis. ICCAD 1989: 426-429 - [c7]Hamid Savoj, Abdul A. Malik, Robert K. Brayton:
Fast two-level logic minimizers for multi-level logic synthesis. ICCAD 1989: 544-547 - [c6]Abdul A. Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Logic minimization for factored forms. ICCD 1989: 396-399 - 1988
- [j6]Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang:
Multi-level logic minimization using implicit don't cares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(6): 723-740 (1988) - [c5]Sharad Malik, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Logic verification using binary decision diagrams in a logic synthesis environment. ICCAD 1988: 6-9 - [c4]Romy L. Bauer, Jiayuan Fang, Antony P.-C. Ng, Robert K. Brayton:
XPSim: a MOS VLSI simulator. ICCAD 1988: 66-69 - [c3]Robert K. Brayton, Ellen M. Sentovich, Fabio Somenzi:
Don't cares and global flow analysis of Boolean networks. ICCAD 1988: 98-101 - [c2]Abdul A. Malik, Robert K. Brayton, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli:
A modified approach to two-level logic minimization. ICCAD 1988: 106-109 - [c1]Kanwar Jit Singh, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Timing optimization of combinational logic. ICCAD 1988: 282-285 - 1987
- [j5]Robert K. Brayton, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang:
MIS: A Multiple-Level Logic Optimization System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(6): 1062-1081 (1987) - 1986
- [j4]Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Correction to "Optimal State Assignment for Finite State Machines". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(1): 239 (1986) - 1985
- [j3]Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Optimal State Assignment for Finite State Machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(3): 269-285 (1985) - 1984
- [b1]Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli:
Logic Minimization Algorithms for VLSI Synthesis. The Kluwer International Series in Engineering and Computer Science 2, Springer 1984, ISBN 978-1-4612-9784-0, pp. 1-193
1960 – 1969
- 1964
- [j2]Robert K. Brayton:
Stability Criteria for Large Networks. IBM J. Res. Dev. 8(4): 466-470 (1964) - 1963
- [j1]Robert K. Brayton, Ralph A. Willoughby:
An Analysis of the Effect of Component Tolerances on the Amplification of the Balanced-Pair Tunnel-Diode Circuit. IEEE Trans. Electron. Comput. 12(3): 269-274 (1963)
Coauthor Index
Jie-Hong Roland Jiang
aka: Jie-Hong R. Jiang
aka: Jie-Hong R. Jiang
[i4] [j61] [c249] [i3] [c248] [c247] [c246] [c245] [c244] [c243] [c242] [c240] [j59] [c239] [c238] [c237] [c236] [j57] [c232] [c231] [j56] [c230] [c229] [c228] [c227] [c223] [j54] [c222] [c221] [c220] [c219] [c218] [c217] [c216] [c214] [c213] [c212] [c211] [c210] [c209] [c208] [c207] [j50] [c204] [c203] [c202] [c200] [i2] [i1] [j49] [j48] [j46] [c197] [c196] [c195] [c194] [c193] [c191] [c190] [c188] [c185] [c181] [c179] [c172] [c171] [c170] [c168] [c166] [c163] [c162]
[j58] [p1] [j51] [c201] [j45] [c180] [j41] [c177] [c167] [c158] [j35] [j34] [c152] [c150] [j32] [c149] [c144] [c142] [j31] [c134] [j30] [j29] [j28] [j27] [c127] [c125] [c124] [c123] [c122] [j25] [j24] [c118] [c116] [c115] [c112] [c111] [c108] [c106] [j20] [j19] [c100] [c98] [c96] [c92] [j18] [j17] [c89] [c88] [c86] [c85] [c84] [c82] [c80] [j15] [j13] [j11] [c69] [c68] [c66] [c64] [c63] [c62] [c61] [c60] [c54] [c53] [j10] [c52] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [j9] [j8] [c38] [c37] [c35] [c34] [c29] [c28] [c26] [j7] [c22] [c20] [c18] [c17] [c16] [c15] [c12] [c6] [j6] [c5] [c2] [c1] [j5] [j4] [j3] [b1]
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