"Sequential Equivalence Checking for Clock-Gated Circuits."

Hamid Savoj, Alan Mishchenko, Robert K. Brayton (2014)

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DOI: 10.1109/TCAD.2013.2284190

access: closed

type: Journal Article

metadata version: 2020-09-24

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Hamid Savoj, Alan Mishchenko, Robert K. Brayton:
Sequential Equivalence Checking for Clock-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 305-317 (2014)

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