default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID23rd ASP-DAC 2018: Jeju, South Korea
- Youngsoo Shin:
23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018. IEEE 2018, ISBN 978-1-5090-0602-1 - Jinjun Xiong:
Tutorial-1: Machine learning and deep learning. - Jeff Burns:
Keynote I: "Designing heterogeneous systems in the AI era: Challenges and opportunities". - Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu
:
Quantized deep neural networks for energy efficient hardware-based inference. 1-8 - Handi Yu, Xin Li:
Intelligent corner synthesis via cycle-consistent generative adversarial networks for efficient validation of autonomous driving systems. 9-15 - Anand Ramachandran, Huiren Li, Eric W. Klee, Steven S. Lumetta, Deming Chen:
Deep Learning for Better Variant Calling for Cancer Diagnosis and Treatment. 16-21 - Zhongyuan Tian, Zhe Wang, Haoran Li, Peng Yang, Rafael Kioji Vivas Maeda, Jiang Xu:
Multi-device collaborative management through knowledge sharing. 22-27 - Yuanjing Shi, Zhaoyan Shen, Zili Shao:
SQLiteKV: An efficient LSM-tree-based SQLite-like database engine for mobile devices. 28-33 - Jian-Hao Huang, Ren-Shuo Liu:
DI-SSD: Desymmetrized interconnection architecture and dynamic timing calibration for solid-state drives. 34-39 - Andreas Grimmer, Berislav Klepic, Tsung-Yi Ho, Robert Wille:
Sound valve-control for programmable microfluidic devices. 40-45 - Guan-Ruei Lu, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen:
Multi-level droplet routing in active-matrix based digital-microfluidic biochips. 46-51 - Vikkitharan Gnanasambandapillai, Arash Bayat, Sri Parameswaran:
MESGA: An MPSoC based embedded system solution for short read genome alignment. 52-57 - Biao Hu, Kai Huang:
Scheduling and shaping of complex task activations for mixed-criticality systems. 58-63 - Wooseok Lee, Reena Panda, Dam Sunwoo, José A. Joao, Andreas Gerstlauer, Lizy K. John:
BUQS: Battery- and user-aware QoS scaling for interactive mobile devices. 64-69 - Hossein Sayadi, Divya Pathak, Ioannis Savidis, Houman Homayoun:
Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning. 70-75 - Anoop Koyily, Satya Venkata Sandeep Avvaru, Chen Zhou, Chris H. Kim, Keshab K. Parhi:
Effect of aging on linear and nonlinear MUX PUFs by statistical modeling. 76-83 - Chenguang Wang, Yici Cai, Qiang Zhou, Haoyi Wang:
ASAX: Automatic security assertion extraction for detecting Hardware Trojans. 84-89 - Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui:
Polymorphic gate based IC watermarking techniques. 90-96 - Qingqing Ma, Chongyan Gu, Neil Hanley, Chenghua Wang, Weiqiang Liu, Máire O'Neill:
A machine learning attack resistant multi-PUF design on FPGA. 97-104 - Chien-Yu Lin, Bo-Cheng Lai:
Supporting compressed-sparse activations and weights on SIMD-like accelerator for sparse convolutional neural networks. 105-110 - Shaahin Angizi, Zhezhi He, Farhana Parveen, Deliang Fan:
IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network. 111-116 - Yi Cai, Tianqi Tang, Lixue Xia, Ming Cheng, Zhenhua Zhu, Yu Wang, Huazhong Yang:
Training low bitwidth convolutional neural network on RRAM. 117-122 - Xizi Chen, Jingbo Jiang, Jingyang Zhu, Chi-Ying Tsui:
A high-throughput and energy-efficient RRAM-based convolutional neural network using data encoding and dynamic quantization. 123-128 - Mingxi Cheng, Ji Li, Shahin Nazarian:
DRL-cloud: Deep reinforcement learning-based resource provisioning and task scheduling for cloud service providers. 129-134 - Rui Wu, M. Ashkan Seyedi, Yuyang Wang, Jared Hulme, Marco Fiorentino, Raymond G. Beausoleil, Kwang-Ting Cheng:
Pairing of microring-based silicon photonic transceivers for tuning power optimization. 135-140 - Xiaoxiao Liu, Wei Wen, Xuehai Qian, Hai Li, Yiran Chen:
Neu-NoC: A high-efficient interconnection network for accelerated neuromorphic systems. 141-146 - Letian Huang, Shuyu Chen, Qiong Wu, Masoumeh Ebrahimi, Junshi Wang, Shuyan Jiang, Qiang Li:
A lifetime-aware mapping algorithm to extend MTTF of Networks-on-Chip. 147-152 - Che-Lun Hsu, Shaofeng Guo, Yibo Lin, Xiaoqing Xu, Meng Li, Runsheng Wang, Ru Huang, David Z. Pan:
Layout-dependent aging mitigation for critical path timing. 153-158 - Yutaka Masuda, Masanori Hashimoto:
MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits. 159-165 - Tin-Yin Lai, Martin D. F. Wong:
A highly compressed timing macro-modeling algorithm for hierarchical and incremental timing analysis. 166-171 - Pei-Yu Lee, Iris Hui-Ru Jiang, Tung-Chieh Chen:
FastPass: Fast timing path search for generalized timing exception handling. 172-177 - Fan Chen, Linghao Song, Yiran Chen:
ReGAN: A pipelined ReRAM-based accelerator for generative adversarial networks. 178-183 - Zhifeng Zhang, Dajiang Zhou, Shihao Wang, Shinji Kimura:
Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA. 184-189 - Canran Jin, Heming Sun, Shinji Kimura:
Sparse ternary connect: Convolutional neural networks using ternarized weights with enhanced sparsity. 190-195 - Pu Zhao, Yanzhi Wang, Naehyuck Chang, Qi Zhu, Xue Lin:
A deep reinforcement learning framework for optimizing fuel economy of hybrid electric vehicles. 196-202 - Nour Sayed, Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM. 203-208 - Sheng Xu, Ying Wang, Yinhe Han, Xiaowei Li:
PIMCH: Cooperative memory prefetching in processing-in-memory architecture. 209-214 - Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, Laxmi Narayan Bhuyan:
CAMO: A novel cache management organization for GPGPUs. 215-220 - Fan Chen, Zheng Li, Wang Kang, Weisheng Zhao, Hai Li, Yiran Chen:
Process variation aware data management for magnetic skyrmions racetrack memory. 221-226 - Shuyan Jiang, Qiong Wu, Shuyu Chen, Junshi Wang, Masoumeh Ebrahimi, Letian Huang, Qiang Li:
Optimizing dynamic mapping techniques for on-line NoC test. 227-232 - Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut Graeb, Ulf Schlichtmann:
On enabling diagnosis for 1-Pin Test fails in an industrial flow. 233-238 - Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler:
Approximation-aware testing for approximate circuits. 239-244 - Kuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A channel-sharable built-in self-test scheme for multi-channel DRAMs. 245-250 - Satwik Patnaik, Johann Knechtel, Mohammed Ashraf, Ozgur Sinanoglu:
Concerted wire lifting: Enabling secure and cost-effective split manufacturing. 251-258 - Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
A conflict-free approach for parallelizing SAT-based de-camouflaging attacks. 259-264 - Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan:
A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion. 265-270 - Yuanqi Shen, Amin Rezaei, Hai Zhou:
A comparative investigation of approximate attacks on logic encryptions. 271-276 - Junghyup Lee, Arup K. George, Minkyu Je:
An ultra-low-noise differential relaxation oscillator based on a swing-boosting scheme. 277-278 - Chiraag Juvekar, Anantha P. Chandrakasan, Joyce Kwong, Hyung-Min Lee:
A nonvolatile flip-flop-enabled cryptographic wireless authentication tag with per-query key update and power-glitch attack countermeasures. 279-280 - Junwon Jeong, Seokhyeon Jeong, Chulwoo Kim, Dennis Sylvester, David T. Blaauw:
A 42nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteries. 281-282 - Dongin Kim, SeongHwan Cho:
A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop. 283-284 - Junmin Jiang, Yan Lu, Xun Liu, Wing-Hung Ki, Philip K. T. Mok, Seng-Pan U, Rui Paulo Martins:
A dual-output SC converter with dynamic power allocation for multicore application processors. 285-286 - Yeonho Lee, Yoonjae Choi, Chulwoo Kim:
12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface. 287-288 - Junmin Jiang, Wing-Hung Ki, Yan Lu:
A digital SC converter with high efficiency and low voltage ripple. 289-290 - Se-un Shin, Sang-Hui Park, Gyu-Hyeong Cho:
A reconfigurable SIMO system with 10-output dual-bus DC-DC converter using the load balancing function in group allocator for diversified load condition. 291-292 - Hyeji Kim, Jinyeon Lim, Yeongmin Lee, Woojin Yun, Young-Gyu Kim, Wonseok Choi, Asim Khan, Muhammad Umar Karim Khan, Said Homidov, Hyun Sang Park, Chong-Min Kyung:
Real-time depth map processor for offset aperture based single camera system. 293-294 - Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Junhua Shen, Chulwoo Kim, Dennis Sylvester, David T. Blaauw, Wanyeong Jung:
Edge pursuit comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC. 295-296 - Sangwoo Lee, Woojin Jo, Seung-Woo Song, Youngcheol Chae:
A 300-pW audio ΑΣ modulator with 100.5-dB DR using dynamic bias inverter. 297-298 - Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi:
An external-capacitor-less high-PSR low-dropout regulator using an adaptive supply-ripple cancellation technique to the body-gate. 299-300 - Dae-Woong Park, Dzuhri Radityo Utomo, Jong-Phil Hong, Sang-Gug Lee:
A 230-260GHz wideband amplifier in 65nm CMOS based on dual-peak Gmax-core. 301-302 - Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi:
Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers. 303-304 - Hyunseok Hwang, Hyeyeon Lee, Youngcheol Chae:
A 6.9mW 120fps 28×50 capacitive touch sensor for 1mm-φ stylus using current-driven ΔΣ ADCs. 305-306 - Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi:
A switched-loop-filter PLL with fast phase-error correction technique. 307-308 - Youngwoo Ji, Cheonhoo Jeon, Hyunwoo Son, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 9.3 nW all-in-one bandgap voltage and current reference circuit using leakage-based PTAT generation and DIBL characteristic. 309-310 - Ji-Hoon Lee, Kwangmin Kim, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
A 16.6-pJ/b 150-Mb/s body-channel communication transceiver with decision feedback equalization improving >200x area efficiency. 311-312 - Dong-Soo Lee, Sung-Jin Kim, SeongJin Oh, Gyusub Won, Thi Kim Nga Truong, Imran Ali, Hamed Abbasizadeh, Behnam Samadpoor Rikan, Kang-Yoon Lee:
Low power FSK transceiver using ADPLL with direct modulation and integrated SPDT for BLE application. 313-314 - Injun Choi, Ji-Hoon Kim:
A 2.22 Gbps high-throughput NB-LDPC decoder in 65nm CMOS with aggressive overlap scheduling. 315-316 - Motomi Ishizuka, Kohei Yamada, Hiroki Ishikuro:
Design of resource sharing reconfigurable ΔΣ SAR-ADC. 317-318 - Oh-Yong Jung, Hyun-Gi Seok, Anjana Dissanayake, Sang-Gug Lee:
A 2.4GHz, -102dBm-sensitivity, 25kb/s, 0.466mW interference resistant BFSK multi-channel sliding-IF ULP receiver. 319-320 - Kyeong-min Park, Joohyeb Song, Franklin Bien:
Highly sensitive fingerprint readout IC for glass-covered mutual capacitive fingerprint sensor. 321-322 - Huimin Liu, Xiongfei Qu, Lingling Cao, Ruifeng Liu, Yuanzhi Zhang, Meijuan Zhang, Xiaoqiang Li, Wenshen Wang, Chao Lu:
A 5.8 GHz DSRC digitally controlled CMOS RF-SoC transceiver for China ETC. 323-324 - Hyunwoo Son, Hwasuk Cho, Jahyun Koo, Youngwoo Ji, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A low-power wide dynamic-range current readout circuit for biosensors. 325-326 - Hong-Thu Nguyen, Xuan-Thuan Nguyen, Cong-Kha Pham:
An efficient fixed-point arithmetic processor using a hybrid CORDIC algorithm. 327-328 - Jaehwan Jung, In-Cheol Park, Youngjoo Lee:
A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems. 329-330 - Boyu Zhang, Azadeh Davoodi, Yu Hen Hu:
Exploring energy and accuracy tradeoff in structure simplification of trained deep neural networks. 331-336 - Zhiheng Wang, Soheil Mohajer, Kia Bazargan:
Low latency parallel implementation of traditionally-called stochastic circuits using deterministic shuffling networks. 337-342 - Jung-Woo Chang, Suk-Ju Kang:
Optimizing FPGA-based convolutional neural networks accelerator for image super-resolution. 343-348 - Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li:
XORiM: A case of in-memory bit-comparator implementation and its performance implications. 349-354 - Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan:
Logic synthesis for energy-efficient photonic integrated circuits. 355-360 - Farhana Parveen, Zhezhi He, Shaahin Angizi, Deliang Fan:
HielM: Highly flexible in-memory computing using STT MRAM. 361-366 - Hongbin Zhang, Chao Zhang, Qingda Hu, Chengmo Yang, Jiwu Shu:
Performance analysis on structure of racetrack memory. 367-374 - Enes Eken, Ismail Bayram, Hai Helen Li, Yiran Chen:
Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization. 375-380 - Daijoon Hyun, Youngsoo Shin:
Automatic insertion of airgap with design rule constraints. 381-386 - Daifeng Guo, Hongbo Zhang, Martin D. F. Wong:
On coloring rectangular and diagonal grid graphs for multiple patterning lithography. 387-392 - Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar:
Lifetime-aware design methodology for dynamic partially reconfigurable systems. 393-398 - Han Zhou, Yijing Sun, Zeyu Sun, Hengyang Zhao, Sheldon X.-D. Tan:
Electromigration-lifetime constrained power grid optimization considering multi-segment interconnect wires. 399-404 - Andrew B. Kahng:
New directions for learning-based IC design tools and methodologies. 405-410 - Manish Pandey:
Machine learning and systems for building the next generation of EDA tools. 411-415 - Norman Chang, Ajay Baranwal, Hao Zhuang, Ming-Chih Shih, Rahul Rajan, Yaowei Jia, Hui-Lun Liao, Ying-Shiun Li, Ting Ku, Rex Lin:
Machine learning based generic violation waiver system with application on electromigration sign-off. 416-421 - Jeff Dyck:
Machine learning for engineering. 422-427 - Siyu Liao, Liutong Zhou, Xuan Di, Bo Yuan, Jinjun Xiong:
Large-scale short-term urban taxi demand forecasting using deep learning. 428-433 - Kai Neubauer, Christian Haubelt, Philipp Wanko, Torsten Schaub:
Utilizing quad-trees for efficient design space exploration with partial assignment evaluation. 434-439 - Bin Lin, Fei Xie:
SCBench: A benchmark design suite for SystemC verification and validation. 440-445 - Qi Nie, Sharad Malik:
MemFlow: Memory-driven data scheduling with datapath co-design in accelerators for large-scale inference applications. 446-451 - Omayma Matoussi, Frédéric Pétrot:
A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimation. 452-457 - Byung-Su Kim, Joon-Sung Yang:
System level performance analysis and optimization for the adaptive clocking based multi-core processor. 458-463 - Dustin Peterson, Yannick Boekle, Oliver Bringmann:
Detecting non-functional circuit activity in SoC designs. 464-469 - Eric Schneider, Michael A. Kochte, Hans-Joachim Wunderlich:
Multi-level timing simulation on GPUs. 470-475 - Sunmean Kim, Taeho Lim, Seokhyeong Kang:
An optimal gate design for the synthesis of ternary logic circuits. 476-481 - Hao-Yu Chi, Hwa-Yi Tseng, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Performance-preserved analog routing methodology via wire load reduction. 482-487 - David M. Moore, Jeffrey A. Fredenburgh, Muhammad Faisal, David D. Wentzloff:
Static timing analysis for ring oscillators. 488-493 - Necati Uysal, Rickard Ewetz:
OCV guided clock tree topology reconstruction. 494-499 - Kyeongrok Jo, Seyong Ahn, Taewhan Kim, Kyu-Myung Choi:
Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion. 500-506 - Chuan Yean Tan, Rickard Ewetz, Cheng-Kok Koh:
Clustering of flip-flops for useful-skew clock tree synthesis. 507-512 - Sergii Osmolovskyi, Johann Knechtel, Igor L. Markov, Jens Lienig:
Optimal die placement for interposer-based 3D ICs. 513-520 - Tao-Chun Yu, Shao-Yun Fang:
Flip-chip routing with IO planning considering practical pad assignment constraints. 521-526 - Minsoo Rhu:
Accelerator-centric deep learning systems for enhanced scalability, energy-efficiency, and programmability. 527-533 - Bing Li, Wei Wen, Jiachen Mao, Sicheng Li, Yiran Chen, Hai Helen Li:
Running sparse and low-precision neural network: When algorithm meets hardware. 534-539 - Barend Harris, Mansureh S. Moghaddam, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min, Hansu Cho, Sukjin Kim, Bernhard Egger, Soonhoi Ha, Kiyoung Choi:
Architectures and algorithms for user customization of CNNs. 540-547 - Chieh-Fu Chang, Che-Wei Chang, Yuan-Hao Chang, Ming-Chang Yang:
Rethinking self-balancing binary search tree over phase change memory with write asymmetry. 548-553 - Huizhang Luo, Liang Shi, Qiao Li, Chun Jason Xue, Edwin Hsing-Mean Sha:
Energy, latency, and lifetime improvements in MLC NVM with enhanced WOM code. 554-559 - Matthias Becker, Saad Mubeen, Dakshina Dasari, Moris Behnam, Thomas Nolte:
Scheduling multi-rate real-time applications on clustered many-core architectures with memory constraints. 560-567 - Tao Liu, Lei Jiang, Yier Jin, Gang Quan, Wujie Wen:
PT-spike: A precise-time-dependent single spike neuromorphic architecture with efficient supervised learning. 568-573 - Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu:
Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neurons. 574-579 - Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Helen Li, Weisheng Zhao:
Spintronics based stochastic computing for efficient Bayesian inference system. 580-585 - Bruno de O. Schmitt, Alan Mishchenko, Robert K. Brayton:
SAT-based area recovery in structural technology mapping. 586-591 - Chak-Wa Pui, Peishan Tu, Haocheng Li, Gengjie Chen, Evangeline F. Y. Young:
A two-step search engine for large scale boolean matching under NP3 equivalence. 592-598 - Keith A. Campbell, Chen-Hsuan Lin, Deming Chen:
Low-cost hardware architectures for mersenne modulo functional units. 599-604 - Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
A low-power high-speed accuracy-controllable approximate multiplier design. 605-610 - Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi:
Exploration of approximate multipliers design space using carry propagation free compressors. 611-616 - Min Soo Kim, Alberto A. Del Barrio, Román Hermida, Nader Bagherzadeh:
Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks. 617-622 - Zeyu Sun, Sheriff Sadiqbatcha, Hengyang Zhao, Sheldon X.-D. Tan:
Accelerating electromigration aging for fast failure detection for nanometer ICs. 623-630 - Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation. 631-636 - Mohammad Saber Golanbari, Anteneh Gebregiorgis, Elyas Moradi, Saman Kiamehr, Mehdi Baradaran Tahoori:
Balancing resiliency and energy efficiency of functional units in ultra-low power systems. 637-644 - Wenyu Sun, Yuxuan Huang, Qinghang Zhao, Fei Qiao, Tsung-Yi Ho, Xiaojun Guo, Huazhong Yang, Yongpan Liu:
Mechanical strain and temperature aware design methodology for thin-film transistor based pseudo-CMOS logic array. 645-650 - Leilai Shao, Tsung-Ching Huang, Ting Lei, Zhenan Bao, Raymond G. Beausoleil, Kwang-Ting Cheng:
Process design kit for flexible hybrid electronics. 651-657 - Gabriel Cadilha Marques, Farhan Rasheed, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori:
From silicon to printed electronics: A coherent modeling and design flow approach based on printed electrolyte gated FETs. 658-663 - Giulia Meuli, Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli:
A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis. 664-669 - Alwin Zulehner, Robert Wille:
Exploiting coding techniques for logic synthesis of reversible circuits. 670-675 - Zhufei Chu, Mathias Soeken, Yinshui Xia, Giovanni De Micheli:
Functional decomposition using majority. 676-681 - Mohsen Imani, Max Masich, Daniel Peroni, Pushen Wang, Tajana Rosing:
CANNA: Neural network acceleration using configurable approximation on GPGPU. 682-689 - Behnam Khodabandeloo, Ahmad Khonsari, Alireza Majidi, Mohammad Hassan Hajiesmaili:
Task assignment and scheduling in MPSoC under process variation: A stochastic approach. 690-695 - Christian Pilato, Luca P. Carloni:
DarkMem: Fine-grained power management of local memories for accelerators in embedded systems. 696-701 - Florencia Irena, Daniel Murphy, Sri Parameswaran:
CryptoBlaze: A partially homomorphic processor with multiple instructions and non-deterministic encryption support. 702-708 - Md. Nazmul Islam, Sandip Kundu:
PMU-Trojan: On exploiting power management side channel for information leakage. 709-714 - Wenxuan Wang, Aijiao Cui, Gang Qu, Huawei Li:
A low-overhead PUF based on parallel scan design. 715-720 - Qi Liu, Tao Liu, Zihao Liu, Yanzhi Wang, Yier Jin, Wujie Wen:
Security analysis and enhancement of model compressed deep learning systems under adversarial attacks. 721-726 - Chenguang Wang, Yici Cai, Qiang Zhou:
HLIFT: A high-level information flow tracking method for detecting hardware Trojans. 727-732 - Atul Prasad Deb Nath, Sandip Ray, Abhishek Basak, Swarup Bhunia:
System-on-chip security architecture and CAD framework for hardware patch. 733-738
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-29 20:20 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
