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2020 – today
- 2024
[j6]Vasilii Kulagin
, Sergio Vinagrero Gutierrez, Tobias Kilian, Daniel Tille, Ulf Schlichtmann, Giorgio Di Natale, Elena-Ioana Vatajelu:
On the Relation Between Reliability and Entropy in Physical Unclonable Functions. IEEE Des. Test 41(6): 46-53 (2024)- 2023
- [j5]Tobias Kilian, Daniel Tille, Martin Huch, Markus Hanel, Ulf Schlichtmann:
Performance Screening Using Functional Path Ring Oscillators. IEEE Trans. Very Large Scale Integr. Syst. 31(6): 711-724 (2023) - [c19]Tobias Kilian, Abhishek Sengupta, Daniel Tille, Martin Huch, Ulf Schlichtmann:
An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators. DFT 2023: 1-6 - [c18]Daniel Tille, Leon Klimasch, Sebastian Huhn:
A Novel LBIST Signature Computation Method for Automotive Microcontrollers using a Digital Twin. VTS 2023: 1-6 - 2022
- [c17]Tobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann:
Reducing Routing Overhead by Self-Enabling Functional Path Ring Oscillators. ETS 2022: 1-6 - [c16]Tobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann:
A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data. ITC 2022: 258-267 - 2021
- [j4]Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Time and Area Optimized Testing of Automotive ICs. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 76-88 (2021) - [c15]Tobias Kilian, Heiko Ahrens, Daniel Tille, Martin Huch, Ulf Schlichtmann:
A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators. ITC 2021: 299-303
2010 – 2019
- 2019
- [c14]Sebastian Huhn, Daniel Tille, Rolf Drechsler:
Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns. ETS 2019: 1-2 - [c13]Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki:
Test Time and Area Optimized BrST Scheme for Automotive ICs. ITC 2019: 1-10 - [c12]Sebastian Huhn, Daniel Tille, Rolf Drechsler:
A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems. ITC-Asia 2019: 115-120 - 2018
- [c11]Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen, Helmut Graeb, Ulf Schlichtmann:
On enabling diagnosis for 1-Pin Test fails in an industrial flow. ASP-DAC 2018: 233-238 - 2017
- [c10]Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen:
A lightweight X-masking scheme for IoT designs. ITC-Asia 2017: 77-82 - 2016
- [c9]Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen:
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test. ATS 2016: 173-178 - 2014
- [c8]Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß:
Automated formal verification of X propagation with respect to testability issues. IDT 2014: 106-111 - 2010
- [j3]Daniel Tille, Stephan Eggersglüß, Rolf Drechsler:
Incremental Solving Techniques for SAT-based ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1125-1130 (2010) - [c7]Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler:
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. ETS 2010: 176-181 - [c6]Stephan Eggersglüß, Daniel Tille, Rolf Drechsler:
Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation. ISCAS 2010: 649-652
2000 – 2009
- 2009
- [b1]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille:
Test Pattern Generation using Boolean Proof Engines. Springer 2009, ISBN 978-90-481-2359-9, pp. I-XII, 1-192 - [j2]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille:
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it Inf. Technol. 51(2): 102-111 (2009) - [c5]Stephan Eggersglüß, Daniel Tille, Rolf Drechsler:
Speeding up SAT-Based ATPG Using Dynamic Clause Activation. Asian Test Symposium 2009: 177-182 - [c4]Daniel Tille, Rolf Drechsler:
A fast untestability proof for SAT-based ATPG. DDECS 2009: 38-43 - 2008
- [j1]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille:
On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1329-1333 (2008) - [c3]Daniel Tille, Rolf Drechsler:
Incremental SAT Instance Generation for SAT-based ATPG. DDECS 2008: 68-73 - [i1]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille:
SAT-based Automatic Test Pattern Generation. Evolutionary Test Generation 2008 - 2007
- [c2]Daniel Tille, Görschwin Fey, Rolf Drechsler:
Instance Generation for SAT-based ATPG. DDECS 2007: 153-156 - [c1]Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6
Coauthor Index
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last updated on 2024-12-02 22:32 CET by the dblp team
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