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ORCIDITC 2022: Anaheim, CA, USA
- IEEE International Test Conference, ITC 2022, Anaheim, CA, USA, September 23-30, 2022. IEEE 2022, ISBN 978-1-6654-6270-9
- Hongfei Wang, Wei Liu, Hai Jin, Yu Chen, Wenjie Cai:
Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs. 1-10 - Yiwen Liao, Raphaël Latty, Paul R. Genssler, Hussam Amrouch, Bin Yang:
Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel Information. 1-9 - Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak:
DIST: Deterministic In-System Test with X-masking. 20-27 - Franco Stellari, Peilin Song:
Reliability Study of 14 nm Scan Chains and Its Application to Hardware Security. 28-35 - Junhua Huang, Hui-Ling Zhen, Naixing Wang, Hui Mao, Mingxuan Yuan, Yu Huang:
Neural Fault Analysis for SAT-based ATPG. 36-45 - Muhtadi Choudhury, Minyan Gao, Shahin Tajik, Domenic Forte
:
TAMED: Transitional Approaches for LFI Resilient State Machine Encoding. 46-55 - Wei Zou, Benoit Nadeau-Dostie:
Configurable BISR Chain For Fast Repair Data Loading. 56-62 - Kazuya Loki, Yasuyuki Kai, Kohei Miyase, Seiji Kajihara:
A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications. 63-72 - Dun-An Yang, Jing-Jia Liou, Harry H. Chen:
Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging. 73-81 - Yan-Fu Chen, Duo-Yao Kang, Kuen-Jong Lee:
Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks. 82-91 - Kuan-Wei Hou, Hsueh-Hung Cheng, Chi Tung, Cheng-Wen Wu, Juin-Ming Lu:
Fault Modeling and Testing of Memristor-Based Spiking Neural Networks. 92-99 - Xiaopeng Zhang, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Evangeline F. Y. Young, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao:
RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement. 100-107 - Xing Wang, Zezhong Wang, Naixing Wang, Weiwei Zhang, Yu Huang:
Compression-Aware ATPG. 108-117 - Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty:
Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration. 118-127 - Sam M.-H. Hsiao, Lowry P.-T. Wang, Aaron C.-W. Liang, Charles H.-P. Wen:
Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies. 128-136 - Chen-Lin Tsai, Shi-Yu Huang:
Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning. 137-144 - Jonti Talukdar, Arjun Chaudhuri, Mayukh Bhattacharya, Krishnendu Chakrabarty:
Automatic Structural Test Generation for Analog Circuits using Neural Twins. 145-154 - Upoma Das, Md Rafid Muttaki, Mark M. Tehranipoor, Farimah Farahmandi:
ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features. 155-164 - Rasheed Kibria, M. Sazadur Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications. 165-174 - Cheng-Sian Kuo, Bing-Han Hsieh, James Chien-Mo Li, Chris Nigh, Gaurav Bhargava, Mason Chern:
Diagnosing Double Faulty Chains through Failing Bit Separation. 175-184 - Yiwen Liao, Zahra Paria Najafi-Haghi, Hans-Joachim Wunderlich, Bin Yang:
Efficient and Robust Resistive Open Defect Detection Based on Unsupervised Deep Learning. 185-193 - Zhengyuan Shi, Min Li, Sadaf Khan, Liuzheng Wang, Naixing Wang, Yu Huang, Qiang Xu:
DeepTPI: Test Point Insertion with Deep Reinforcement Learning. 194-203 - Brian Foutz, Sarthak Singhal, Prateek Kumar Rai, Krishna Chakravadhanula, Vivek Chickermane, Bharath Nandakumar, Sameer Chillarige, Christos Papameletis, Satish Ravichandran:
PPA Optimization of Test Points in Automotive Designs. 204-212 - Wei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh:
ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption. 213-218 - Farrokh Ghani Zadegan, Zilin Zhang, Kim Petersén, Erik Larsson:
Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus. 219-228 - Ayush Arunachalam, Athulya Kizhakkayil, Shamik Kundu, Arnab Raha, Suvadeep Banerjee, Robert Jin, Fei Su, Kanad Basu:
Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs. 229-238 - Soyed Tuhin Ahmed, Mehdi B. Tahoori:
Compact Functional Test Generation for Memristive Deep Learning Implementations using Approximate Gradient Ranking. 239-248 - Arani Sinha, Yonsang Cho, Jon Easter, Meizel V. Leiva Rojas:
Multi-die Parallel Test Fabric for Scalability and Pattern Reusability. 249-257 - Tobias Kilian, Markus Hanel, Daniel Tille, Martin Huch, Ulf Schlichtmann:
A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data. 258-267 - Jun-Yang Lei, Abhijit Chatterjee:
ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits. 268-277 - Josie E. Rodriguez Condia, Juan-David Guerrero-Balaguera, Fernando Fernandes dos Santos, Matteo Sonza Reorda, Paolo Rech:
A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability. 278-287 - Min Jian Yang, Yueling Zeng, Li-C. Wang:
Language Driven Analytics for Failure Pattern Feedforward and Feedback. 288-297 - Suriyaprakash Natarajan, Abhijit Sathaye, Chaitali Oak, Nipun Chaplot, Suvadeep Banerjee:
DEFCON: Defect Acceleration through Content Optimization. 298-304 - Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski:
Test Generation for an Iterative Design Flow with RTL Changes. 305-313 - Wei Li, Chris Nigh, Danielle Duvalsaint, Subhasish Mitra, Ronald D. Blanton:
PEPR: Pseudo-Exhaustive Physically-Aware Region Testing. 314-323 - Nirmal R. Saxena, Atieh Lotfi:
Error Model (EM) - A New Way of Doing Fault Simulation. 324-333 - Khader S. Abdel-Hafez, Michael Dsouza, Likith Kumar Manchukonda, Elddie Tsai, Karthikeyan Natarajan, Ting-Pu Tai, Wenhao Hsueh, Smith Lai:
Comprehensive Power-Aware ATPG Methodology for Complex Low-Power Designs. 334-339 - Bharath Nandakumar, Madhur Maheshwari, Sameer Chillarige, Robert Redburn, Jeff Zimmerman, Nicholai L'Esperance, Edward Dziarcak:
Scaling physically aware logic diagnosis to complex high volume 7nm server processors. 340-347 - Subhadip Kundu, Gaurav Bhargava, Lesly Endrinal, Lavakumar Ranganathan:
Using Custom Fault Models to Improve Understanding of Silicon Failures. 348-354 - Francesco Angione, Paolo Bernardi, Andrea Calabrese, Lorenzo Cardone, A. Niccoletti, Davide Piumatti, Stefano Quer, Davide Appello, Vincenzo Tancorre, Roberto Ugioli:
An innovative Strategy to Quickly Grade Functional Test Programs. 355-364 - Hans Martin von Staudt, Luai Tarek Elnawawy, Sarah Wang, Larry Ping, Jung Woo Choi:
Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC. 365-371 - Adit D. Singh:
Understanding Vmin Failures for Improved Testing of Timing Marginalities. 372-381 - Michael Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Songlin Zuo:
IEEE P1687.1: Extending the Network Boundaries for Test. 382-390 - Shyue-Kung Lu, Shi-Chun Tseng, Kohei Miyase:
Fine-Grained Built-In Self-Repair Techniques for NAND Flash Memories. 391-399 - Abhairaj Singh, Moritz Fieback, Rajendra Bishnoi, Filip Bradaric, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui:
Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT. 400-409 - Lorella Bordogna, Fabio Brembilla, Alberto Pagani, Marco Spinetta:
New R&R Methodology in Semiconductor Manufacturing Electrical Testing. 410-419 - Soumya Mittal, Szczepan Urban, Kun Young Chung, Jakub Janicki, Wu-Tung Cheng, Martin Parley, Manish Sharma, Shaun Nicholson:
Industry Evaluation of Reversible Scan Chain Diagnosis. 420-426 - Chen He, Paul Grosch, Onder Anilturk, Joyce Witowski, Carl Ford, Rahul Kalyan, John C. Robinson, David W. Price, Jay Rathert, Barry Saville, Dave Lee:
Defect-Directed Stress Testing Based on Inline Inspection Results. 427-435 - Mayukh Bhattacharya, Beatrice Solignac, Michael Dürr:
Application of Sampling in Industrial Analog Defect Simulation. 436-445 - Ankush Srivastava, Jais Abraham:
Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test. 446-455 - Esteban Garita-Rodríguez, Renato Rimolo-Donadio, Rafael Zamora-Salazar:
Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products. 456-464 - Takumi Uezono, Yi He, Yanjing Li:
Achieving Automotive Safety Requirements through Functional In-Field Self-Test for Deep Learning Accelerators. 465-473 - Irith Pomeranz:
Transforming an $n$-Detection Test Set into a Test Set for a Variety of Fault Models. 474-478 - Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak:
Hardware Root of Trust for SSN-basedDFT Ecosystems. 479-483 - P. D'Hondt, Aymen Ladhar, Patrick Girard, Arnaud Virazel:
A Comprehensive Learning-Based Flow for Cell-Aware Model Generation. 484-488 - Ze-Wei Pan, Jin-Fu Li:
DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs. 489-493 - Mukta Debnath, Animesh Basak Chowdhury, Debasri Saha, Susmita Sur-Kolay:
GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs. 494-498 - Kwondo Ma, Anurup Saha, Chandramouli N. Amarnath, Abhijit Chatterjee:
Efficient Low Cost Alternative Testing of Analog Crossbar Arrays for Deep Neural Networks. 499-503 - Shamik Kundu, Akul Malhotra, Arnab Raha, Sumeet Kumar Gupta, Kanad Basu:
RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators. 504-508 - Praise O. Farayola, Isaac Bruce, Shravan K. Chaganti, Abalhassan Sheikh, Srivaths Ravi, Degang Chen:
Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing. 509-513 - Kushagra Bhatheja, Shravan K. Chaganti, Degang Chen, Xiankun Robert Jin, Chris C. Dao, Juxiang Ren, Abhishek Kumar, Daniel Correa, Mark Lehmann, Thomas Rodriguez, Eric Kingham, Joel R. Knight, Allan Dobbin, Scott W. Herrin, Doug Garrity:
Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing. 514-518 - Bijay Raj Paudel, Spyros Tragoudas:
The Impact of On-chip Training to Adversarial Attacks in Memristive Crossbar Arrays. 519-523 - Saurabh Hukerikar, Nirmal R. Saxena:
Runtime Fault Diagnostics for GPU Tensor Cores. 524-528 - Feng Yun, Yunkun Lin, Lou Yunfei, Lei Gao, Vaibhav Gera, Boxuan Li, Vennela Chowdary Nekkanti, Aditya Rajendra Pharande, Kunal Sheth, Meghana Thommondru, Guizhong Ye, Sandeep Gupta:
Fault-coverage Maximizing March Tests for Memory Testing. 529-533 - Mahta Mayahinia, Mehdi B. Tahoori, Manu Perumkunnil, Kristof Croes, Francky Catthoor:
Analyzing the Electromigration Challenges of Computation in Resistive Memories. 534-538 - Michele Portolan, Antonios Pavlidis, Giorgio Di Natale, Eric Faehn, Haralampos-G. Stratigopoulos:
Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure. 539-543 - Weng Joe Soh, Chen He:
Enhanced Data Pattern to Detect Defects in Flash Memory Address Decoder. 544-548 - Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Andrew Yi-Ann Huang, Chen-Shiun Lee, Leon Li-Yang Chen, Peter Yi-Yu Liao, Nova Cheng-Yen Tsai:
Wafer Defect Pattern Classification with Explainable-Decision Tree Technique. 549-553 - Nadun Sinhabahu, Katherine Shu-Min Li, Jian-De Li, J. R. Wang, Sying-Jyan Wang:
Yield-Enhanced Probe Head Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test. 554-558 - Thomas Nirmaier, Manuel Harrant, Marc Huppmann, Wendy You, Georg Pelz:
Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification. 559-562 - Seongkwan Lee, Cheolmin Park, Minho Kang, Jun Yeon Won, HyungSun Ryu, Jaemoo Choi, Byunghyun Yim:
4.5 Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment. 563-567 - Vijayakumar Thangamariappan, Nidhi Agrawal, Jason Kim, Constantinos Xanthopoulos, Ken Butler, Ira Leventhal, Joe Xiao:
Improvements in Automated IC Socket Pin Defect Detection. 568-572 - Makoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Michihiro Shintani:
Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data. 573-577 - David P. Lerner, Benson Inkley, Shubhada H. Sahasrabudhe, Ethan Hansen, Luis D. Rojas Munoz, Arjan van de Ven:
Optimization of Tests for Managing Silicon Defects in Data Centers. 578-582 - Brian Buras, Constantinos Xanthopoulos, Ken Butler, Jason Kim:
Zero Trust Approach to IC Manufacturing and Testing. 583-586 - Benjamin Niewenhuis, Devanathan Varadarajan:
Improving structural coverage of functional tests with checkpoint signature computation. 587-590 - Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase:
Fault Resilience Techniques for Flash Memory of DNN Accelerators. 591-600 - Ya-Chi Cheng, Pai-Yu Tan, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang, Gordon Liao:
Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method. 601-608 - Sebastian Huhn, Rolf Drechsler:
Next Generation Design For Testability, Debug and Reliability Using Formal Techniques. 609-618 - Supriyo Srimani, Hafizur Rahaman:
Testing of Analog Circuits using Statistical and Machine Learning Techniques. 619-626 - Prabuddha Chakraborty, Swarup Bhunia:
AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks. 627-636 - Hans Martin von Staudt, Franz Schuler, Rohitaswa Bhattacharya, Justin Wei-Lin Cheng, Cheng-Da Huang, Parker Chih-Chun Chen:
High-Coverage DfT and Reliability Enhancements for Automotive Floating Gate OTP Beyond AEC-Q100. 637-641 - Costas Argyrides, Vilas Sridharan, Hayk Danoyan, Gurgen Harutyunyan, Yervant Zorian:
A Novel Protection Technique for Embedded Memories with Optimized PPA. 642-645 - Gabriele Filipponi, Giusy Iaria, Matteo Sonza Reorda, Davide Appello, Giuseppe Garozzo, Vincenzo Tancorre:
In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip. 646-649 - Mahta Mayahinia, Mehdi B. Tahoori, Gurgen Harutyunyan, Grigor Tshagharyan, Karen Amirkhanyan:
An Efficient Test Strategy for Detection of Electromigration Impact in Advanced FinFET Memories. 650-655 - Amit Pandey, Brendan Tully, Karthikeyan Natarajan:
High Speed IO Access for Test forms the foundation for Silicon Lifecycle Management. 656-660 - Firooz Massoudi:
In search of Vmin for dynamic power managmenet and reliable operation in mission mode. 661-664
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last updated on 2025-02-20 19:49 CET by the dblp team
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