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2020 – today
- 2024
[j41]Sumit Diware
, Koteswararao Chilakala, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi:
Reliable and Energy-Efficient Diabetic Retinopathy Screening Using Memristor-Based Neural Networks. IEEE Access 12: 47469-47482 (2024)- [c100]Sumit Diware, Mohammad Amin Yaldagard, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi:
Dynamic Detection and Mitigation of Read-disturb for Accurate Memristor-based Neural Networks. AICAS 2024: 393-397 - [c99]Dinesh Kushwaha, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin. ISCAS 2024: 1-5 - [c98]Dinesh Kushwaha, Ashish Joshi, Abhishek Goel, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology. ISQED 2024: 1-8 - [c97]Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Jainendra Singh, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture. LASCAS 2024: 1-5 - [c96]Dinesh Kushwaha, Rajiv V. Joshi, Anand Bulusu, Sudeb Dasgupta:
Variation-Aware Design Methodology for SRAM-Based Multi-Bit Analog Compute-in-Memory Architecture. NewCAS 2024: 243-247 - [c95]Asmae El Arrassi, Mohammad Amin Yaldagard, Xingjian Tao, Taha Shahroodi, Fouwad Jamil Mir, Yashvardhan Biyani, Manil Dev Gomony, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui:
AFSRAM-CIM: Adder Free SRAM-Based Digital Computation-in-Memory for BNN. VLSI-SoC 2024: 1-6 - [i3]Zijian Zhao, Sola Woo, Khandker Akif Aabrar, Sharadindu Gopal Kirtania, Zhouhang Jiang, Shan Deng, Yi Xiao, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Steven Soss, Sven Beyer, Rajiv V. Joshi, Scott Meninger, Mohamed Mohamed, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Vijaykrishnan Narayanan, Suman Datta, Shimeng Yu, Kai Ni:
Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate. CoRR abs/2403.04981 (2024) - 2023
- [j40]Sumit Diware, Sudeshna Dash, Anteneh Gebregiorgis, Rajiv V. Joshi, Christos Strydis, Said Hamdioui, Rajendra Bishnoi:
Severity-Based Hierarchical ECG Classification Using Neural Networks. IEEE Trans. Biomed. Circuits Syst. 17(1): 77-91 (2023) - [j39]Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi:
A Best Balance Ratio Ordered Feature Selection Methodology for Robust and Fast Statistical Analysis of Memory Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 1742-1755 (2023) - [j38]Sumit Diware, Abhairaj Singh, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi:
Accurate and Energy-Efficient Bit-Slicing for RRAM-Based Neural Networks. IEEE Trans. Emerg. Top. Comput. Intell. 7(1): 164-177 (2023) - [c94]Sumit Diware, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi:
Mapping-aware Biased Training for Accurate Memristor-based Neural Networks. AICAS 2023: 1-5 - [c93]Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application. AICAS 2023: 1-5 - [c92]Abhairaj Singh, Rajendra Bishnoi, Ali Kaichouhi, Sumit Diware, Rajiv V. Joshi, Said Hamdioui:
A 115.1 TOPS/W, 12.1 TOPS/mm2 Computation-in-Memory using Ring-Oscillator based ADC for Edge AI. AICAS 2023: 1-5 - [c91]Mohammad Amin Yaldagard, Sumit Diware, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi:
Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture. AICAS 2023: 1-5 - [c90]David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Chris Baks, John Timmerwilke, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman:
Low power cryogenic RF ASICs for quantum computing. CICC 2023: 1-8 - [c89]Rajiv V. Joshi, Jean-Olivier Plouchart, George Zettles, Scott Willenborg, Sudipto Chakraborty, Blake R. Johnson, Andrew Wack, Brian Allison, John Timmerwilke, Kevin Tien, Mark Yeck, Dereje Yilma, Alberto Valdes-Garcia, Daniel J. Friedman:
Cryogenic CMOS: design considerations for future quantum computing systems. CICC 2023: 1-8 - [c88]Rajiv V. Joshi, Sudipto Chakraborty:
(Invited) Predictive analytics for cryogenic CMOS in future quantum computing systems. DAC 2023: 1-4 - [c87]Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. VLSID 2023: 359-364 - [i2]Zijian Zhao, Shan Deng, Swetaki Chatterjee, Zhouhang Jiang, Muhammad Shaffatul Islam, Yi Xiao, Yixin Xu, Scott Meninger, Mohamed Mohamed, Rajiv V. Joshi, Yogesh Singh Chauhan, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Sven Beyer, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni:
Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET. CoRR abs/2305.01484 (2023) - 2022
- [j37]Mahta Mayahinia, Abhairaj Singh, Christopher Bengel, Stefan Wiefels, Muath Abu Lebdeh, Stephan Menzel, Dirk J. Wouters, Anteneh Gebregiorgis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui:
A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs. ACM J. Emerg. Technol. Comput. Syst. 18(2): 32:1-32:25 (2022) - [j36]Sudipto Chakraborty, David J. Frank, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Devin Underwood, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Dorothy Wisnieff, Christian W. Baks, Donald S. Bethune, John Timmerwilke, Thomas Fox, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman:
A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology. IEEE J. Solid State Circuits 57(11): 3258-3273 (2022) - [j35]Gokul Krishnan, Li Yang, Jingbo Sun, Jubin Hazra, Xiaocong Du, Maximilian Liehr, Zheng Li, Karsten Beckmann, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Yu Cao:
Exploring Model Stability of Deep Neural Networks for Reliable RRAM-Based In-Memory Acceleration. IEEE Trans. Computers 71(11): 2740-2752 (2022) - [j34]Gokul Krishnan, Zhenyu Wang, Injune Yeo, Li Yang, Jian Meng, Maximilian Liehr, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Jae-Sun Seo, Yu Cao:
Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4241-4252 (2022) - [j33]Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi, Ali Chehab:
Group LARS-Based Iterative Reweighted Least Squares Methodology for Efficient Statistical Modeling of Memory Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5722-5726 (2022) - [j32]Neeraj Mishra, Anchit Proch, Lomash Chandra Acharya, Jeffrey Prinzie, Sudipto Chakraborty, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
Phase Noise Analysis of Separately Driven Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 69(11): 4415-4428 (2022) - [j31]Neeraj Mishra, Lalit Mohan Dani, Sudipto Chakraborty, Rajiv V. Joshi, Anand Bulusu:
Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Using ROs. IEEE Trans. Circuits Syst. II Express Briefs 69(1): 30-34 (2022) - [j30]Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2311-2315 (2022) - [c86]Abhairaj Singh, Mahdi Zahedi, Taha Shahroodi, Mohit Gupta, Anteneh Gebregiorgis, Manu Komalan, Rajiv V. Joshi, Francky Catthoor, Rajendra Bishnoi, Said Hamdioui:
CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out. AICAS 2022: 451-454 - [c85]Kevin Tien, Ken Inoue, Scott Lekuch, David J. Frank, Sudipto Chakraborty, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman:
A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation. DATE 2022: 13-16 - [c84]Abhairaj Singh, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui:
Referencing-in-Array Scheme for RRAM-based CIM Architecture. DATE 2022: 1413-1418 - [c83]Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu:
A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. ISCAS 2022: 1556-1560 - [c82]David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman:
A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology. ISSCC 2022: 360-362 - [c81]Abhairaj Singh, Moritz Fieback, Rajendra Bishnoi, Filip Bradaric, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui:
Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT. ITC 2022: 400-409 - [c80]Rajiv V. Joshi, John Timmerwilke, Kevin Tien, Mark Yeck, Sudipto Chakraborty:
A 0.31V Vmin Cryogenic SRAM in 14 nm FinFET for Quantum Computing. VLSI Technology and Circuits 2022: 232-233 - [c79]Zhouhang Jiang, Yi Xiao, Swetaki Chatterjee, Halid Mulaosmanovic, Stefan Dünkel, Steven Soss, Sven Beyer, Rajiv V. Joshi, Yogesh Singh Chauhan, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni:
Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window. VLSI Technology and Circuits 2022: 395-396 - [i1]Yixin Xu, Zijian Zhao, Yi Xiao, Tongguang Yu, Halid Mulaosmanovic, Dominik Kleimaier, Stefan Dünkel, Sven Beyer, Xiao Gong, Rajiv V. Joshi, X. Sharon Hu, Shixian Wen, Amanda Sofie Rios, Kiran Lekkala, Laurent Itti, Eric Homan, Sumitha George, Vijaykrishnan Narayanan, Kai Ni:
Ferroelectric FET based Context-Switching FPGA Enabling Dynamic Reconfiguration for Adaptive Deep Learning Machines. CoRR abs/2212.00089 (2022) - 2021
- [j29]Abhairaj Singh, Muath Abu Lebdeh, Anteneh Gebregiorgis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui:
SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 1917-1930 (2021) - [c78]Sumit Diware, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi:
Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture. AICAS 2021: 1-4 - [c77]Gokul Krishnan, Jingbo Sun, Jubin Hazra, Xiaocong Du, Maximilian Liehr, Zheng Li, Karsten Beckmann, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao:
Robust RRAM-based In-Memory Computing in Light of Model Stability. IRPS 2021: 1-5 - [c76]Abhairaj Singh, Sumit Diware, Anteneh Gebregiorgis, Rajendra Bishnoi, Francky Catthoor, Rajiv V. Joshi, Said Hamdioui:
Low-Power Memristor-Based Computing for Edge-AI Applications. ISCAS 2021: 1-5 - [c75]Alexander Fritsch, Rajiv V. Joshi, Sudipto Chakraborty, Holger Wetter, Uma Srinivasan, Matthew Hyde, Otto A. Torreiter, Michael Kugel, Dan Radko, Hyong Kim, Daniel J. Friedman:
24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology. ISSCC 2021: 334-336 - 2020
- [c74]Gouranga Charan, Jubin Hazra, Karsten Beckmann, Xiaocong Du, Gokul Krishnan, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao:
Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation. DAC 2020: 1-6
2010 – 2019
- 2019
- [j28]Matthew M. Ziegler, Krishnan Kailas, Xin Zhang, Rajiv V. Joshi:
Research From the IEEE IBM AI Compute and Emerging Technology Symposia. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(3): 435-438 (2019) - [j27]Insik Yoon, Malik Aqeel Anwar, Rajiv V. Joshi, Titash Rakshit, Arijit Raychowdhury:
Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones. IEEE J. Emerg. Sel. Topics Circuits Syst. 9(3): 485-497 (2019) - [j26]Maria Malik, Katayoun Neshatpour, Setareh Rafatirad, Rajiv V. Joshi, Tinoosh Mohsenin, Hassan Ghasemzadeh, Houman Homayoun:
Big vs little core for energy-efficient Hadoop computing. J. Parallel Distributed Comput. 129: 110-124 (2019) - [j25]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c73]Nandhini Chandramoorthy, Karthik Swaminathan, Martin Cochet, Arun Paidimarri, Schuyler Eldridge, Rajiv V. Joshi, Matthew M. Ziegler, Alper Buyuktosunoglu, Pradip Bose:
Resilient Low Voltage Accelerators for High Energy Efficiency. HPCA 2019: 147-158 - [c72]Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi:
Data Imbalance Handling Approaches for Accurate Statistical Modeling and Yield Analysis of Memory Designs. ISCAS 2019: 1-5 - [c71]Rajiv V. Joshi, Matthew M. Ziegler:
Low Power Design From Moore to AI for nm Era : Invited Paper. MIXDES 2019: 59-64 - 2018
- [j24]Maria Malik, Rajiv V. Joshi, Rouwaida Kanj, Shupeng Sun, Houman Homayoun, Tong Li:
Sparse Regression Driven Mixture Importance Sampling for Memory Design. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 63-72 (2018) - [c70]Rajiv V. Joshi, Matthew M. Ziegler, Karthik Swaminathan, Nandhini Chandramoorthy:
Cascaded and resonant SRAM supply boosting for ultra-low voltage cognitive IoT applications. CICC 2018: 1-4 - 2017
- [j23]Leibin Ni, Hantao Huang, Zichuan Liu, Rajiv V. Joshi, Hao Yu:
Distributed In-Memory Computing on Binary RRAM Crossbar. ACM J. Emerg. Technol. Comput. Syst. 13(3): 36:1-36:18 (2017) - [j22]Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter:
A Low Voltage SRAM Using Resonant Supply Boosting. IEEE J. Solid State Circuits 52(3): 634-644 (2017) - [j21]Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [j20]Krishnendu Chakrabarty, Massimo Alioto, Rajiv V. Joshi:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2393 (2017) - [c69]Rajiv V. Joshi, Matthew M. Ziegler:
Programmable supply boosting techniques for near threshold and wide operating voltage SRAM. CICC 2017: 1-4 - [c68]Muhammad M. Khellah, Rajiv V. Joshi:
Session 5 - Memory for emerging applications. CICC 2017: 1 - [c67]Ramon Bertran, Pradip Bose, David M. Brooks, Jeff Burns, Alper Buyuktosunoglu, Nandhini Chandramoorthy, Eric Cheng, Martin Cochet, Schuyler Eldridge, Daniel Friedman, Hans M. Jacobson, Rajiv V. Joshi, Subhasish Mitra, Robert K. Montoye, Arun Paidimarri, Pritish Parida, Kevin Skadron, Mircea Stan, Karthik Swaminathan, Augusto Vega, Swagath Venkataramani, Christos Vezyrtzis, Gu-Yeon Wei, John-David Wellman, Matthew M. Ziegler:
Very Low Voltage (VLV) Design. ICCD 2017: 601-604 - [c66]Adam Issa, Rouwaida Kanj, Ali Chehab, Rajiv V. Joshi:
Yield and energy tradeoffs of an NVLatch design using radial sampling. ICICDT 2017: 1-4 - [c65]Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi, Maria Malik, Ali Chehab:
Regularized logistic regression for fast importance sampling based SRAM yield analysis. ISQED 2017: 119-124 - 2016
- [j19]Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li:
Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 105-108 (2016) - [j18]Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li:
Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 261-264 (2016) - [j17]Swaroop Ghosh, Anirudh Iyengar, Seyedhamidreza Motaman, Rekha Govindaraj, Jae-Won Jang, Jinil Chung, Jongsun Park, Xin Li, Rajiv V. Joshi, Dinesh Somasekhar:
Overview of Circuits, Systems, and Applications of Spintronics. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 265-278 (2016) - [j16]Rajiv V. Joshi, Sudesh Saroop, Rouwaida Kanj, Yang Liu, Weike Wang, Carl Radens, Yue Tan, Karthik Yogendra:
A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 968-978 (2016) - [c64]Katayoun Neshatpour, Arezou Koohi, Farnoud Farahmand, Rajiv V. Joshi, Setareh Rafatirad, Avesta Sasan, Houman Homayoun:
Big biomedical image processing hardware acceleration: A case study for K-means and image filtering. ISCAS 2016: 1134-1137 - [c63]Maria Malik, Avesta Sasan, Rajiv V. Joshi, Setareh Rafatirah, Houman Homayoun:
Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations. ISPASS 2016: 153-154 - [c62]Mohamed Baker Alawieh, Fa Wang, Rouwaida Kanj, Xin Li, Rajiv V. Joshi:
Efficient analog circuit optimization using sparse regression and error margining. ISQED 2016: 410-415 - 2015
- [j15]Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh:
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 534-543 (2015) - [j14]Rajiv V. Joshi, Rouwaida Kanj:
Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction". IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1380 (2015) - [c61]Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter, C. Wandel, Herschel A. Ainspan:
14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation. VLSIC 2015: 268- - 2014
- [c60]Debajit Bhattacharya, Rajiv V. Joshi, Herschel A. Ainspan, Ninad D. Sathaye, Mohit Bajaj, Suresh Gundapaneni, Niraj K. Jha:
TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology. CICC 2014: 1-4 - [c59]Takamaro Kikkawa, Rajiv V. Joshi:
Design technology co-optimization for 10 nm and beyond. CICC 2014: 1 - [c58]Enes Eken, Yaojun Zhang, Wujie Wen, Rajiv V. Joshi, Hai Li, Yiran Chen:
A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability. DAC 2014: 63:1-63:6 - [c57]Gerard Touma, Rouwaida Kanj, Rajiv V. Joshi, Ayman I. Kayssi, Ali Chehab:
Robust bias temperature instability refresh design and methodology for memory cell recovery. ICICDT 2014: 1-4 - [c56]Sabine Francis, Rouwaida Kanj, Rajiv V. Joshi, Ayman I. Kayssi, Ali Chehab:
Statistical methodology for modeling non-IID memory fails events. ISQED 2014: 205-211 - [c55]Keunwoo Kim, Rouwaida Kanj, Rajiv V. Joshi:
Impact of FinFET technology for power gating in nano-scale design. ISQED 2014: 543-547 - [c54]Subhasish Mitra, Pradip Bose, Eric Cheng, Chen-Yong Cher, Hyungmin Cho, Rajiv V. Joshi, Young Moon Kim, Charles R. Lefurgy, Yanjing Li, Kenneth P. Rodbell, Kevin Skadron, James H. Stathis, Lukasz G. Szafaryn:
The resilience wall: Cross-layer solution strategies. VLSI-DAT 2014: 1-11 - 2013
- [j13]Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha:
Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 47-58 (2013) - [j12]Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha:
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2094-2105 (2013) - [c53]Mark M. Budnik, Rasit Onur Topaloglu, Pallab Chatterjee, Keith A. Bowman, Kamesh V. Gadepally, Paul Wesling, Syed M. Alam, Rajiv V. Joshi:
Welcome to ISQED 2013. ISQED 2013 - [c52]Rajiv V. Joshi, Rouwaida Kanj, S. Butt, Emrah Acar, Dallas Lea, D. Sciacca:
Hardware-corroborated Variability-Aware SRAM Methodology. VLSI Design 2013: 344-349 - 2012
- [c51]Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jerry Hayes, Sani R. Nassif:
Yield estimation via multi-cones. DAC 2012: 1107-1112 - [c50]Peiyuan Wang, Wei Zhang, Rajiv V. Joshi, Rouwaida Kanj, Yiran Chen:
A thermal and process variation aware MTJ switching model and its applications in soft error analysis. ICCAD 2012: 720-727 - [c49]Rouwaida Kanj, Rajiv V. Joshi:
A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability. ISQED 2012: 672-678 - [c48]John Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver:
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro. VLSIC 2012: 110-111 - 2011
- [j11]Rajiv V. Joshi, Rouwaida Kanj, Vinod Ramadurai:
A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 869-882 (2011) - [j10]Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif:
The Impact of Statistical Leakage Models on Design Yield Estimation. VLSI Design 2011: 471903:1-471903:12 (2011) - [c47]Rajiv V. Joshi, Rouwaida Kanj, Peiyuan Wang, Hai Li:
Universal statistical cure for predicting memory loss. ICCAD 2011: 236-239 - [c46]Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif:
Accelerated statistical simulation via on-demand Hermite spline interpolations. ICCAD 2011: 353-360 - [c45]J. Sujatha, Rajshri Jobanputra, Rajiv V. Joshi:
A Tutorial on Enhancing the Level-of-Learning through ICT-Enabled Teaching in Engineering Education. T4E 2011: 303-304 - 2010
- [j9]Rajiv V. Joshi, Rouwaida Kanj, Anthony Pelella, Arthur Tuminaro, Yuen H. Chan:
The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane. IEEE Des. Test Comput. 27(6): 36-45 (2010) - [c44]Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif:
Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. ISLPED 2010: 337-342 - [c43]Jeanne Bickford, Nazmul Habib, John Goss, Robert McMahon, Rajiv V. Joshi, Rouwaida Kanj:
Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test. ISQED 2010: 315-319 - [c42]Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj:
FinFET SRAM Design. VLSI Design 2010: 440-445
2000 – 2009
- 2009
- [j8]Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Yue Tan:
Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics. IEEE J. Solid State Circuits 44(3): 965-976 (2009) - [c41]Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James D. Warnock, Sani R. Nassif:
An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. ICCAD 2009: 497-504 - [c40]Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka:
Statistical yield analysis of silicon-on-insulator embedded DRAM. ISQED 2009: 190-194 - [c39]Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi:
The impact of BEOL lithography effects on the SRAM cell performance and yield. ISQED 2009: 607-612 - 2008
- [c38]Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif:
SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. ISLPED 2008: 87-92 - [c37]Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang:
Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. ISQED 2008: 488-491 - [c36]Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif:
Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. ISQED 2008: 702-707 - [c35]Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif:
A Root-Finding Method for Assessing SRAM Stability. ISQED 2008: 804-809 - 2007
- [j7]Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy:
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectron. J. 38(8-9): 931-941 (2007) - [c34]Vinod Ramadurai, Rajiv V. Joshi, Rouwaida Kanj:
A Disturb Decoupled Column Select 8T SRAM Cell. CICC 2007: 25-28 - [c33]Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang:
A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. ISLPED 2007: 8-13 - [c32]Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif:
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. ISQED 2007: 33-40 - [c31]Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang:
A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. VLSI Design 2007: 665-672 - 2006
- [c30]Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif:
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. DAC 2006: 69-72 - [c29]Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee:
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. DAC 2006: 977-982 - [c28]Rajiv V. Joshi, Kaustav Banerjee, André DeHon:
Tutorial 1: Emerging Technologies for VLSI Design. ISQED 2006: 4 - [c27]John Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr:
A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. ISSCC 2006: 2564-2571 - [c26]Ruchir Puri, Tanay Karnik, Rajiv V. Joshi:
Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. VLSI Design 2006: 5-7 - 2005
- [c25]Rajiv V. Joshi, Yuen H. Chan:
A novel circuit topology for generating and validating digitally sense amplifier differentials for bulk and SOI. ESSCIRC 2005: 371-374 - [c24]Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, Jethro C. Law, Rajiv V. Joshi:
A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction. ICCD 2005: 574-584 - [c23]Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi:
Design of sub-90nm Circuits and Design Methodologies. ISQED 2005: 3-4 - [c22]Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy:
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED 2005: 410-415 - [c21]Rajiv V. Joshi, S. S. Kang, N. Zamdmar, Anda Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez:
Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. VLSI Design 2005: 697-702 - 2004
- [c20]Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Anirudh Devgan:
Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell. ESSCIRC 2004: 211-214 - [c19]Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang:
Nanoscale CMOS circuit leakage power reduction by double-gate device. ISLPED 2004: 102-107 - [c18]Rajiv V. Joshi, K. Kroell, Ching-Te Chuang:
A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. VLSI Design 2004: 832- - [e1]Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy:
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004. ACM 2004 [contents] - 2003
- [j6]E. N. Elnozahy, Rajiv V. Joshi:
Preface. IBM J. Res. Dev. 47(5-6): 521-524 (2003) - [j5]Rosana Rodríguez, James H. Stathis, Barry P. Linder, Rajiv V. Joshi, Ching-Te Chuang:
Influence and model of gate oxide breakdown on CMOS inverters. Microelectron. Reliab. 43(9-11): 1439-1444 (2003) - [j4]Rajiv V. Joshi, Ching-Te Chuang, Samuel K. H. Fung, Fari Assaderaghi, Melanie Sherony, I. Yang, Ghavam V. Shahidi:
PD/SOI SRAM performance in presence of gate-to-body tunneling current. IEEE Trans. Very Large Scale Integr. Syst. 11(6): 1106-1113 (2003) - [c17]Mei-Kei Ieong, Kathryn W. Guarini, Victor Chan, Kerry Bernstein, Rajiv V. Joshi, Jakub Kedzierski, Wilfred Haensch:
Three dimensional CMOS devices and integrated circuits. CICC 2003: 207-213 - [c16]Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown:
New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology. ESSCIRC 2003: 309-312 - [c15]Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri:
Design and CAD Challenges in sub-90nm CMOS Technologies. ICCAD 2003: 129-137 - [c14]Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown:
New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. ISLPED 2003: 168-171 - [c13]Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang:
Strained-si devices and circuits for low-power applications. ISLPED 2003: 180-183 - [c12]Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim:
Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. ISQED 2003: 153-158 - [c11]Rajiv V. Joshi, Kaushik Roy:
Design of Deep Sub-Micron CMOS Circuits. VLSI Design 2003: 15-16 - 2002
- [j3]Rosana Rodríguez, James H. Stathis, Barry P. Linder, Steven P. Kowalczyk, Ching-Te Chuang, Rajiv V. Joshi, Gregory A. Northrop, Kerry Bernstein, Azeez J. Bhavnagarwala, Salvatore Lombardo:
Analysis of the effect of the gate oxide breakdown on SRAM stability. Microelectron. Reliab. 42(9-11): 1445-1448 (2002) - 2001
- [c10]Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang:
SOI for asynchronous dynamic circuits. ACM Great Lakes Symposium on VLSI 2001: 37-42 - [c9]W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi:
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. ISLPED 2001: 263-266 - [c8]Ruchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty:
IBM's Blue Logic Design Methodology-Circuits and Physical Design. VLSI Design 2001: 11-12 - [c7]Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann:
Design Of Provably Correct Storage Arrays. VLSI Design 2001: 196- - 2000
- [j2]Wei Hwang, Rajiv V. Joshi, George Gristede:
A scannable pulse-to-static conversion register array for self-timed circuits. IEEE J. Solid State Circuits 35(1): 125-128 (2000) - [c6]Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang:
"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). ISLPED 2000: 203-206 - [c5]Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang:
A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. VLSI Design 2000: 44-49
1990 – 1999
- 1999
- [j1]Wei Hwang, Rajiv V. Joshi, Walter H. Henkels:
A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file. IEEE J. Solid State Circuits 34(1): 56-67 (1999) - [c4]Rajiv V. Joshi, Wei Hwang:
Design Considerations and Implementation of a High Performance Dynamic Register File. VLSI Design 1999: 526-531 - 1998
- [c3]Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Benjamin D. Parker, T. V. Rajeevakumar, Kevin Stawiasz:
Designing a Testable System on a Chip. VTS 1998: 2-7 - 1997
- [c2]W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi:
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285 - [c1]Wei Hwang, Rajiv V. Joshi, Walter H. Henkels:
A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. ICCD 1997: 712-717
Coauthor Index
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