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ORCIDDhruva Acharyya
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2010 – 2019
- 2013
[j4]Jim Aarestad, Philip Ortiz, Dhruva Acharyya, Jim Plusquellic:
HELP: A Hardware-Embedded Delay PUF. IEEE Des. Test 30(2): 17-25 (2013)- [c13]Raj Chakraborty, Charles Lamech, Dhruva Acharyya, Jim Plusquellic:
A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique. DAC 2013: 59:1-59:10 - [c12]Jim Aarestad, Jim Plusquellic, Dhruva Acharyya:
Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF. HOST 2013: 151-158 - 2011
- [c11]Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal:
Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect. DAC 2011: 534-539 - [c10]Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal:
Measuring within-die spatial variation profile through power supply current measurements. ISQED 2011: 711-715 - [c9]Dhruva Acharyya, Kosuke Miyao, David Ting, Daniel Lam, Robert Smith, Pete Fitzpatrick, Brian Buras, John Williamson:
Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current. ITC 2011: 1-10 - 2010
- [j3]Jim Aarestad, Dhruva Acharyya, Reza M. Rad, Jim Plusquellic:
Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pad IDDQ s. IEEE Trans. Inf. Forensics Secur. 5(4): 893-904 (2010) - [c8]Ryan Helinski, Dhruva Acharyya, Jim Plusquellic:
Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system. DAC 2010: 240-243 - [c7]Dhruva Acharyya, Kanak Agarwal, Jim Plusquellic:
Leveraging existing power control circuits and power delivery architecture for variability measurement. ITC 2010: 645-653
2000 – 2009
- 2009
- [c6]Ryan Helinski, Dhruva Acharyya, Jim Plusquellic:
A physical unclonable function defined using power distribution system equivalent resistance variations. DAC 2009: 676-681 - [c5]Kanak Agarwal, Dhruva Acharyya, Jim Plusquellic:
Characterizing within-die variation from multiple supply port IDDQ measurements. ICCAD 2009: 418-424 - 2007
- [c4]Wei Zhao, Yu Cao, Frank Liu, Kanak Agarwal, Dhruva Acharyya, Sani R. Nassif, Kevin J. Nowka
:
Rigorous extraction of process variations for 65nm CMOS design. ESSCIRC 2007: 89-92 - [c3]Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif:
Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. ISQED 2007: 33-40 - 2006
- [j2]Jim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor, Chintan Patel:
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method. IEEE Des. Test Comput. 23(4): 278-293 (2006) - 2005
- [c2]Dhruva Acharyya, Jim Plusquellic:
Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements. VTS 2005: 433-438 - 2003
- [j1]Chintan Patel, Ernesto Staroswiecki, Smita Pawar, Dhruva Acharyya, Jim Plusquellic:
Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids. J. Electron. Test. 19(6): 611-623 (2003) - [c1]Dhruva Acharyya, Jim Plusquellic:
Impedance Profile of a Commercial Power Grid and Test System. ITC 2003: 709-718
Coauthor Index
aka: Jim Plusquellic
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