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ORCIDHOST 2013: Austin, TX, USA
- 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2013, Austin, TX, USA, June 2-3, 2013. IEEE Computer Society 2013, ISBN 978-1-4799-0559-1
- Clemens Helfmeier, Christian Boit, Dmitry Nedospasov, Jean-Pierre Seifert:
Cloning Physically Unclonable Functions. 1-6 - Stéphanie Kerckhof, François Durvaux, François-Xavier Standaert
, Benoît Gérard:
Intellectual property protection for FPGA designs with soft physical hash functions: First experimental results. 7-12 - Mukund Kalyanaraman, Michael Orshansky:
Novel strong PUF based on nonlinearity of MOSFET subthreshold operation. 13-18 - Dominik Merli, Johann Heyszl, Benedikt Heinz, Dieter Schuster, Frederic Stumpf, Georg Sigl:
Localized electromagnetic analysis of RO PUFs. 19-24 - Filippo Melzani, Andrea Palomba:
Enhancing fault sensitivity analysis through templates. 25-28 - Mark D. Aagaard, Guang Gong, Rajesh K. Mota:
Hardware implementations of the WG-5 cipher for passive RFID tags. 29-34 - Mafalda Cortez, Said Hamdioui, Vincent van der Leest, Roel Maes, Geert Jan Schrijen:
Adapting voltage ramp-up time for temperature noise reduction on memory-based PUFs. 35-40 - Indrasish Saha, Ratan Rahul Jeldi, Rajat Subhra Chakraborty:
Model building attacks on Physically Unclonable Functions using genetic programming. 41-44 - Kan Xiao, Mohammad Tehranipoor:
BISA: Built-in self-authentication for preventing hardware Trojan insertion. 45-50 - Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
A bulk built-in sensor for detection of fault attacks. 51-54 - Li Li, Hai Zhou:
Structural transformation for best-possible obfuscation of sequential circuits. 55-60 - David W. Palmer, Parbati Kumar Manna:
An efficient algorithm for identifying security relevant logic and vulnerabilities in RTL designs. 61-66 - Wenchao Li, Adrià Gascón, Pramod Subramanyan, Wei Yang Tan, Ashish Tiwari, Sharad Malik, Natarajan Shankar, Sanjit A. Seshia:
WordRev: Finding word-level structures in a sea of bit-level gates. 67-74 - Obaid Khalid, Carsten Rolfes, Andreas Ibing:
On implementing trusted boot for embedded systems. 75-80 - Aydin Aysu, Cameron Patterson, Patrick Schaumont:
Low-cost and area-efficient FPGA implementations of lattice-based cryptography. 81-86 - Bodhisatwa Mazumdar, Debdeep Mukhopadhyay, Indranil Sengupta:
Design and implementation of rotation symmetric S-boxes with high nonlinearity and high DPA resilience. 87-92 - Vikram B. Suresh, Daniele Antonioli, Wayne P. Burleson:
On-chip lightweight implementation of reduced NIST randomness test suite. 93-98 - Yier Jin, Bo Yang, Yiorgos Makris:
Cycle-accurate information assurance by proof-carrying based signal sensitivity tracing. 99-106 - Jie Zhang, Qiang Xu:
On hardware Trojan design and implementation at register-transfer level. 107-112 - Sheng Wei, Miodrag Potkonjak:
Malicious circuitry detection using fast timing characterization via test points. 113-118 - Cyril Roscian, Jean-Max Dutertre, Assia Tria:
Frontside laser fault injection on cryptosystems - Application to the AES' last round -. 119-124 - Mostafa M. I. Taha, Patrick Schaumont:
Side-Channel Analysis of MAC-Keccak. 125-130 - Philip Hodgers, Neil Hanley, Máire O'Neill:
Pre-processing power traces with a phase-sensitive detector. 131-136 - Jeroen Delvaux, Ingrid Verbauwhede:
Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise. 137-142 - J. Ju, Ray Chakraborty, Charles Lamech, Jim Plusquellic:
Stability analysis of a physical unclonable function based on metal resistance variations. 143-150 - Jim Aarestad, Jim Plusquellic, Dhruva Acharyya:
Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF. 151-158
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