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ORCID51st DAC 2014: San Francisco, CA, USA
- The 51st Annual Design Automation Conference 2014, DAC '14, San Francisco, CA, USA, June 1-5, 2014. ACM 2014, ISBN 978-1-4503-2730-5
- Johannes Koesters, Alex Goryachev:
Verification of Non-Mainline Functions in Todays Processor Chips. 1:1-1:3 - Yael Abarbanel, Eli Singerman, Moshe Y. Vardi:
Validation of SoC Firmware-Hardware Flows: Challenges and Solution Directions. 2:1-2:4 - Daniel J. Sorin, Opeoluwa Matthews, Meng Zhang:
Architecting Dynamic Power Management to be Formally Verifiable. 3:1-3:3 - Moongon Jung, Taigon Song, Yang Wan, Yarui Peng
, Sung Kyu Lim:
On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective. 4:1-4:6 - Wen-Hao Liu, Min-Sheng Chang, Ting-Chi Wang:
Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs. 5:1-5:6 - Pei-Ci Wu, Martin D. F. Wong, Ivailo Nedelchev, Sarvesh Bhardwaj, Vidyamani Parkhe:
On Timing Closure: Buffer Insertion for Hold-Violation Removal. 6:1-6:6 - Stephan Held, Ulrike Schorr:
Post-Routing Latch Optimization for Timing Closure. 7:1-7:6 - Jui-Hung Chien, Ruei-Siang Hsu, Hsueh-Ju Lin, Ka-Yi Yeh, Shih-Chieh Chang:
Contactless Stacked-die Testing for Pre-bond Interposers. 8:1-8:6 - Parijat Mukherjee, Peng Li:
Leveraging pre-silicon data to diagnose out-of-specification failures in mixed-signal circuits. 9:1-9:6 - Martin Andraud, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu:
One-Shot Calibration of RF Circuits Based on Non-Intrusive Sensors. 10:1-10:2 - Marcin Gebala, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
On Using Implied Values in EDT-based Test Compression. 11:1-11:6 - Florian Kriebel, Semeen Rehman, Duo Sun, Muhammad Shafique, Jörg Henkel:
ASER: Adaptive Soft Error Resilience for Reliability-Heterogeneous Processors in the Dark Silicon Era. 12:1-12:6 - Aviral Shrivastava, Abhishek Rhisheekesan, Reiley Jeyapaul, Carole-Jean Wu:
Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors. 13:1-13:6 - Devendra Rai, Pengcheng Huang, Nikolay Stoimenov, Lothar Thiele:
An Efficient Real Time Fault Detection and Tolerance Framework Validated on the Intel SCC Processor. 14:1-14:6 - Faramarz Khosravi, Felix Reimann, Michael Glaß, Jürgen Teich:
Multi-Objective Local-Search Optimization using Reliability Importance Measuring. 15:1-15:6 - Mingui Sun, Lora E. Burke, Zhi-Hong Mao, Yiran Chen, Hsin-Chen Chen, Yicheng Bai, Yuecheng Li, Chengliu Li, Wenyan Jia:
eButton: A Wearable Computer for Health Monitoring and Personal Assistance. 16:1-16:6 - Rubén Braojos, Hossein Mamaghanian, Alair Dias Junior, Giovanni Ansaloni, David Atienza, Francisco J. Rincón, Srinivasan Murali:
Ultra-Low Power Design of Wearable Cardiac Monitoring Systems. 17:1-17:6 - Philip Axer, Daniel Thiele, Rolf Ernst, Jonas Diemer:
Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB Networks. 18:1-18:6 - Chung-Wei Lin, Lei Rao, Paolo Giusto, Joseph D'Ambrosio, Alberto L. Sangiovanni-Vincentelli:
An Efficient Wire Routing and Wire Sizing Algorithm for Weight Minimization of Automotive Systems. 19:1-19:6 - Florian Sagstetter, Sidharta Andalam, Peter Waszecki, Martin Lukasiewycz, Hauke Stähle, Samarjit Chakraborty, Alois C. Knoll:
Schedule Integration Framework for Time-Triggered Automotive Architectures. 20:1-20:6 - Armin Wasicek, Patricia Derler, Edward A. Lee:
Aspect-oriented Modeling of Attacks in Automotive Cyber-Physical Systems. 21:1-21:6 - Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Glenn Farrall, Franck Wartel, Francisco J. Cazorla:
Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware. 22:1-22:6 - Prahladavaradan Sampath, A. C. Rajeev, S. Ramesh:
Translation Validation for Stateflow to C. 23:1-23:6 - Ryan H.-M. Huang, Charles H.-P. Wen:
Advanced Soft-Error-Rate (SER) Estimation with Striking-Time and Multi-Cycle Effects. 24:1-24:6 - Carles Hernández, Jaume Abella:
LiVe: Timely Error Detection in Light-Lockstep Safety Critical Systems. 25:1-25:6 - Azad Naeemi, Ahmet Ceyhan, Vachan Kumar, Chenyun Pan, Rouhollah M. Iraei, Shaloo Rakheja:
BEOL Scaling Limits and Next Generation Technology Prospects. 26:1-26:6 - Duckhwan Kim, Saibal Mukhopadhyay:
On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die Stacking. 27:1-27:6 - Yarui Peng, Dusan Petranovic, Sung Kyu Lim:
Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling. 28:1-28:6 - Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li:
BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits. 29:1-29:6 - Li Yu, Sharad Saxena, Christopher Hess, Ibrahim Abe M. Elfadel, Dimitri A. Antoniadis, Duane S. Boning:
Remembrance of Transistors Past: Compact Model Parameter Extraction Using Bayesian Inference and Incomplete New Measurements. 30:1-30:6 - Shin-Haeng Kang, Hoeseok Yang, Sungchan Kim, Iuliana Bacivarov, Soonhoi Ha, Lothar Thiele:
Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCs. 31:1-31:6 - Hongyan Zhang, Michael A. Kochte, Michael E. Imhof, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel:
GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems. 32:1-32:6 - Haris Javaid, Yusuke Yachide, Su Myat Min Shwe, Haseeb Bokhari, Sri Parameswaran:
FALCON: A Framework for HierarchicAL Computation of Metrics for CompONent-Based Parameterized SoCs. 33:1-33:6 - Arunprasath Shankar, Bhanu Pratap Singh, Francis G. Wolff, Christos A. Papachristou:
Ontology-guided Conceptual Analysis of Design Specifications. 34:1-34:6 - Wujie Wen, Yaojun Zhang, Mengjie Mao, Yiran Chen:
State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System. 35:1-35:6 - Mengying Zhao, Lei Jiang, Youtao Zhang, Chun Jason Xue:
SLC-enabled Wear Leveling for MLC PCM Considering Process Variation. 36:1-36:6 - Fazal Hameed, Lars Bauer, Jörg Henkel:
Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture. 37:1-37:6 - Hsiang-Jen Tsai, Chien-Chih Chen, Keng-Hao Yang, Ting-Chin Yang, Li-Yue Huang, Ching-Hao Chuang, Meng-Fan Chang, Tien-Fu Chen:
Leveraging Data Lifetime for Energy-Aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination. 38:1-38:6 - Wei Liu, Jian-Jia Chen, Anas Toma, Tei-Wei Kuo, Qingxu Deng:
Computation Offloading by Using Timing Unreliable Components in Real-Time Systems. 39:1-39:6 - Anuj Pathania, Qing Jiao, Alok Prakash, Tulika Mitra:
Integrated CPU-GPU Power Management for 3D Mobile Games. 40:1-40:6 - Dongwon Kim, Nohyun Jung, Hojung Cha:
Content-centric Display Energy Management for Mobile Devices. 41:1-41:6 - Chun-Han Lin, Chih-Kai Kang, Pi-Cheng Hsiu:
Catch Your Attention: Quality-retaining Power Saving on Mobile OLED Displays. 42:1-42:6 - Rafael Zalman, Albrecht Mayer:
A Secure but still Safe and Low Cost Automotive Communication Technique. 43:1-43:5 - Sophie Quinton, Torsten T. Bone, Julien Hennig, Moritz Neukirchner, Mircea Negrean, Rolf Ernst:
Typical Worst Case Response-Time Analysis and its Use in Automotive Network Design. 44:1-44:6 - Christoph Stoermer, Ghizlane Tibba:
Powertrain Co-Simulation using AUTOSAR and the Functional Mockup Interface standard. 45:1 - Vikas Chandra:
Monitoring Reliability in Embedded Processors - A Multi-layer View. 46:1-46:6 - Jörg Henkel, Lars Bauer, Hongyan Zhang, Semeen Rehman, Muhammad Shafique:
Multi-Layer Dependability: From Microarchitecture to Application Level. 47:1-47:6 - Nikil D. Dutt, Puneet Gupta, Alex Nicolau, Abbas BanaiyanMofrad, Mark Gottscho, Majid Shoushtari:
Multi-Layer Memory Resiliency. 48:1-48:6 - Veit Kleeberger, Petra R. Maier, Ulf Schlichtmann:
Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level Resilience. 49:1-49:6 - Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang:
Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. 50:1-50:6 - Yixiao Ding, Chris Chu, Wai-Kei Mak:
Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout. 51:1-51:6 - Jhih-Rong Gao, Xiaoqing Xu, Bei Yu, David Z. Pan:
MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction. 52:1-52:6 - Bei Yu, David Z. Pan:
Layout Decomposition for Quadruple Patterning Lithography and Beyond. 53:1-53:6 - Chi-Yuan Liu, Hui-Ju Katherine Chiang, Yao-Wen Chang, Jie-Hong R. Jiang:
Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification. 54:1-54:6 - Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang:
Directed Self-Assembly (DSA) Template Pattern Verification. 55:1-55:6 - Amir Nahir, Manoj Dusanapudi, Shakti Kapoor, Kevin Reick, Wolfgang Roesner, Klaus-Dieter Schubert, Keith Sharp, Greg Wetli:
Post-Silicon Validation of the IBM POWER8 Processor. 56:1-56:6 - Monica Farkash, Bryan G. Hickerson, Michael L. Behm:
Coverage Learned Targeted Validation for Incremental HW Changes. 57:1-57:6 - Allon Adir, Dave Goodman, Daniel Hershcovich, Oz Hershkovitz, Bryan G. Hickerson, Karen Holtz, Wisam Kadry, Anatoly Koyfman, John M. Ludden, Charles Meissner, Amir Nahir, Randall R. Pratt, Mike Schiffli, Brett St. Onge, Brian W. Thompto, Elena Tsanko, Avi Ziv:
Verification of Transactional Memory in POWER8. 58:1-58:6 - Zhimiao Chen, Yifan Wang, Lei Liao, Ye Zhang, Aytac Atac, Jan Henning Müller, Ralf Wunderlich, Stefan Heinen:
A SystemC Virtual Prototyping based Methodology for Multi-Standard SoC Functional Verification. 59:1-59:6 - Supratik Chakraborty, Kuldeep S. Meel, Moshe Y. Vardi:
Balancing Scalability and Uniformity in SAT Witness Generator. 60:1-60:6 - Viraj Athavale, Sai Ma, Samuel Hertz, Shobha Vasudevan:
Code Coverage of Assertions Using RTL Source Code Analysis. 61:1-61:6 - Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim:
Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations. 62:1-62:6 - Enes Eken, Yaojun Zhang, Wujie Wen, Rajiv V. Joshi, Hai Li, Yiran Chen:
A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability. 63:1-63:6 - Marjan Asadinia, Mohammad Arjomand, Hamid Sarbazi-Azad:
OD3P: On-Demand Page Paired PCM. 64:1-64:6 - Anirudh Iyengar, Swaroop Ghosh:
Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory. 65:1-65:6 - Seyedhamidreza Motaman, Swaroop Ghosh:
Simultaneous Sizing, Reference Voltage and Clamp Voltage Biasing for Robustness, Self-Calibration and Testability of STTRAM Arrays. 66:1-66:2 - Hassan Albalawi, Yuanning Li, Xin Li:
Computer-Aided Design of Machine Learning Algorithm: Training Fixed-Point Classifier for On-Chip Low-Power Implementation. 67:1-67:6 - Santanu Sarma, Nalini Venkatasubramanian, Nikil D. Dutt:
Sense-making from Distributed and Mobile Sensing Data: A Middleware Perspective. 68:1-68:6 - Christian Wietfeld, Christoph Ide, Bjoern Dusza:
Resource Efficient Mobile Communications for Crowd-Sensing. 69:1-69:6 - Xiang Chen, Yiran Chen, Mian Dong, Jianzhong (Charlie) Zhang:
Demystifying Energy Usage in Smartphones. 70:1-70:5 - Wolfgang Ecker, Michael Velten, Leily Zafari, Ajay Goyal:
Metasynthesis for Designing Automotive SoCs. 71:1-71:6 - Qing Rao, Christian Grünler, Markus Hammori, Samarjit Chakraborty:
Design Methods for Augmented Reality In-Vehicle Infotainment Systems. 72:1-72:6 - Mehdi Kabir, Mircea R. Stan:
Computing with Hybrid CMOS/STO Circuits. 73:1-73:6 - Suman Datta, Nikhil Shukla, Matthew Cotter, Abhinav Parihar, Arijit Raychowdhury:
Neuro Inspired Computing with Coupled Relaxation Oscillators. 74:1-74:6 - Liang Chen, Mehdi Baradaran Tahoori:
Reliability-aware Register Binding for Control-Flow Intensive Designs. 75:1-75:6 - Steve Dai, Mingxing Tan, Kecheng Hao, Zhiru Zhang:
Flushing-Enabled Loop Pipelining for High-Level Synthesis. 76:1-76:6 - Jason Cong, Peng Li, Bingjun Xiao, Peng Zhang:
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers. 77:1-77:6 - Feng Liu, Soumyadeep Ghosh, Nick P. Johnson, David I. August:
CGPA: Coarse-Grained Pipelined Accelerators. 78:1-78:6 - Cheng Zhuo, Houle Gan, Wei-Kai Shih:
Early-Stage Power Grid Design: Extraction, Modeling and Optimization. 79:1-79:6 - Xin Huang, Tan Yu, Valeriy Sukharev, Sheldon X.-D. Tan:
Physics-based Electromigration Assessment for Power Grid Networks. 80:1-80:6 - Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng:
MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks. 81:1-81:6 - Wei Wu, Wenyao Xu, Rahul Krishnan, Yen-Lung Chen, Lei He:
REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage. 82:1-82:6 - Yu-Ming Chang, Yuan-Hao Chang, Jian-Jia Chen, Tei-Wei Kuo, Hsiang-Pang Li, Hang-Ting Lue:
On Trading Wear-leveling with Heal-leveling. 83:1-83:6 - Semeen Rehman, Florian Kriebel, Duo Sun, Muhammad Shafique, Jörg Henkel:
dTune: Leveraging Reliable Code Generation for Adaptive Dependability Tuning under Process Variation and Aging-Induced Effects. 84:1-84:6 - Po-Hsien Tseng, Pi-Cheng Hsiu, Chin-Chiang Pan, Tei-Wei Kuo:
User-Centric Energy-Efficient Scheduling on Multi-Core Mobile Devices. 85:1-85:6 - Matthias Beckert, Moritz Neukirchner, Rolf Ernst, Stefan M. Petters:
Sufficient Temporal Independence and Improved Interrupt Latencies in a Real-Time Hypervisor. 86:1-86:6 - Ujjwal Guin, Xuehui Zhang, Domenic Forte, Mohammad Tehranipoor:
Low-cost On-Chip Structures for Combating Die and IC Recycling. 87:1-87:6 - Yu Zheng, Abhishek Basak, Swarup Bhunia:
CACI: Dynamic Current Analysis Towards Robust Recycled Chip Identification. 88:1-88:6 - Mingze Gao, Khai Lai, Gang Qu:
A Highly Flexible Ring Oscillator PUF. 89:1-89:6 - Sheng Wei, James B. Wendt, Ani Nahapetian, Miodrag Potkonjak:
Reverse Engineering and Prevention Techniques for Physical Unclonable Functions Using Side Channels. 90:1-90:6 - Likun Xia, Tran Duc Chung, Khairil Anwar Abu Kassim:
An Automobile Detection Algorithm Development for Automated Emergency Braking System. 91:1-91:6 - Chuansheng Dong, Haibo Zeng, Minghua Chen:
A Cost Efficient Online Algorithm for Automotive Idling Reduction. 92:1-92:6 - Asim Munawar, Shuichi Shimizu:
Scalable Co-Simulation of Functional Models With Accurate Event Exchange. 93:1-93:6 - Ze Ni, Avenir Kobetski, Jakob Axelsson:
Design and Implementation of a Dynamic Component Model for Federated AUTOSAR Systems. 94:1-94:6 - Guillermo Rodríguez-Navas, Cristina Cerschi Seceleanu, Hans Hansson, Mattias Nyberg, Oscar Ljungkrantz, Henrik Lönn:
Automated Specification and Verification of Functional Safety in Heavy-Vehicles: the VeriSpec Approach. 95:1-95:4 - Felix Reimann, Michael Glaß, Jürgen Teich, Alejandro Cook, Laura Rodríguez Gómez, Dominik Ull, Hans-Joachim Wunderlich, Piet Engelke, Ulrich Abelein:
Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures. 96:1-96:9 - Qian Zhang, Feng Yuan, Rong Ye, Qiang Xu:
ApproxIt: An Approximate Computing Framework for Iterative Methods. 97:1-97:6 - Yu-Guang Chen, Tao Wang, Kuan-Yu Lai, Wan-Yu Wen, Yiyu Shi, Shih-Chieh Chang:
Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs. 98:1-98:6 - Hang Zhang, Mateja Putic, John C. Lach:
Low Power GPGPU Computation with Imprecise Hardware. 99:1-99:6 - Mark Gottscho, Abbas BanaiyanMofrad, Nikil D. Dutt, Alex Nicolau, Puneet Gupta:
Power / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches. 100:1-100:6 - Mohammad Fattah, Maurizio Palesi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
SHiFA: System-Level Hierarchy in Run-Time Fault-Aware Management of Many-Core Systems. 101:1-101:6 - Pengju Ren, Qingxin Meng, Xiaowei Ren, Nanning Zheng:
Fault-tolerant Routing for On-chip Network Without Using Virtual Channels. 102:1-102:6 - Supriya Rao, Supreet Jeloka, Reetuparna Das, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge:
VIX: Virtual Input Crossbar for Efficient Switch Allocation. 103:1-103:6 - Yuankun Xue, Zhiliang Qian, Paul Bogdan, Fan Ye, Chi-Ying Tsui:
Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis. 104:1-104:6 - Jan Heisswolf, Aurang Zaib, Andreas Zwinkau, Sebastian Kobbe, Andreas Weichslgartner, Jürgen Teich, Jörg Henkel, Gregor Snelting, Andreas Herkersdorf, Jürgen Becker:
CAP: Communication Aware Programming. 105:1-105:6 - Keni Qiu, Qing'an Li, Chun Jason Xue:
Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM. 106:1-106:6 - Mahdi Hamzeh, Aviral Shrivastava, Sarma B. K. Vrudhula:
Branch-Aware Loop Mapping on CGRAs. 107:1-107:6 - Luc Waeijen, Dongrui She, Henk Corporaal, Yifan He:
Reduction Operator for Wide-SIMDs Reconsidered. 108:1-108:6 - Joonho Kong, Farinaz Koushanfar, Praveen Kumar Pendyala, Ahmad-Reza Sadeghi, Christian Wachsmann:
PUFatt: Embedded Platform Attestation Based on Novel Processor-Based PUFs. 109:1-109:6 - Tobias Oder, Thomas Pöppelmann, Tim Güneysu:
Beyond ECDSA and RSA: Lattice-based Digital Signatures on Constrained Devices. 110:1-110:6 - Anthony Van Herrewege, Ingrid Verbauwhede:
Software Only, Extremely Compact, Keccak-based Secure PRNG on ARM Cortex-M. 111:1-111:6 - Ruan de Clercq, Leif Uhsadel, Anthony Van Herrewege, Ingrid Verbauwhede:
Ultra Low-Power implementation of ECC on the ARM Cortex-M0+. 112:1-112:6 - Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Grüttner, Thomas Kruse, Christoph Kuznik, Hoang Minh Le, Andreas Mauderer, Wolfgang Müller, Daniel Müller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl:
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. 113:1-113:6 - Karthik Swaminathan, Huichu Liu, Xueqing Li, Moon Seok Kim, Jack Sampson, Vijaykrishnan Narayanan:
Steep Slope Devices: Enabling New Architectural Paradigms. 114:1-114:6 - Parijat Mukherjee, Chirayu S. Amin, Peng Li:
Approximate property checking of mixed-signal circuits. 115:1-115:6 - Palak Bhushan:
A Rigorous Graphical Technique for Predicting Sub-harmonic Injection Locking in LC Oscillators. 116:1-116:8 - Jian Deng, Kim Batselier, Yang Zhang, Ngai Wong:
An Efficient Two-level DC Operating Points Finder for Transistor Circuits. 117:1-117:6 - Frank Liu, Peter Feldmann:
A Time-Unrolling Method to Compute Sensitivity of Dynamic Systems. 118:1-118:6 - Ifigeneia Apostolopoulou, Konstantis Daloukas, Nestor E. Evmorfopoulos, George I. Stamoulis:
Selective Inversion of Inductance Matrix for Large-Scale Sparse RLC Simulation. 119:1-119:6 - Sangho Youn, Chenjie Gu, Jaeha Kim:
Probabilistic Bug Localization via Statistical Inference based on Partially Observed Data. 120:1-120:6 - Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis J.-H. Huang, Chin-Chi Teng, Chung-Kuan Cheng:
ePlace: Electrostatics Based Placement Using Nesterov's Method. 121:1-121:6 - Sergiy Popovych, Hung-Hao Lai, Chieh-Min Wang, Yih-Lang Li, Wen-Hao Liu, Ting-Chi Wang:
Density-aware Detailed Placement with Instant Legalization. 122:1-122:6 - Tao Lin, Chris Chu:
POLAR 2.0: An Effective Routability-Driven Placer. 123:1-123:6 - Yi-Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang:
Routability-Driven Blockage-Aware Macro Placement. 124:1-124:6 - Hua Xiang, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu:
Row Based Dual-VDD Island Generation and Placement. 125:1-125:6 - Ke Wang, Brett H. Meyer, Runjie Zhang, Mircea R. Stan, Kevin Skadron:
Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization. 126:1-126:6 - Firew Siyoum, Marc Geilen, Henk Corporaal:
Symbolic Analysis of Dataflow Applications Mapped onto Shared Heterogeneous Resources. 127:1-127:6 - Giuseppe Di Guglielmo, Christian Pilato, Luca P. Carloni:
A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCs. 128:1-128:6 - Chien-Chih Chen, Yin-Chi Peng, Cheng-Fen Chen, Wei-Shan Wu, Qinghao Min, Pen-Chung Yew, Weihua Zhang, Tien-Fu Chen:
DAPs: Dynamic Adjustment and Partial Sampling for Multithreaded/Multicore Simulation. 129:1-129:6 - Jong Chul Lee, Roman Lysecky:
Area-Efficient Event Stream Ordering for Runtime Observability of Embedded Systems. 130:1-130:6 - Pengcheng Huang, Hoeseok Yang, Lothar Thiele:
On the Scheduling of Fault-Tolerant Mixed-Criticality Systems. 131:1-131:6 - Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini:
An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing. 132:1-132:6 - Lucas Davi, Patrick Koeberl, Ahmad-Reza Sadeghi:
Hardware-Assisted Fine-Grained Control-Flow Integrity: Towards Efficient Protection of Embedded Systems Against Software Exploitation. 133:1-133:6 - Allon Adir, Alex Goryachev, Lev Greenberg, Tamer Salman:
Using a High-Level Test Generation Expert System for Testing In-Car Networks. 134:1-134:6 - Donghwa Shin, Enrico Macii, Massimo Poncino:
Statistical Battery Models and Variation-Aware Battery Management. 135:1-135:6 - Tianshu Wei, Taeyoung Kim, Sangyoung Park, Qi Zhu, Sheldon X.-D. Tan, Naehyuck Chang, Sadrul Ula, Mehdi Maasoumy:
Battery Management and Application for Energy-Efficient Buildings. 136:1-136:6 - Vivek S. Nandakumar, Malgorzata Marek-Sadowska:
System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs. 137:1-137:6 - Youngsub Ko, Taeyoung Kim, Youngmin Yi, Myungsun Kim, Soonhoi Ha:
Hardware-in-the-loop Simulation for CPU/GPU Heterogeneous Platforms. 138:1-138:6 - Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes. 139:1-139:6 - Zehan Cui, Licheng Chen, Yungang Bao, Mingyu Chen:
A Swap-based Cache Set Index Scheme to Leverage both Superpage and Page Coloring Optimizations. 140:1-140:6 - Chun-Xun Lin, Chih-Hung Liu, I-Che Chen, D. T. Lee, Tsung-Yi Ho:
An Efficient Bi-criteria Flow Channel Routing Algorithm For Flow-based Microfluidic Biochips. 141:1-141:6 - Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler:
Exact One-pass Synthesis of Digital Microfluidic Biochips. 142:1-142:6 - Qin Wang, Yiren Shen, Hailong Yao, Tsung-Yi Ho, Yici Cai:
Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips. 143:1-143:6 - Sudip Roy, Srijan Kumar, Partha Pratim Chakrabarti, Bhargab B. Bhattacharya, Krishnendu Chakrabarty:
Demand-Driven Mixture Preparation and Droplet Streaming using Digital Microfluidic Biochips. 144:1-144:6 - Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li:
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs. 145:1-145:6 - Liang Shi, Kaijie Wu, Mengying Zhao, Chun Jason Xue, Edwin Hsing-Mean Sha:
Retention Trimming for Wear Reduction of Flash Memory Storage Systems. 146:1-146:6 - Yuan-Hung Kuan, Yuan-Hao Chang, Po-Chun Huang, Kam-yiu Lam:
Space-Efficient Multiversion Index Scheme for PCM-based Embedded Database Systems. 147:1-147:6 - Chi Zhang, Yi Wang, Tianzheng Wang, Renhai Chen, Duo Liu, Zili Shao:
Deterministic Crash Recovery for NAND Flash Based Storage Systems. 148:1-148:6 - Zhenkun Yang, Kecheng Hao, Kai Cong, Li Lei, Sandip Ray, Fei Xie:
Scalable Certification Framework for Behavioral Synthesis Front-End. 149:1-149:6 - Honghuang Lin, Peng Li:
Parallel Hierarchical Reachability Analysis for Analog Verification. 150:1-150:6 - Udo Krautz, Viresh Paruthi, Anand Arunagiri, Sujeet Kumar, Shweta Pujar, Tina Babinsky:
Automatic Verification of Floating Point Units. 151:1-151:6 - Tim Pruss, Priyank Kalla, Florian Enescu:
Equivalence Verification of Large Galois Field Arithmetic Circuits using Word-Level Abstraction via Gröbner Bases. 152:1-152:6 - Ronald P. Cocchi, James P. Baukus, Lap Wai Chow, Bryan J. Wang:
Circuit Camouflage Integration for Hardware IP Protection. 153:1-153:5 - Steve Trimberger, Jason Moore:
FPGA Security: From Features to Capabilities to Trusted Systems. 154:1-154:4 - Yu Liu, Ke Huang, Yiorgos Makris:
Hardware Trojan Detection through Golden Chip-Free Statistical Side-Channel Fingerprinting. 155:1-155:6 - Kaushik Vaidyanathan, Bishnu Prasad Das, Larry T. Pileggi:
Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack. 156:1-156:6 - Xiaotong Cui, Kun Ma, Liang Shi, Kaijie Wu:
High-Level Synthesis for Run-Time Hardware Trojan Detection and Recovery. 157:1-157:6 - Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy:
Fort-NoCs: Mitigating the Threat of a Compromised NoC. 158:1-158:6 - Li-C. Wang, Magdy S. Abadir:
Data Mining In EDA - Basic Principles, Promises, and Constraints. 159:1-159:6 - Jia Zhan, Yuan Xie, Guangyu Sun:
NoC-Sprinting: Interconnect for Fine-Grained Sprinting in the Dark Silicon Era. 160:1-160:6 - Haseeb Bokhari, Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran:
darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon. 161:1-161:6 - Ritesh Parikh, Reetuparna Das, Valeria Bertacco:
Power-Aware NoCs through Routing and Topology Reconfiguration. 162:1-162:6 - Nilmini Abeyratne, Supreet Jeloka, Yiping Kang, David T. Blaauw, Ronald G. Dreslinski, Reetuparna Das, Trevor N. Mudge:
Quality-of-Service for a High-Radix Switch. 163:1-163:6 - Ye Wang, Michael Orshansky, Constantine Caramanis:
Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization. 164:1-164:6 - Mark Po-Hung Lin, Vincent Wei-Hao Hsiao, Chun-Yu Lin:
Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC. 165:1-165:6 - Wulong Liu, Guoqing Chen, Xue Han, Yu Wang, Yuan Xie, Huazhong Yang:
Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case. 166:1-166:6 - Aytac Atac, Zhimiao Chen, Lei Liao, Yifan Wang, Martin Schleyer, Ye Zhang, Ralf Wunderlich, Stefan Heinen:
An HDL-Based System Design Methodology for Multistandard RF SoC's. 167:1-167:6 - Xiaoming Chen, Yu Wang, Yun Liang, Yuan Xie, Huazhong Yang:
Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUs. 168:1-168:6 - Ting Wang, Qiang Xu:
On the Simulation of NBTI-Induced Performance Degradation Considering Arbitrary Temperature and Voltage Variations. 169:1-169:6 - Anup Das, Rishad A. Shafik, Geoff V. Merrett, Bashir M. Al-Hashimi, Akash Kumar, Bharadwaj Veeravalli:
Reinforcement Learning-Based Inter- and Intra-Application Thermal Optimization for Lifetime Improvement of Multicore Systems. 170:1-170:6 - Xinfei Guo, Wayne P. Burleson, Mircea R. Stan:
Modeling and Experimental Demonstration of Accelerated Self-Healing Techniques. 171:1-171:6 - Mukesh Reddy Rudra, Nimmy Anna Daniel, Varun Nagoorkar, David H. K. Hoe:
Designing Stealthy Trojans with Sequential Logic: A Stream Cipher Case Study. 172:1-172:4 - Dean Sullivan, Jeff Biggers, Guidong Zhu, Shaojie Zhang, Yier Jin:
FIGHT-Metric: Functional Identification of Gate-Level Hardware Trustworthiness. 173:1-173:4 - Nektarios Georgios Tsoutsos, Charalambos Konstantinou, Michail Maniatakos:
Advanced Techniques for Designing Stealthy Hardware Trojans. 174:1-174:4 - Adam Waksman, Jeyavijayan Rajendran, Matthew Suozzo, Simha Sethumadhavan:
A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification. 175:1-175:4 - Weiwei Shan, Longxing Shi, Xingyuan Fu, Xiao Zhang, Chaoxuan Tian, Zhipeng Xu, Jun Yang, Jie Li:
A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms. 176:1-176:6 - Debapriya Basu Roy, Debdeep Mukhopadhyay, Masami Izumi, Junko Takahashi:
Tile Before Multiplication: An Efficient Strategy to Optimize DSP Multiplier for Accelerating Prime Field ECC for NIST Curves. 177:1-177:6 - Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu:
Secure Memristor-based Main Memory. 178:1-178:6 - Md. Tauhidur Rahman, Kan Xiao, Domenic Forte, Xuhei Zhang, Zhijie Jerry Shi, Mohammad Tehranipoor:
TI-TRNG: Technology Independent True Random Number Generator. 179:1-179:6 - Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Karthik Gururaj, Glenn Reinman:
Accelerator-Rich Architectures: Opportunities and Progresses. 180:1-180:6 - Rafael Ubal, Dana Schaa, Perhaad Mistry, Xiang Gong, Yash Ukidave, Zhongliang Chen, Gunar Schirner, David R. Kaeli:
Exploring the Heterogeneous Design Space for both Performance and Reliability. 181:1-181:6 - Vasileios Kontorinis, Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Dean M. Tullsen, Houman Homayoun:
Enabling Dynamic Heterogeneity Through Core-on-Core Stacking. 182:1-182:6 - Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Ivan Miro Panades, Pascal Benoit, Lionel Torres:
Power management through DVFS and dynamic body biasing in FD-SOI circuits. 183:1-183:6 - Selçuk Köse:
Thermal Implications of On-Chip Voltage Regulation: Upcoming Challenges and Possible Solutions. 184:1-184:6 - Muhammad Shafique, Siddharth Garg, Jörg Henkel, Diana Marculescu:
The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives. 185:1-185:6 - Mohammad Javad Dousti, Massoud Pedram:
Power-Aware Deployment and Control of Forced-Convection and Thermoelectric Coolers. 186:1-186:6 - Xing Hu, Yi Xu, Jun Ma, Guoqing Chen, Yu Hu, Yuan Xie:
Thermal-Sustainable Power Budgeting for Dynamic Threading. 187:1-187:6 - Yi Liang, Deming Chen:
ClusRed: Clustering and Network Reduction Based Probabilistic Optimal Power Flow Analysis for Large-Scale Smart Grids. 188:1-188:6 - Mahmoud Elbayoumi, Mihir Choudhury, Victor N. Kravets, Andrew Sullivan, Michael S. Hsiao, Mustafa Y. ElNainay:
TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis. 189:1-189:6 - Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides:
Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. 190:1-190:6 - Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang:
Functional ECO Using Metal-Configurable Gate-Array Spare Cells. 191:1-191:6 - Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang:
Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. 192:1-192:6 - Yehdhih Ould Mohammed Moctar, Philip Brisk:
Parallel FPGA Routing based on the Operator Formulation. 193:1-193:6 - Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization. 194:1-194:6 - Abbas Rahimi, Amirali Ghofrani, Miguel Angel Lastras-Montaño, Kwang-Ting Cheng, Luca Benini, Rajesh K. Gupta:
Energy-Efficient GPGPU Architectures via Collaborative Compilation and Memristive Memory-Based Computing. 195:1-195:6 - Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai (Helen) Li:
Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory. 196:1-196:6 - Mohammad Hossein Samavatian, Hamed Abbasitabar, Mohammad Arjomand, Hamid Sarbazi-Azad:
An Efficient STT-RAM Last Level Cache Architecture for GPUs. 197:1-197:6 - Mladen Slijepcevic, Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla:
Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems. 198:1-198:6 - Vivek Joy Kozhikkottu, Abhisek Pan, Vijay S. Pai, Sujit Dey, Anand Raghunathan:
Variation Aware Cache Partitioning for Multithreaded Programs. 199:1-199:6 - Josef Schneider, Jorgen Peddersen, Sri Parameswaran:
MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis. 200:1-200:6 - Saman Kiamehr, Thomas H. Osiecki, Mehdi Baradaran Tahoori, Sani R. Nassif:
Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach. 201:1-201:6 - Jiangyi Li, Mingoo Seok:
Robust and In-Situ Self-Testing Technique for Monitoring Device Aging Effects in Pipeline Circuits. 202:1-202:6 - Ketul Sutaria, Athul Ramkumar, Rongjun Zhu, Renju Rajveev, Yao Ma, Yu Cao:
BTI-Induced Aging under Random Stress Waveforms: Modeling, Simulation and Silicon Validation. 203:1-203:6 - Kuan-Hsien Ho, Yao-Wen Chang:
A New Asynchronous Pipeline Template for Power and Performance Optimization. 204:1-204:6 - Chen-Hsuan Lin, Lu Wan, Deming Chen:
C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs. 205:1-205:6 - Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saedi, Yang Du, Sung Kyu Lim:
Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs. 206:1-206:6 - Andrea Höller, Norbert Druml, Christian Kreiner, Christian Steger, Tomaz Felicijan:
Hardware/Software Co-Design of Elliptic-Curve Cryptography for Resource-Constrained Applications. 207:1-207:6 - James B. Wendt, Farinaz Koushanfar, Miodrag Potkonjak:
Techniques for Foundry Identification. 208:1-208:6 - Hassan Eldib, Chao Wang, Mostafa M. I. Taha, Patrick Schaumont:
QMS: Evaluating the Side-Channel Resistance of Masked Software from Source Code. 209:1-209:6 - Giovanni Agosta, Alessandro Barenghi, Gerardo Pelosi, Michele Scandale:
A Multiple Equivalent Execution Trace Approach to Secure Cryptographic Embedded Software. 210:1-210:6 - Kekai Hu, Tilman Wolf, Thiago Teixeira, Russell Tessier:
System-Level Security for Network Processors with Hardware Monitors. 211:1-211:6 - Parthasarathy M. B. Rao, Mojtaba Ebrahimi, Razi Seyyedi, Mehdi Baradaran Tahoori:
Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes. 212:1-212:6 - Rob A. Rutenbar:
The First EDA MOOC: Teaching Design Automation to Planet Earth. 213:1-213:6
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