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2020 – today
- 2021
[c14]M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng
:
Cross-Boundary Inductive Timing Optimization for 2.5D Chiplet-Package Co-Design. ACM Great Lakes Symposium on VLSI 2021: 135-140- 2020
- [c13]M. D. Arafat Kabir, Dusan Petranovic, Yarui Peng:
Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-Design. ICCAD 2020: 3:1-3:8 - [c12]Lingjun Zhu, Kyungwook Chang, Dusan Petranovic, Saurabh Sinha, Yun Seop Yu, Sung Kyu Lim:
Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs. ISPD 2020: 39-46
2010 – 2019
- 2015
- [j5]Yarui Peng, Dusan Petranovic, Sung Kyu Lim:
Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 1964-1976 (2015) - [c11]Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim:
Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs. ICCAD 2015: 649-655 - 2014
- [j4]Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim:
Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1900-1913 (2014) - [c10]Yarui Peng, Dusan Petranovic, Sung Kyu Lim:
Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling. DAC 2014: 28:1-28:6 - [c9]Nur Kurt-Karsilayan, Jim Falbo, Dusan Petranovic:
Efficient and accurate RIE modeling methodology for BEOL 2.5D parasitic extraction. MWSCAS 2014: 519-522 - 2013
- [c8]Yarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim:
On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs. ICCAD 2013: 281-288 - 2011
- [j3]Ahmed Shebaita, Debasish Das, Dusan Petranovic, Yehea I. Ismail:
A Novel Moment Based Framework for Accurate and Efficient Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1258-1262 (2011)
2000 – 2009
- 2009
- [j2]Youngmin Kim, Dusan Petranovic, Dennis Sylvester:
Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1166-1170 (2009) - [c7]Matthew Hogan, Dusan Petranovic:
Robust verification of 3D-ICs: Pros, cons and recommendations. 3DIC 2009: 1-6 - 2007
- [c6]Youngmin Kim, Dusan Petranovic, Dennis Sylvester:
Simple and Accurate Models for Capacitance Increment due to Metal Fill Insertion. ASP-DAC 2007: 456-461 - [c5]Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail:
Including inductance in static timing analysis. ICCAD 2007: 686-691 - 2006
- [c4]Ahmed Shebaita, Dusan Petranovic, Yehea I. Ismail:
Importance of volume discretization of single and coupled interconnects. ICCAD 2006: 119-126 - 2004
- [c3]Sunil Yu, Dusan Petranovic, Shoba Krishnan, Kwyro Lee, Cary Y. Yang:
Resistance Matrix in Crosstalk Modeling for Muliconductor Systems. ISQED 2004: 122-125 - 2003
- [c2]Yannick L. Le Coz, Dhivya Krishna, Dusan M. Petranovic, William M. Loh, Peter Bendix:
A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines. ICCAD 2003: 665-671 - 2001
- [c1]Seapahn Meguerdichian, Farinaz Koushanfar, Advait M. Mogre, Dusan Petranovic, Miodrag Potkonjak:
MetaCores: Design and Optimization Techniques. DAC 2001: 585-590
1990 – 1999
- 1998
- [j1]Veselin N. Ivanovic, Ljubisa Stankovic, Dusan Petranovic:
Finite word-length effects in implementation of distributions for time-frequency signal analysis. IEEE Trans. Signal Process. 46(7): 2035-2040 (1998)
Coauthor Index
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