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ORCIDDaniel Thiele
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2020 – today
- 2022
[b1]Daniel Thiele:
Formal Timing Analysis of Ethernet TSN Extensions for Automotive Applications (Formale Timing Analyse von Ethernet TSN Erweiterungen für automobile Anwendungen). Braunschweig University of Technology, Germany, 2022
2010 – 2019
- 2017
- [j2]Henning Sahlbach, Daniel Thiele, Rolf Ernst:
A system-level FPGA design methodology for video applications with weakly-programmable hardware components. J. Real Time Image Process. 13(2): 291-309 (2017) - [p1]Haibo Zeng, Prachi Joshi, Daniel Thiele, Jonas Diemer, Philip Axer, Rolf Ernst, Petru Eles:
Networked Real-Time Embedded Systems. Handbook of Hardware/Software Codesign 2017: 753-792 - 2016
- [j1]Daniel Thiele, Johannes Schlatow
, Philip Axer, Rolf Ernst:
Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networks. Real Time Syst. 52(1): 88-112 (2016) - [c12]Mischa Möstl, Daniel Thiele, Rolf Ernst:
Invited - Towards fail-operational ethernet based in-vehicle networks. DAC 2016: 53:1-53:6 - [c11]Daniel Thiele, Rolf Ernst:
Formal analysis based evaluation of software defined networking for time-sensitive Ethernet. DATE 2016: 31-36 - [c10]Daniel Thiele, Rolf Ernst:
Formal worst-case timing analysis of Ethernet TSN's burst-limiting shaper. DATE 2016: 187-192 - [c9]Daniel Thiele, Rolf Ernst:
Formal worst-case performance analysis of time-sensitive Ethernet with frame preemption. ETFA 2016: 1-9 - 2015
- [c8]Daniel Thiele, Philip Axer, Rolf Ernst:
Improving formal timing analysis of switched ethernet by exploiting FIFO scheduling. DAC 2015: 41:1-41:6 - [c7]Daniel Thiele, Rolf Ernst, Jonas Diemer:
Formal worst-case timing analysis of Ethernet TSN's time-aware and peristaltic shapers. VNC 2015: 251-258 - 2014
- [c6]Daniel Thiele, Philip Axer, Rolf Ernst, Jan R. Seyler:
Improving formal timing analysis of switched ethernet by exploiting traffic stream correlations. CODES+ISSS 2014: 15:1-15:10 - [c5]Philip Axer, Daniel Thiele, Rolf Ernst, Jonas Diemer:
Exploiting Shaper Context to Improve Performance Bounds of Ethernet AVB Networks. DAC 2014: 18:1-18:6 - [c4]Philip Axer, Daniel Thiele, Rolf Ernst:
Formal timing analysis of automatic repeat request for switched real-time networks. SIES 2014: 78-87 - 2013
- [c3]Daniel Thiele, Jonas Diemer, Philip Axer, Rolf Ernst, Jan R. Seyler:
Improved formal worst-case timing analysis of weighted round robin scheduling for Ethernet. CODES+ISSS 2013: 25:1-25:10 - 2012
- [c2]Daniel Thiele, Rolf Ernst:
Optimizing performance analysis for synchronous dataflow graphs with shared resources. DATE 2012: 635-640 - [c1]Jonas Diemer, Daniel Thiele, Rolf Ernst:
Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching. SIES 2012: 1-10
Coauthor Index
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