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ORCIDIvan Miro Panades
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- affiliation: University Grenoble Alpes, CEA, Grenoble, France
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2020 – today
- 2023
[j10]Ivan Miro-Panades, Benoît Tain
, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Guillaume Waltener, Emmanuel Pluchart, Jean-Philippe Noel, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Yvain Thonnart, Alexandre Valentian, Frédéric Heitzmann, Fabien Clermidy:
SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration. IEEE J. Solid State Circuits 58(6): 1782-1797 (2023)- [i2]Ivan Miro-Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Guillaume Waltener, Emmanuel Pluchart, Jean-Philippe Noel, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Yvain Thonnart, Alexandre Valentian, Frédéric Heitzmann, Fabien Clermidy:
SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration. CoRR abs/2304.13726 (2023) - 2021
- [j9]Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. IEEE J. Solid State Circuits 56(1): 79-97 (2021) - [j8]Davide Pala, Ivan Miro-Panades, Olivier Sentieys:
Freezer: A Specialized NVM Backup Controller for Intermittently Powered Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1559-1572 (2021) - [i1]Davide Pala, Ivan Miro-Panades, Olivier Sentieys:
Freezer: A Specialized NVM Backup Controller for Intermittently-Powered Systems. CoRR abs/2101.09968 (2021) - 2020
- [c26]Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. ISSCC 2020: 46-48 - [c25]Ivan Miro Panades, Benoît Tain, Jean-Frédéric Christmann, David Coriat, Romain Lemaire, Clement Jany, Baudouin Martineau, Fabrice Chaix, Anthony Quelen, Emmanuel Pluchart, Jean-Philippe Noel, Reda Boumchedda, Adam Makosiej, Maxime Montoya, Simone Bacles-Min, David Briand, Jean-Marc Philippe, Alexandre Valentian, Frédéric Heitzmann, Edith Beigné, Fabien Clermidy:
SamurAI: A 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15, 000× Peak-to-Idle Power Reduction, 207ns Wake-Up Time and 1.3TOPS/W ML Efficiency. VLSI Circuits 2020: 1-2
2010 – 2019
- 2018
- [c24]Anthony Quelen, Guilherme Migliato Marega, Sylvain Bouquet, Ivan Miro Panades, Gaël Pillonnet:
LDO-Assisted Voltage Selector Over 0.5-to-1V VDD Range for Fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition. ESSCIRC 2018: 202-205 - [c23]Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet:
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. ESSCIRC 2018: 318-321 - [c22]Mickael Maman, Dominique Morche, Baudouin Martineau, Clement Jany, Ivan Miro Panades, Anthony Quelen, Franck Badets, Edith Beigné:
Benefits of Joint Optimization of Tunable Wake-up Radio Architecture and Protocols. ICECS 2018: 789-792 - 2017
- [j7]Pascal Vivet, Yvain Thonnart, Romain Lemaire, Cristiano Santos, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Denis Dutoit, Fabien Clermidy, Séverine Cheramy, Abbas Sheibanyrad, Frédéric Pétrot, Eric Flamand, Jean Michailos, Alexandre Arriordaz, Lee Wang, Juergen Schloeffel:
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. IEEE J. Solid State Circuits 52(1): 33-49 (2017) - [j6]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini:
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro 37(5): 20-31 (2017) - [j5]Anuj Grover, G. S. Visweswaran, Chittoor R. Parthasarathy, Mohammad Daud, David Turgis, Bastien Giraud, Jean-Philippe Noel, Ivan Miro Panades, Guillaume Moritz, Edith Beigné, Philippe Flatresse, Promod Kumar, Shamsi Azmi:
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2438-2447 (2017) - [c21]Ivan Miro Panades, Edith Beigné, Olivier Billoint, Yvain Thonnart:
In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization. IOLTS 2017: 96-99 - 2016
- [c20]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini:
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips 2016: 1-3 - [c19]Pascal Vivet, Yvain Thonnart, Romain Lemaire, Edith Beigné, Christian Bernard, Florian Darve, Didier Lattard, Ivan Miro Panades, Cristiano Santos, Fabien Clermidy, Séverine Cheramy, Frédéric Pétrot, Eric Flamand, Jean Michailos:
8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. ISSCC 2016: 146-147 - 2015
- [j4]Edith Beigné, Alexandre Valentian, Ivan Miro Panades, Robin Wilson, Philippe Flatresse, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Jean-Philippe Noel, Olivier Thomas, Yvain Thonnart:
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. IEEE J. Solid State Circuits 50(1): 125-136 (2015) - [c18]Pascal Vivet, Christian Bernard, Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Gaël Pillonnet, Yvain Thonnart, Arnaud Garnier, Didier Lattard, Amandine Jouve, Franck Bana, Thierry Mourier, Séverine Cheramy:
3D advanced integration technology for heterogeneous systems. 3DIC 2015: FS6.1-FS6.3 - [c17]Edith Beigné, Fabien Clermidy, Didier Lattard, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet:
Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes. ISCAS 2015: 1550-1553 - [c16]Pascal Vivet, Christian Bernard, Eric Guthmuller, Ivan Miro Panades, Yvain Thonnart, Fabien Clermidy:
Interconnect Challenges for 3D Multi-cores: From 3D Network-on-Chip to Cache Interconnects. ISVLSI 2015: 615-620 - [c15]Robert Polster, Jose-Luis Gonzalez Jimenez, Ivan Miro Panades, Eric Cassan:
An optical clock receiver based on an injection locked ring oscillator featuring auto-calibration. MWSCAS 2015: 1-4 - 2014
- [j3]Ivan Miro Panades, Edith Beigné, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Anca Molnos, Farhat Thabet, Benoît Tain, Karim Ben Chehida, Sylvain Engels, Robin Wilson, Didier Fuin:
A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. IEEE J. Solid State Circuits 49(7): 1475-1486 (2014) - [c14]Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Ivan Miro Panades, Pascal Benoit, Lionel Torres:
Power management through DVFS and dynamic body biasing in FD-SOI circuits. DAC 2014: 183:1-183:6 - [c13]Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Alexandre Valentian, Suresh Pajaniradja, Lirida Alves de Barros Naviner, Valentin Gherman:
Shadow-scan design with low latency overhead and in-situ slack-time monitoring. ETS 2014: 1-6 - [c12]Sébastien Sarrazin, Samuel Evain, Ivan Miro Panades, Lirida Alves de Barros Naviner, Valentin Gherman:
Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths. IOLTS 2014: 160-163 - [c11]Robin Wilson, Edith Beigné, Philippe Flatresse, Alexandre Valentian, Fady Abouzeid, Thomas Benoist, Christian Bernard, Sebastien Bernard, Olivier Billoint, Sylvain Clerc, Bastien Giraud, Anuj Grover, Julien Le Coz, Ivan Miro Panades, Jean-Philippe Noël, Bertrand Pelloux-Prayer, Philippe Roche, Olivier Thomas, Yvain Thonnart, David Turgis, Fabien Clermidy, Philippe Magarshack:
27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. ISSCC 2014: 452-453 - 2013
- [c10]Denis Dutoit, Eric Guthmuller, Ivan Miro Panades:
3D integration for power-efficient computing. DATE 2013: 779-784 - [c9]Edith Beigné, Ivan Miro-Panades, Yvain Thonnart, Laurent Alacoque, Pascal Vivet, Suzanne Lesecq, Diego Puschini, Farhat Thabet, Benoît Tain, K. Benchehida, Sylvain Engels, Robin Wilson, Didier Fuin:
A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. ESSCIRC 2013: 57-60 - [c8]Fabien Clermidy, Denis Dutoit, Eric Guthmuller, Ivan Miro Panades, Pascal Vivet:
3D stacking for multi-core architectures: From WIDEIO to distributed caches. ISCAS 2013: 537-540 - [c7]Eric Guthmuller, Ivan Miro Panades, Alain Greiner:
Architectural exploration of a fine-grained 3D cache for high performance in a manycore context. VLSI-SoC 2013: 302-307 - 2012
- [c6]Eric Guthmuller, Ivan Miro Panades, Alain Greiner:
Adaptive Stackable 3D Cache Architecture for Manycores. ISVLSI 2012: 39-44 - 2011
- [j2]Carolina Albea, Diego Puschini, Pascal Vivet, Ivan Miro Panades, Edith Beigné, Suzanne Lesecq:
Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures. J. Low Power Electron. 7(3): 328-340 (2011) - 2010
- [c5]Fabien Clermidy, Christian Bernard, Romain Lemaire, Jérôme Martin, Ivan Miro Panades, Yvain Thonnart, Pascal Vivet, Norbert Wehn:
A 477mW NoC-based digital baseband for MIMO 4G SDR. ISSCC 2010: 278-279
2000 – 2009
- 2008
- [j1]Abbas Sheibanyrad, Alain Greiner, Ivan Miro Panades:
Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. IEEE Des. Test Comput. 25(6): 572-580 (2008) - [c4]Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner:
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture. NOCS 2008: 139-148 - 2007
- [c3]Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner:
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture. DATE 2007: 1090-1095 - [c2]Ivan Miro Panades, Alain Greiner:
Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures. NOCS 2007: 83-94 - 2006
- [c1]Ivan Miro Panades, Alain Greiner, Abbas Sheibanyrad:
A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach. Nano-Net 2006: 1-5
Coauthor Index
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