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Frank Kagan Gürkaynak
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2020 – today
- 2025
[i23]Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. CoRR abs/2501.07330 (2025)- 2024
- [c55]Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang
, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. VLSI Technology and Circuits 2024: 1-2 - [i22]Philippe Sauter, Thomas Benz, Paul Scheffler, Zerun Jiang, Beat Muheim, Frank K. Gürkaynak, Luca Benini:
Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC. CoRR abs/2405.03523 (2024) - [i21]Philippe Sauter, Thomas Benz, Paul Scheffler, Frank K. Gürkaynak, Luca Benini:
Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design? CoRR abs/2405.04257 (2024) - [i20]Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. CoRR abs/2406.15068 (2024) - [i19]Paul Scheffler, Philippe Sauter, Thomas Benz, Frank K. Gürkaynak, Luca Benini:
Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS. CoRR abs/2406.15107 (2024) - [i18]Michael Rogenmoser, Philip Wiese, Bruno E. Forlin, Frank K. Gürkaynak, Paolo Rech, Alessandra Menicucci, Marco Ottavi, Luca Benini:
Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC. CoRR abs/2407.05938 (2024) - [i17]Tim Fischer, Michael Rogenmoser, Thomas Benz, Frank K. Gürkaynak, Luca Benini:
FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support. CoRR abs/2409.17606 (2024) - 2023
- [j15]Tim Fischer, Michael Rogenmoser, Matheus A. Cavalcante, Frank K. Gürkaynak, Luca Benini:
FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic. IEEE Des. Test 40(6): 7-17 (2023) - [j14]Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Gernot Heiser, Luca Benini:
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning. IEEE Trans. Computers 72(5): 1420-1430 (2023) - [c54]Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal:
PetaOps/W edge-AI $\mu$ Processors: Myth or reality? DATE 2023: 1-6 - [c53]MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David:
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. ISCAS 2023: 1-5 - [i16]MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David:
Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference. CoRR abs/2302.05996 (2023) - [i15]Tim Fischer, Michael Rogenmoser, Matheus A. Cavalcante, Frank K. Gürkaynak, Luca Benini:
FlooNoC: A Multi-Tbps Wide NoC for Heterogeneous AXI4 Traffic. CoRR abs/2305.08562 (2023) - 2022
- [c52]Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini:
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. ISVLSI 2022: 44-49 - [c51]Michael Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank K. Gürkaynak, Luca Benini:
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster. ISVLSI 2022: 398-401 - [i14]Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Gernot Heiser, Luca Benini:
Systematic Prevention of On-Core Timing Channels by Full Temporal Partitioning. CoRR abs/2202.12029 (2022) - [i13]Michael Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank K. Gürkaynak, Luca Benini:
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster. CoRR abs/2205.12580 (2022) - [i12]Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini:
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. CoRR abs/2209.00889 (2022) - [i11]Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Frank K. Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, S. Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal:
CONVOLVE: Smart and seamless design of smart edge processors. CoRR abs/2212.00873 (2022) - 2021
- [j13]Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini:
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 677-690 (2021) - [c50]Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser:
Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core. DATE 2021: 627-632 - [c49]Thomas Benz, Luca Bertaccini, Florian Zaruba, Fabian Schuiki, Frank K. Gürkaynak, Luca Benini:
A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range. ESSCIRC 2021: 263-266 - [c48]Jaume Abella, Sergi Alcaide, Jens Anders, Francisco Bas, Steffen Becker, Elke De Mulder, Nourhan Elhamawy, Frank K. Gürkaynak, Helena Handschuh, Carles Hernández, Michael Hutter, Leonidas Kosmidis, Ilia Polian, Matthias Sauer, Stefan Wagner, Francesco Regazzoni:
Security, Reliability and Test Aspects of the RISC-V Ecosystem. ETS 2021: 1-10 - 2020
- [c47]Dionysios Diamantopoulos, Florian Scheidegger, Stefan Mach, Fabian Schuiki, Germain Haugou, Michael Schaffner, Frank K. Gürkaynak, Christoph Hagleitner, A. Cristiano I. Malossi, Luca Benini:
XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs. COOL CHIPS 2020: 1-3 - [c46]Aizea Lojo, Leire Rubio, Jesus Miguel Ruano, Tania Di Mascio, Luigi Pomante, Enrico Ferrari, Ignacio Garcìa Vega, Frank K. Gürkaynak, Mikel Labayen Esnaola, Vanessa Orani, Jaume Abella:
The ECSEL FRACTAL Project: A Cognitive Fractal and Secure edge based on a unique Open-Safe-Reliable-Low Power Hardware Platform. DSD 2020: 393-400 - [i10]Nils Wistoff, Moritz Schneider, Frank K. Gürkaynak, Luca Benini, Gernot Heiser:
Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core. CoRR abs/2005.02193 (2020) - [i9]Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini:
Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes. CoRR abs/2006.14256 (2020)
2010 – 2019
- 2019
- [j12]Fabian Schuiki, Michael Schaffner, Frank K. Gürkaynak, Luca Benini:
A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets. IEEE Trans. Computers 68(4): 484-497 (2019) - 2018
- [c45]Robert Schilling, Thomas Unterluggauer, Stefan Mangard, Frank K. Gürkaynak, Michael Muehlberghuber, Luca Benini:
High speed ASIC implementations of leakage-resilient cryptography. DATE 2018: 1259-1264 - [c44]Florian Glaser, Stefan Mach, Abbas Rahimi, Frank K. Gürkaynak, Qiuting Huang, Luca Benini:
An 826 MOPS, 210uW/MHz Unum ALU in 65 nm. ISCAS 2018: 1-5 - [i8]Fabian Schuiki, Michael Schaffner, Frank K. Gürkaynak, Luca Benini:
A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets. CoRR abs/1803.04783 (2018) - 2017
- [j11]Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini:
An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster. IEEE J. Solid State Circuits 52(1): 98-112 (2017) - [j10]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini:
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro 37(5): 20-31 (2017) - [j9]Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini:
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2481-2494 (2017) - [j8]Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini:
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2700-2713 (2017) - [c43]Thomas Unterluggauer, Thomas Korak, Stefan Mangard, Robert Schilling, Luca Benini, Frank K. Gürkaynak, Michael Muehlberghuber:
Leakage Bounds for Gaussian Side Channels. CARDIS 2017: 88-104 - [c42]Frank K. Gürkaynak, Robert Schilling, Michael Muehlberghuber, Francesco Conti, Stefan Mangard, Luca Benini:
Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS. CS2@HiPEAC 2017: 19-24 - [i7]Florian Glaser, Stefan Mach, Abbas Rahimi, Frank K. Gürkaynak, Qiuting Huang, Luca Benini:
An 826 MOPS, 210 uW/MHz Unum ALU in 65 nm. CoRR abs/1712.01021 (2017) - [i6]Thomas Unterluggauer, Thomas Korak, Stefan Mangard, Robert Schilling, Luca Benini, Frank K. Gürkaynak, Michael Muehlberghuber:
Leakage Bounds for Gaussian Side Channels. IACR Cryptol. ePrint Arch. 2017: 992 (2017) - 2016
- [j7]Michael Schaffner, Frank K. Gürkaynak, Pierre Greisen, Hubert Kaeslin, Luca Benini, Aljosa Smolic:
Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW. IEEE Trans. Circuits Syst. Video Technol. 26(11): 2093-2108 (2016) - [c41]Michael Schaffner, Michael Gautschi, Frank K. Gürkaynak, Luca Benini:
Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters. ARITH 2016: 95-103 - [c40]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini:
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips 2016: 1-3 - [c39]Youri Popoff, Florian Scheidegger, Michael Schaffner, Michael Gautschi, Frank K. Gürkaynak, Luca Benini:
High-efficiency logarithmic number unit design based on an improved cotransformation scheme. DATE 2016: 1387-1392 - [c38]Vincent Camus, Jeremy Schlachter, Christian C. Enz, Michael Gautschi, Frank K. Gürkaynak:
Approximate 32-bit floating-point unit design with 53% power-area product reduction. ESSCIRC 2016: 465-468 - [c37]Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini:
4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster. ISSCC 2016: 82-83 - [i5]Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini:
A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices. CoRR abs/1608.08376 (2016) - [i4]Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini:
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. CoRR abs/1612.05974 (2016) - 2015
- [c36]Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Luca Benini:
DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS. DATE 2015: 707-712 - [c35]Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic:
Automatic multiview synthesis - Towards a mobile system on a chip. VCIP 2015: 1-4 - [c34]Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic:
Automatic multiview synthesis - Prototype demo. VCIP 2015: 1 - 2014
- [c33]Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini:
An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing. DAC 2014: 132:1-132:6 - [c32]Christoph Keller, Frank K. Gürkaynak, Hubert Kaeslin, Norbert Felber:
Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers. ISCAS 2014: 2740-2743 - 2013
- [c31]Michael Schaffner, Pierre Greisen, Simon Heinzle, Frank K. Gürkaynak, Hubert Kaeslin, Aljoscha Smolic:
MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping. ESSCIRC 2013: 61-64 - [c30]Michael Muehlberghuber, Frank K. Gürkaynak, Thomas Korak, Philipp Dunst, Michael Hutter:
Red team vs. blue team hardware trojan analysis: detection of a hardware trojan on an actual ASIC. HASP@ISCA 2013: 1 - [c29]Michael Schaffner, Pascal Hager, Lukas Cavigelli, Pierre Greisen, Frank K. Gürkaynak, Hubert Kaeslin:
A real-time 720p feature extraction core based on Semantic Kernels Binarized. VLSI-SoC 2013: 27-32 - [c28]Michael Schaffner, Pascal A. Hager, Lukas Cavigelli, Z. Fang, Pierre Greisen, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini:
A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized. VLSI-SoC (Selected Papers) 2013: 144-167 - 2012
- [c27]Jeremy Constantin, Andreas Burg, Frank K. Gürkaynak:
Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture. ASAP 2012: 117-124 - [c26]Michael Muehlberghuber, Christoph Keller, Frank K. Gürkaynak, Norbert Felber:
FPGA-Based High-Speed Authenticated Encryption System. VLSI-SoC (Selected Papers) 2012: 1-20 - [c25]Pierre Greisen, Michael Schaffner, Danny Luu, Val Mikos, Simon Heinzle, Frank K. Gürkaynak, Aljoscha Smolic:
Spatially-Varying Image Warping: Evaluations and VLSI Implementations. VLSI-SoC (Selected Papers) 2012: 64-87 - [c24]Pierre Greisen, Richard Emler, Michael Schaffner, Simon Heinzle, Frank K. Gürkaynak:
A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS. VLSI-SoC 2012: 105-110 - [i3]Jeremy Constantin, Andreas Burg, Frank K. Gürkaynak:
Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture. IACR Cryptol. ePrint Arch. 2012: 50 (2012) - 2010
- [j6]Deniz Karakoyunlu, Frank Kagan Gürkaynak, Berk Sunar, Yusuf Leblebici:
Efficient and side-channel-aware implementations of elliptic curve cryptosystems over prime fields. IET Inf. Secur. 4(1): 30-43 (2010) - [c23]Luca Henzen, Pietro Gendotti, Patrice Guillet, Enrico Pargaetzi, Martin Zoller, Frank K. Gürkaynak:
Developing a Hardware Evaluation Method for SHA-3 Candidates. CHES 2010: 248-263
2000 – 2009
- 2009
- [j5]Omer Can Akgun, Frank K. Gürkaynak, Yusuf Leblebici:
A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime. Int. J. Circuit Theory Appl. 37(2): 203-220 (2009) - [j4]Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne:
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Trans. Comput. Sci. 4: 230-243 (2009) - [j3]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 13:1-13:36 (2009) - [c22]Milos Krstic, Xin Fan, Eckhard Grass, Frank K. Gürkaynak:
GALS for Bursty Data Transfer based on Clock Coupling. FMGALS@DATE 2009: 103-113 - [i2]Daniel V. Bailey, Brian Baldwin, Lejla Batina, Daniel J. Bernstein, Peter Birkner, Joppe W. Bos, Gauthier Van Damme, Giacomo de Meulenaer, Junfeng Fan, Tim Güneysu, Frank K. Gürkaynak, Thorsten Kleinjung, Tanja Lange, Nele Mentens, Christof Paar, Francesco Regazzoni, Peter Schwabe, Leif Uhsadel:
The Certicom Challenges ECC2-X. IACR Cryptol. ePrint Arch. 2009: 466 (2009) - [i1]Daniel V. Bailey, Lejla Batina, Daniel J. Bernstein, Peter Birkner, Joppe W. Bos, Hsieh-Chung Chen, Chen-Mou Cheng, Gauthier Van Damme, Giacomo de Meulenaer, Luis J. Dominguez Perez, Junfeng Fan, Tim Güneysu, Frank K. Gürkaynak, Thorsten Kleinjung, Tanja Lange, Nele Mentens, Ruben Niederhagen, Christof Paar, Francesco Regazzoni, Peter Schwabe, Leif Uhsadel, Anthony Van Herrewege, Bo-Yin Yang:
Breaking ECC2K-130. IACR Cryptol. ePrint Arch. 2009: 541 (2009) - 2008
- [c21]Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Design space exploration for field programmable compressor trees. CASES 2008: 207-216 - [c20]Stéphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Gürkaynak, Yusuf Leblebici:
A Generic Standard Cell Design Methodology for Differential Circuit Styles. DATE 2008: 843-848 - [c19]Carlotta Guiducci, Alexandre Schmid, Frank K. Gürkaynak, Yusuf Leblebici:
Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. DATE 2008: 1328-1333 - [c18]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190 - [c17]Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer:
Improving the power-delay product in SCL circuits using source follower output stage. ISCAS 2008: 145-148 - 2007
- [j2]Milos Krstic, Eckhard Grass, Frank K. Gürkaynak, Pascal Vivet:
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook. IEEE Des. Test Comput. 24(5): 430-441 (2007) - [c16]Milos Stanisavljevic, Frank K. Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani:
Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density. ACM Great Lakes Symposium on VLSI 2007: 204-207 - [c15]Milos Stanisavljevic, Frank Kagan Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani:
A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density. Nano-Net 2007: 4 - 2006
- [b1]Frank Kagan Gürkaynak:
GALS system design: side channel attack secure cryptographic accelerators. ETH Zurich, 2006, ISBN 3-86628-065-3, pp. 1-165 - [c14]Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
GALS at ETH Zurich: Success or Failure. ASYNC 2006: 150-159 - 2005
- [c13]Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Improving DPA security by using globally-asynchronous locally-synchronous systems. ESSCIRC 2005: 407-410 - [c12]Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. FMGALS@MEMOCODE 2005: 133-149 - 2004
- [c11]Norbert Pramstaller, Frank K. Gürkaynak, Simon Haene, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Towards an AES crypto-chip resistant to differential power analysis. ESSCIRC 2004: 307-310 - [c10]Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, Franco Hug, Hubert Kaeslin:
A 2 Gb/s balanced AES crypto-chip implementation. ACM Great Lakes Symposium on VLSI 2004: 39-44 - [c9]Siddika Berna Örs, Frank K. Gürkaynak, Elisabeth Oswald, Bart Preneel:
Power-Analysis Attack on an ASIC AES implementation. ITCC (2) 2004: 546-552 - 2003
- [c8]Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner:
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. ASYNC 2003: 141-150 - [c7]Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner:
Variable delay ripple carry adder with carry chain interrupt detection. ISCAS (5) 2003: 113-116 - 2002
- [c6]Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. ASYNC 2002: 181-189 - [c5]Adrian K. Lutz, Jürg Treichler, Frank K. Gürkaynak, Hubert Kaeslin, Gérard Basler, Antonia Erni, Stephan Reichmuth, Pieter Rommens, Stephan Oetiker, Wolfgang Fichtner:
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. CHES 2002: 144-158 - 2000
- [j1]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic. VLSI Design 11(2): 115-128 (2000) - [c4]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
A compact modular architecture for high-speed binary sorting. ICASSP 2000: 3339-3342 - [c3]Frank K. Gürkaynak, Yusuf Leblebici, Laurent Chaouat, Patrik J. McGuinness:
Higher radix Kogge-Stone parallel prefix adder architectures. ISCAS 2000: 609-612 - [c2]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering. ISCAS 2000: 685-688
1990 – 1999
- 1999
- [c1]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. ISCAS (1) 1999: 435-438
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Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
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Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
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Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
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Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
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OpenAlex data
Load additional information about publications from 
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last updated on 2025-03-04 22:23 CET by the dblp team
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