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ORCIDIlhan Hatirnaz
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2000 – 2009
- 2007
[c9]Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza
, Giovanni De Micheli:
Early wire characterization for predictable network-on-chip global interconnects. SLIP 2007: 57-64- 2006
- [c8]Elizabeth J. Brauer, Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici:
Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. ISCAS 2006 - [c7]Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer:
Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. VLSI-SoC 2006: 234-238 - 2004
- [c6]Ilhan Hatirnaz, Yusuf Leblebici:
Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction. ISCAS (5) 2004: 185-188 - 2003
- [c5]Turan Demirci, Ilhan Hatirnaz, Yusuf Leblebici:
Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity. ISCAS (5) 2003: 453-456 - [c4]Ilhan Hatirnaz, Yusuf Leblebici:
Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation. SoC 2003: 93-96 - 2000
- [j1]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic. VLSI Design 11(2): 115-128 (2000) - [c3]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
A compact modular architecture for high-speed binary sorting. ICASSP 2000: 3339-3342 - [c2]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering. ISCAS 2000: 685-688
1990 – 1999
- 1999
- [c1]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. ISCAS (1) 1999: 435-438
Coauthor Index
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