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ORCID2nd FMGALS@MEMOCODE 2005: Verona, Italy
- Montek Singh, Jean-Pierre Talpin:
Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, FMGALS@MEMOCODE 2005, Verona, Italy, July 15, 2005. Electronic Notes in Theoretical Computer Science 146(2), Elsevier 2006 - Ken S. Stevens, Sandeep K. Shukla
, Montek Singh, Jean-Pierre Talpin:
Preface. 1-3 - Ankur Agiwal, Montek Singh:
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis. 5-28 - David S. Bormann:
GALS Test Chip on 130nm Process. 29-40 - Julien Boucaron, Jean-Vivien Millo, Robert de Simone:
Another Glance at Relay Stations in Latency-Insensitive Design. 41-59 - Luca P. Carloni:
The Role of Back-Pressure in Implementing Latency-Insensitive Systems. 61-80 - Sohini Dasgupta, Dumitru Potop-Butucaru, Benoît Caillaud, Alexandre Yakovlev:
Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits. 81-103 - Frederic Doucet, Massimiliano Menarini, Ingolf H. Krüger, Rajesh K. Gupta, Jean-Pierre Talpin:
A Verification Approach for GALS Integration of Synchronous Components. 105-131 - Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. 133-149 - Julien Ouy:
A Survey of Desynchronization in a Polychronous Model of Computation. 151-167 - Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner, Jean-Pierre Talpin:
A Functional Programming Framework for Latency Insensitive Protocol Validation. 169-188 - Xu Wang, Marta Z. Kwiatkowska, Georgios Theodoropoulos, Qianyi Zhang:
Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs. 189-206
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