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ORCIDIEEE Transactions on Very Large Scale Integration Systems, Volume 29
Volume 29, Number 1, January 2021
- Massimo Alioto
:
Opening of the 2021 Editorial Year - Overture for a New Year of Change. 1-2 - Boris Murmann:
Mixed-Signal Computing for Deep Neural Network Inference. 3-13 - M. Imtiaz Rashid, Farah Ferdaus, Bashir M. Sabquat Bahar Talukder, Paul Henny, Aubrey N. Beal, Md. Tauhidur Rahman:
True Random Number Generation Using Latency Variations of FRAM. 14-23 - Nadesh Ramanathan, George A. Constantinides, John Wickerson:
Global Analysis of C Concurrency in High-Level Synthesis. 24-37 - Nadir Khan, Jorge Castro-Godínez, Shixiang Xue, Jörg Henkel, Jürgen Becker:
Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores. 38-50 - Ahmed Mahdi, Nikos Kanistras, Vassilis Paliouras:
A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees. 51-64 - Rahul Shrestha:
A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications. 65-75 - Nilanjan Mukherjee, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Time and Area Optimized Testing of Automotive ICs. 76-88 - Irith Pomeranz:
Partitioning Functional Test Sequences Into Multicycle Functional Broadside Tests. 89-99 - Gang Li, Pengjun Wang, Xuejiao Ma, Yijian Shi, Bo Chen, Yuejun Zhang:
A Multimode Configurable Physically Unclonable Function With Bit-Instability-Screening and Power-Gating Strategies. 100-111 - Anirban Sengupta, Mahendra Rathor:
Facial Biometric for Securing Hardware Accelerators. 112-123 - Tiancheng Yang, Ankit Mittal, Yunsi Fei, Aatmesh Shrivastava:
Large Delay Analog Trojans: A Silent Fabrication-Time Attack Exploiting Analog Modalities. 124-135 - Karim Shahbazi, Seok-Bum Ko:
Area-Efficient Nano-AES Implementation for Internet-of-Things Devices. 136-148 - Fengchao Zhang, Shubhra Deb Paul, Patanjali SLPSK, Amit Ranjan Trivedi, Swarup Bhunia:
On Database-Free Authentication of Microelectronic Components. 149-161 - Seongsik Park, Jaehee Jang, Sei Joon Kim, Byunggook Na, Sungroh Yoon:
Memory-Augmented Neural Networks on FPGA for Real-Time and Energy-Efficient Question Answering. 162-175 - Kun-Chih Chen, Ya-Wei Huang, Geng-Ming Liu, Jing-Wen Liang, Yueh-Chi Yang, Yuan-Hao Liao:
A Hierarchical K-Means-Assisted Scenario-Aware Reconfigurable Convolutional Neural Network. 176-188 - Qingkun Chen, Wenjin Huang, Yuanshan Zhang, Yihua Huang:
An IP Core Mapping Algorithm Based on Neural Networks. 189-202 - Vishnu Unnikrishnan, Okko Järvinen, Waqas Siddiqui, Kari Stadius, Marko Kosunen, Jussi Ryynänen:
Data Conversion With Subgate-Delay Time Resolution Using Cyclic-Coupled Ring Oscillators. 203-214 - Anirban Chakraborty, Ayan Banerjee:
CORDIC-Based High-Speed VLSI Architecture of Transform Model Estimation for Real-Time Imaging. 215-226 - Qihui Zhang, Ning Ning, Jing Li, Qi Yu, Kejun Wu, Zhong Zhang:
A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator. 227-231 - Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Reliable CRC-Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography. 232-236 - Sina Sayyah Ensan, Swaroop Ghosh:
ReLOPE: Resistive RAM-Based Linear First-Order Partial Differential Equation Solver. 237-241 - Irith Pomeranz:
Test Compaction by Backward and Forward Extension of Multicycle Tests. 242-246
Volume 29, Number 2, February 2021
- Seyfeddine Boukhtache, Benoît Blaysat, Michel Grédiac, François Berry:
Alternatives to Bicubic Interpolation Considering FPGA Hardware Resource Consumption. 247-258 - Jun Li, Paul Chow, Yuanxi Peng, Tian Jiang:
FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction. 259-272 - Karim Hammad, Zhongpan Wu, Ebrahim Ghafar-Zadeh, Sebastian Magierowski:
A Scalable Hardware Accelerator for Mobile DNA Sequencing. 273-286 - Chenbing Qu, Zhangming Zhu, Yunfei En, Liwei Wang, Xiaoxian Liu:
Area-Efficient Extended 3-D Inductor Based on TSV Technology for RF Applications. 287-296 - Atul Thakur, Shouri Chatterjee:
A 4.4-mA ESD-Safe 900-MHz LNA With 0.9-dB Noise Figure. 297-306 - Zhuojun Liang, Dongxu Lv, Chao Cui, Hai-Bao Chen, Weifeng He, Weiguang Sheng, Naifeng Jing, Zhigang Mao, Guanghui He:
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing. 307-320 - Tsutomu Yoshimura:
Study of Injection Pulling of Oscillators in Phase-Locked Loops. 321-332 - Jian Zhou, Sumit K. Mandal, Brendan L. West, Siyuan Wei, Ümit Y. Ogras, Oliver D. Kripfgans, J. Brian Fowlkes, Thomas F. Wenisch, Chaitali Chakrabarti:
Front-End Architecture Design for Low-Complexity 3-D Ultrasound Imaging Based on Synthetic Aperture Sequential Beamforming. 333-346 - Kai Wang, Fengkai Yuan, Lutan Zhao, Rui Hou, Zhenzhou Ji, Dan Meng:
Mitigating Cross-Core Cache Attacks via Suspicious Traffic Detection. 347-358 - Jing Tian, Jun Lin, Zhongfeng Wang:
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography. 359-371 - Riduan Khaddam-Aljameh, Pier Andrea Francese, Luca Benini, Evangelos Eleftheriou:
An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power. 372-385 - Gauthaman Murali, Xiaoyu Sun, Shimeng Yu, Sung Kyu Lim:
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM. 386-396 - Daehan Ji, Dongyeob Shin, Jongsun Park:
An Error Compensation Technique for Low-Voltage DNN Accelerators. 397-408 - Sanmitra Banerjee, Arjun Chaudhuri, August Ning, Krishnendu Chakrabarty:
Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits. 409-422 - Irith Pomeranz, Xijiang Lin:
Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults. 423-433 - Roohollah Yarmand, Mehdi Kamal, Ali Afzali-Kusha, Pooria Esmaeli, Massoud Pedram:
OPTIMA: An Approach for Online Management of Cache Approximation Levels in Approximate Processing Systems. 434-446
Volume 29, Number 3, March 2021
- Hasan Erdem Yantir, Ahmed M. Eltawil, Khaled N. Salama:
IMCA: An Efficient In-Memory Convolution Accelerator. 447-460 - Steven Colleman, Marian Verhelst:
High-Utilization, High-Flexibility Depth-First CNN Coprocessor for Image Pixel Processing on FPGA. 461-471 - Dawen Xu, Ziyang Zhu, Cheng Liu, Ying Wang, Shuang Zhao, Lei Zhang, Huaguo Liang, Huawei Li, Kwang-Ting Cheng:
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System. 472-484 - Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu:
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators. 485-498 - Taehwan Kim, Heechun Park, Taewhan Kim:
Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach. 499-511 - Isaak Yang, Kwang-Hyun Cho:
A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock. 512-518 - Yi-Wen Hung, Yung-Chih Chen, Chi Lo, Austin Go So, Shih-Chieh Chang:
Dynamic Workload Allocation for Edge Computing. 519-529 - Mengting Yan, Haoran Wei, Marvin Onabajo:
On-Chip Thermal Profiling to Detect Malicious Activity: System-Level Concepts and Design of Key Building Blocks. 530-543 - Chris Nigh, Alex Orailoglu:
AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction. 544-557 - Yuri Ardesi, Giovanna Turvani, Mariagrazia Graziano, Gianluca Piccinini:
SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing. 558-567 - Chenxi Zhao, Jiawei Guo, Huihua Liu, Yiming Yu, Yunqiu Wu, Kai Kang:
A 33-41-GHz SiGe-BiCMOS Digital Step Attenuator With Minimized Unit Impedance Variation. 568-579 - Charalampos Antoniadis, Nestor E. Evmorfopoulos, Georgios I. Stamoulis:
Graph-Based Sparsification and Synthesis of Dense Matrices in the Reduction of RLC Circuits. 580-590
Volume 29, Number 4, April 2021
- Andrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Bangqi Xu:
Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology. 591-604 - Gauthaman Murali, Heechun Park, Eric Qin, Hakki Mert Torun, Majid Ahadi Dolatsara, Madhavan Swaminathan, Tushar Krishna, Sung Kyu Lim:
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems. 605-616 - Hongbo Cao, Faqiang Wang:
Spreading Operation Frequency Ranges of Memristor Emulators via a New Sine-Based Method. 617-630 - Kwang Woo Lee, Hyun Kook Park, Seong-Ook Jung:
Adaptive Sensing Voltage Modulation Technique in Cross-Point OTS-PRAM. 631-642 - Kimia Zamiri Azar, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, Christos P. Sotiriou, Avesta Sasan:
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits. 643-656 - Paulo Realpe-Muñoz, Jaime Velasco-Medina, Guillermo Adolfo-David:
Design of an S-ECIES Cryptoprocessor Using Gaussian Normal Bases Over GF(2m). 657-666 - Moslem Heidarpur, Mitra Mirhassani:
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation. 667-676 - Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini:
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes. 677-690 - Saambhavi Baskaran, Jack Sampson:
Evaluation of Tradeoffs in the Design of FPGA Fabrics Using Electrostrictive 2-D FETs. 691-701 - Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique:
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators. 702-715 - Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique:
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators. 716-729 - Sourjya Roy, Shrihari Sridharan, Shubham Jain, Anand Raghunathan:
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems. 730-738 - Sanghun Lee, Kisang Jung, Hak Seong Kim, Huan Nguyen, Thinh Nguyen, Luan Nguyen, Cuong Huynh, Kunhee Cho, Jusung Kim:
Frequency-Locked RF Power Oscillator With 43-dBm Output Power and 58% Efficiency. 739-746 - Shahriar Shahabuddin, Ilkka Hautala, Markku J. Juntti, Christoph Studer:
ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture. 747-759 - Rohit B. Chaurasiya, Rahul Shrestha:
A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network. 760-773 - Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini:
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing. 774-787 - Yu-Hsuan Lee, Tzu-Chieh Chen, Hsuan-Chi Liang, Jian-Xiang Liao:
Algorithm and Architecture Design of FAST-C Image Corner Detection Engine. 788-799 - Mahmoud Masadeh, Osman Hasan, Sofiène Tahar:
Machine-Learning-Based Self-Tunable Design of Approximate Computing. 800-813
Volume 29, Number 5, May 2021
- Massimo Alioto:
Second Quarter of the 2021 Editorial Year - A Year in Crescendo. 815-842 - Sriram R. Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Saurabh Kumar, Ram Krishnamurthy, Harish Krishnamurthy, James W. Tschanz, Vivek De, Chris H. Kim:
Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. 843-856 - Rui Zhang, Kexin Yang, Zhaocheng Liu, Taizhi Liu, Wenshan Cai, Linda Milor:
A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory. 857-870 - Azad Mahmoudi, Pooya Torkzadeh, Massoud Dousti:
A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications. 871-882 - Ching-Yuan Yang, Miao-Shan Li, Ai-Jia Chuang:
A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links. 883-894 - Jian Liu, Shubin Liu, Ruixue Ding, Zhangming Zhu:
A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems. 895-903 - Hsun-Wei Chan, Wei-Che Lee, Kang-Lun Chiu, Chih-Wei Jen, Shyh-Jye Jou:
A Digital Two-Stage Phase Noise Compensation and rCFO/rSCO Tracking Module for mmW Single Carrier Systems. 904-915 - Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri:
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register. 916-924 - Nima Taherinejad:
SIXOR: Single-Cycle In-Memristor XOR. 925-935 - Di Wu, Xitian Fan, Wei Cao, Lingli Wang:
SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator. 936-949 - Fatima Hameed Khan, Wala Saadeh:
An EEG-Based Hypnotic State Monitor for Patients During General Anesthesia. 950-961 - Dimitrios Garyfallou, Stavros Simoglou, Nikolaos Sketopoulos, Charalampos Antoniadis, Christos P. Sotiriou, Nestor E. Evmorfopoulos, George I. Stamoulis:
Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance. 962-972 - Jai-Ming Lin, You-Lun Deng, Ya-Chu Yang, Jia-Jian Chen, Po-Chen Lu:
Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs. 973-984 - Jai-Ming Lin, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu:
Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation. 985-997 - Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo:
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops. 998-1008 - Biswajit Bhowmik:
Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks. 1009-1021 - Heng You, Jia Yuan, Zenghui Yu, Shushan Qiao:
Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation. 1022-1032 - Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh:
CRC-Based Error Detection Constructions for FLT and ITA Finite Field Inversions Over GF(2m). 1033-1037
Volume 29, Number 6, June 2021
- Kamlesh Singh, Barry de Bruin, Hailong Jiao, Jos Huisken, Henk Corporaal, José Pineda de Gyvez:
Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation. 1039-1051 - Yin Sun, Jongjoo Lee, Chulsoon Hwang:
A Generalized Power Supply Induced Jitter Model Based on Power Supply Rejection Ratio Response. 1052-1060 - Ruzica Jevtic, Marko Ylitolva, Clara Calonge, Martti Ojanen, Tero Säntti, Lauri Koskinen:
EM Side-Channel Countermeasure for Switched-Capacitor DC-DC Converters Based on Amplitude Modulation. 1061-1072 - Zhen Gao, Lingling Zhang, Yinghao Cheng, Kangkang Guo, Anees Ullah, Pedro Reviriego:
Design of FPGA-Implemented Reed-Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory. 1073-1082 - Dongyun Kam, Hoyoung Yoo, Youngjoo Lee:
Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism. 1083-1094 - Zhuojun Chen, Judi Zhang, Shuangchun Wen, Ya Li, Qinghui Hong:
Competitive Neural Network Circuit Based on Winner-Take-All Mechanism and Online Hebbian Learning Rule. 1095-1107 - John Reuben, Stefan Pechmann:
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates. 1108-1121 - Pablo Ilha Vaz, Patrick Girard, Arnaud Virazel, Hassen Aziza:
Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors. 1122-1131 - Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici:
A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI. 1132-1140 - Jérémy Nadal, Amer Baghdadi:
Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA. 1141-1151 - Lingjun Zhu, Lennart Bamberg, Sai Surya Kiran Pentapati, Kyungwook Chang, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Brian Cline, Saurabh Sinha, Xiaoqing Xu, Alberto García-Ortiz, Sung Kyu Lim:
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors. 1152-1163 - Jungil Mok, Hyeonchan Lim, Sungho Kang:
Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs. 1164-1177 - Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin, Dongwon Park:
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT. 1178-1191 - Suchang Kim, Seungho Na, Byeong Yong Kong, Jaewoong Choi, In-Cheol Park:
Real-Time SSDLite Object Detection on FPGA. 1192-1205 - Febin P. Sunny, Asif Mirza, Ishan G. Thakkar, Mahdi Nikdast, Sudeep Pasricha:
ARXON: A Framework for Approximate Communication Over Photonic Networks-on-Chip. 1206-1219 - Wenbo Guo, Shuguo Li:
Fast Binary Counters and Compressors Generated by Sorting Network. 1220-1230 - Tanfer Alan, Andreas Gerstlauer, Jörg Henkel:
Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy. 1231-1243 - I-Ju Wang, Yu-Pei Liang, Tseng-Yi Chen, Yuan-Hao Chang, Bo-Jun Chen, Hsin-Wen Wei, Wei-Kuan Shih:
Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range Query Over NVRAM. 1244-1256 - Jin-Tai Yan:
Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits. 1257-1270 - Guilherme Cardoso Medeiros, Moritz Fieback, Lizhou Wu, Mottaqiallah Taouil, Letícia Maria Bolzani Poehls, Said Hamdioui:
Hard-to-Detect Fault Analysis in FinFET SRAMs. 1271-1284
Volume 29, Number 7, July 2021
- Ivan Miketic, Emre Salman:
PhaseCamouflage: Leveraging Adiabatic Operation to Thwart Reverse Engineering. 1285-1296 - Mojtaba Bisheh-Niasar, Reza Azarderakhsh, Mehran Mozaffari Kermani:
Cryptographic Accelerators for Digital Signature Based on Ed25519. 1297-1305 - Christian Pilato, Animesh Basak Chowdhury, Donatella Sciuto, Siddharth Garg, Ramesh Karri:
ASSURE: RTL Locking Against an Untrusted Foundry. 1306-1318 - Esteban Garzón, Yosi Greenblatt, Odem Harel, Marco Lanuzza, Adam Teman:
Gain-Cell Embedded DRAM Under Cryogenic Operation - A First Study. 1319-1324 - Jinbo Chen, Chengcheng Lu, Jiacheng Ni, Xiaochen Guo, Patrick Girard, Yuanqing Cheng:
DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect. 1325-1334 - Wei-pei Huang, Ray C. C. Cheung, Hong Yan:
An Efficient Parallel Processor for Dense Tensor Computation. 1335-1347 - Deepak Dasalukunte, Richard Dorrance, Le Liang, Lu Lu:
A Vector Processor for Mean Field Bayesian Channel Estimation. 1348-1359 - Mohsen Javadi, Hossein Miar Naimi, Saheed Tijani, Danilo Manstretta, Rinaldo Castello:
A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture. 1360-1369 - Xiuqin Chu, Wenting Guo, Jun Wang, Feng Wu, Yuhuan Luo, Yushan Li:
Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links. 1370-1378 - Kuang-Wei Cheng, Shih-En Chen:
An Ultralow-Power OOK/BFSK/DBPSK Wake-Up Receiver Based on Injection-Locked Oscillator. 1379-1391 - Pierpaolo Palestri, Ahmed Elnaqib, Davide Menin, Klaid Shyti, Francesco Brandonisio, Andrea Bandiziol, Davide Rossi, Roberto Nonis:
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation. 1392-1401 - Pedro Tauã Lopes Pereira, Guilherme Paim, Patrícia Ücker Leleu da Costa, Eduardo Antônio César da Costa, Sérgio Jose Melo de Almeida, Sergio Bampi:
Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design. 1402-1415 - Meng Ni, Xiao Wang, Fule Li, Zhihua Wang:
A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation. 1416-1427 - Jiann-Jong Chen, Yuh-Shyan Hwang, Jyun-Heng Wu, Chien-Hung Lai, Yi-Tsen Ku:
A New Improved V-Square-Controlled Buck Converter With Rail-to-Rail OTA-Based Current-Sensing Circuits. 1428-1436 - Jeongwoo Heo, Taewhan Kim:
Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller. 1437-1450 - Pampa Howladar, Pranab Roy, Hafizur Rahaman:
Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique for Intelligent Cross-Contamination Avoidance. 1451-1464 - Rituparna Choudhury, Shaik Rafi Ahamed, Prithwijit Guha:
Training Accelerator for Two Means Decision Tree. 1465-1469 - Fei Lyu, Zhelong Mao, Jin Zhang, Yu Wang, Yuanyong Luo:
PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers. 1470-1474 - Erik Larsson, Zehang Xiang, Prathamesh Murali:
Graceful Degradation of Reconfigurable Scan Networks. 1475-1479 - Yangtao Dong, Chirn Chye Boon, Xin Ding, Chenyang Li, Zhe Liu:
A Bidirectional Nonlinearly Coupled QVCO With Passive Phase Interpolation for Multiphase Signals Generation. 1480-1484 - Haoyu Zhuang, Wenzhen Cao, Xizhu Peng, He Tang:
A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback. 1485-1489 - Gyanendra Singh, Samba Raju Chiluveru, Balasubramanian Raman, Manoj Tripathy, Brajesh Kumar Kaushik:
Novel Architecture for Lifting Discrete Wavelet Packet Transform With Arbitrary Tree Structure. 1490-1494 - Yoshisato Yokoyama, Yuichiro Ishii, Koji Nii, Kazutoshi Kobayashi:
Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs. 1495-1499 - Irith Pomeranz:
Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation. 1500-1504
Volume 29, Number 8, August 2021
- Ahmet Turan Erozan, Simon Bosse, Mehdi B. Tahoori:
Defect Detection in Transparent Printed Electronics Using Learning-Based Optical Inspection. 1505-1517 - Karthikeyan Nagarajan, Farid Uddin Ahmed, Mohammad Nasim Imtiaz Khan, Asmit De, Masud H. Chowdhury, Swaroop Ghosh:
SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM. 1518-1528 - Abdulrahman Alaql, Md. Moshiur Rahman, Swarup Bhunia:
SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking. 1529-1542 - Prashansa Mukim, Forrest Brewer:
Multiwire Phase Encoding: A Signaling Strategy for High-Bandwidth, Low-Power Data Movement. 1543-1552 - Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak:
X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan. 1553-1566 - Junyoung Song, Sewook Hwang, Chulwoo Kim:
A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology. 1567-1574 - Chuanshi Yang, Erik Olieman, Alphons Litjes, Lei Qiu, Kai Tang, Yuanjin Zheng, Robert H. M. van Veldhoven:
An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth. 1575-1585 - Chi-Ray Huang, Lih-Yih Chiou:
An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM. 1586-1590 - Zhifei Lu, He Tang, Zhaofeng Ren, Ruogu Hua, Haoyu Zhuang, Xizhu Peng:
A Timing Mismatch Background Calibration Algorithm With Improved Accuracy. 1591-1595 - Sarah Azimi, Corrado De Sio, Luca Sterpone:
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication. 1596-1600
Volume 29, Number 9, September 2021
- Meysam Akbari, Safwan Mawlood Hussein, Yasir Hashim, Kea-Tiong Tang:
An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers. 1601-1611 - Nikos Temenos, Paul P. Sotiriadis:
Nonscaling Adders and Subtracters for Stochastic Computing Using Markov Chains. 1612-1623 - Gianna Paulin, Renzo Andri, Francesco Conti, Luca Benini:
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures. 1624-1637 - Qingkun Chen, Wenjin Huang, Yuze Peng, Yihua Huang:
A Reinforcement Learning-Based Framework for Solving the IP Mapping Problem. 1638-1651 - Jai-Ming Lin, Wei-Yi Chang, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu:
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC. 1652-1664 - Jiangchao Wu, Hou-Man Leong, Yang Jiang, Man-Kay Law, Pui-In Mak, Rui Paulo Martins:
A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS. 1665-1669 - Jiajing Gao, Wei Zhang, Yanyan Liu, Hao Wang, Jianhan Zhao:
High-Performance Concatenation Decoding of Reed-Solomon Codes With SPC Codes. 1670-1674 - Abhijit Das, John Jose, Prabhat Mishra:
Data Criticality in Multithreaded Applications: An Insight for Many-Core Systems. 1675-1679 - Gwangho Lee, Sunwoo Lee, Dongsuk Jeon:
Dynamic Block-Wise Local Learning Algorithm for Efficient Neural Network Training. 1680-1684
Volume 29, Number 10, October 2021
- Na Niu, Fangfa Fu, Bing Yang, Qiang Wang, Xinpeng Li, Fengchang Lai, Jinxiang Wang:
PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems. 1685-1692 - Hritom Das, Ali Ahmad Haidous, Scott C. Smith, Na Gong:
Flexible Low-Cost Power-Efficient Video Memory With ECC-Adaptation. 1693-1706 - M. Sultan M. Siddiqui, Zhao Chuan Lee, Tony Tae-Hyoung Kim:
A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI. 1707-1719 - Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng:
A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications. 1720-1729 - Kaniz Mishty, Mehdi Sadi:
Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM. 1730-1742 - Aqeeb Iqbal Arka, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures. 1743-1756 - Morteza Hosseini, Nitheesh Kumar Manjunath, Bharat Prakash, Arnab Neelim Mazumder, Vandana Chandrareddy, Houman Homayoun, Tinoosh Mohsenin:
Cyclic Sparsely Connected Architectures for Compact Deep Convolutional Neural Networks. 1757-1770 - Tianqi Kong, Shuguo Li:
Design and Analysis of Approximate 4-2 Compressors for High-Accuracy Multipliers. 1771-1781 - Bin Zhou, Guangsen Wang, Guisheng Jie, Qing Liu, Zhiwei Wang:
A High-Speed Floating-Point Multiply-Accumulator Based on FPGAs. 1782-1789 - Noel Daniel Gundi, Tahmoures Shabanian, Prabal Basu, Pramesh Pandey, Sanghamitra Roy, Koushik Chakraborty:
EFFORT: A Comprehensive Technique to Tackle Timing Violations and Improve Energy Efficiency of Near-Threshold Tensor Processing Units. 1790-1799 - Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi:
A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS. 1800-1811
Volume 29, Number 11, November 2021
- Nikos Temenos, Paul P. Sotiriadis:
Stochastic Computing Max & Min Architectures Using Markov Chains: Design, Analysis, and Implementation. 1813-1823 - Zhenxin Zhao, Lihong Zhang:
Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis. 1824-1837 - Po-Hsuan Wei, Boris Murmann:
Analog and Mixed-Signal Layout Automation Using Digital Place-and-Route Tools. 1838-1849 - Mohamed B. Elamien, Brent J. Maundy, Leonid Belostotski, Ahmed S. Elwakil:
Analog Circuit Design Using Symbolic Math Toolboxes: Demonstrative Examples. 1850-1860 - Ahmed S. Emara, Denis Romanov, Gordon W. Roberts, Sadok Aouini, Soheyl Ziabakhsh, Mahdi Parvizi, Naim Ben-Hamida:
An Area-Efficient High-Resolution Segmented ΣΔ-DAC for Built-In Self-Test Applications. 1861-1874 - Shao-Chun Hung, Yi-Chen Lu, Sung Kyu Lim, Krishnendu Chakrabarty:
Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs. 1875-1888 - Jin-Tai Yan:
Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs. 1889-1902 - Qianqian Wang, Fei Liu, Cece Huang, Qianhui Li, Zongliang Huo:
A Small Ripple and High-Efficiency Wordline Voltage Generator for 3-D nand Flash Memories. 1903-1911 - Madhan Thirumoorthi, Marko Jovanovic, Mitra Mirhassani, Mohammed A. S. Khalid:
Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF. 1912-1921 - Yingchun Lu, Xinyu Wang, Yanjie Wang, Yuan Zhang, Liang Yao, Maoxiang Yi, Zhengfeng Huang, Huaguo Liang:
Pure Digital Scalable Mixed Entropy Separation Structure for Physical Unclonable Function and True Random Number Generator. 1922-1929 - Abdullah Aljuffri, Marc Zwalua, Cezar Rodolfo Wedig Reinbrecht, Said Hamdioui, Mottaqiallah Taouil:
Applying Thermal Side-Channel Attacks on Asymmetric Cryptography. 1930-1942 - Milad Bahadori, Kimmo Järvinen, Valtteri Niemi:
FPGA Implementations of 256-Bit SNOW Stream Ciphers for Postquantum Mobile Security. 1943-1954 - Dawen Xu, Meng He, Cheng Liu, Ying Wang, Long Cheng, Huawei Li, Xiaowei Li, Kwang-Ting Cheng:
R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors. 1955-1966 - Libo Chang, Shengbing Zhang, Huimin Du, Yue Chen, Shiyu Wang:
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA. 1967-1980 - Hongtao Zhong, Shengjie Cao, Li Jiang, Xia An, Vijaykrishnan Narayanan, Yongpan Liu, Huazhong Yang, Xueqing Li:
DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays. 1981-1993 - Neelam Arya, Manisha Pattanaik, G. K. Sharma:
Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications. 1994-1997 - Heiner Bauer, Sebastian Höppner, Chris Paul Iatrou, Zohra Charania, Stephan Hartmann, Saif-Ur Rehman, Andreas Dixius, Georg Ellguth, Dennis Walter, Johannes Uhlig, Felix Neumärker, Marc Berthel, Marco Stolba, Florian Kelber, Leon Urbas, Christian Mayr:
Hardware Implementation of an OPC UA Server for Industrial Field Devices. 1998-2002 - Chenggang Yan, Jie Sun, Weiqiang Liu:
An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering. 2003-2007 - Yongwoon Song, Jooyoung Hwang, Insoon Jo, Hyukjun Lee:
Highly Available Packet Buffer Design With Hybrid Nonvolatile Memory. 2008-2012
Volume 29, Number 12, December 2021
- Vaibhav Venugopal Rao, Ioannis Savidis:
Performance and Security Analysis of Parameter-Obfuscated Analog Circuits. 2013-2026 - Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu:
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption. 2027-2039 - Sina Sayyah Ensan, Karthikeyan Nagarajan, Mohammad Nasim Imtiaz Khan, Swaroop Ghosh:
SCARE: Side Channel Attack on In-Memory Computing for Reverse Engineering. 2040-2051 - Soner Seçkiner, Selçuk Köse:
Preprocessing of the Physical Leakage Information to Combine Side-Channel Distinguishers. 2052-2063 - Turki Alnuayri, S. Saqib Khursheed, Antonio Leonel Hernández Martínez, Daniele Rossi:
Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs. 2064-2075 - Sandeep Kumar, Atin Mukherjee:
A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications. 2076-2085 - Saurabh Kumar, Minki Cho, Luke R. Everson, Andres Malavasi, Dan Lake, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De, Chris H. Kim:
A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses. 2086-2097 - Jaewon Choi, Nam-Seog Kim:
A Spurious and Oscillator Pulling Free CMOS Quadrature LO-Generator for Cellular NB-IoT. 2098-2109 - Juncheng Wang, Xuefeng Chen, Rui Bai, Patrick Yin Chiang, Quan Pan:
A 4 × 10 Gb/s Adaptive Optical Receiver Utilizing Current-Reuse and Crosstalk-Remove. 2110-2118 - Zakaria El Alaoui Ismaili, Wessam Ajib, Frederic Nabki, François Gagnon:
A 0.1-9-GHz Frequency Synthesizer for Avionic SDR Applications in 0.13-μm CMOS Technology. 2119-2129 - Mohamed Elshamy, Alhassan Sayed, Marie-Minerve Louërat, Hassan Aboushady, Haralampos-G. Stratigopoulos:
Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security. 2130-2142 - Kentaro Yoshioka:
VCO-Based Comparator: A Fully Adaptive Noise Scaling Comparator for High-Precision and Low-Power SAR ADCs. 2143-2152 - Zule Xu, Naoki Ojima, Shuowei Li, Tetsuya Iizuka:
An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC. 2153-2162 - Islam Mansour, Marwa Mansour, Mohamed Aboualalaa, Ahmed Allam, Adel B. Abdel-Rahman, Ramesh K. Pokharel, Mohammed Abo-Zahhad:
A Multiband VCO Using a Switched Series Resonance for Fine Frequency Tuning Sensitivity and Phase Noise Improvement. 2163-2171 - Chua-Chin Wang, Lean Karlo S. Tolentino, Chia-Yi Huang, Chia-Hung Yeh:
A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM. 2172-2185 - Nicholas Jao, Akshay Krishna Ramanathan, John Sampson, Vijaykrishnan Narayanan:
Sparse Vector-Matrix Multiplication Acceleration in Diode-Selected Crossbars. 2186-2196 - Ming Ling, Qingde Lin, Ke Tan, Tianxiang Shao, Shan Shen, Jun Yang:
A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages. 2197-2209 - Xinyu Du, Lidan Wang, Dengwei Yan, Shukai Duan:
A Multiring Julia Fractal Chaotic System With Separated-Scroll Attractors. 2210-2219 - Juan Sebastian Piedrahita Giraldo, Vikram Jain, Marian Verhelst:
Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting. 2220-2228
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