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ORCIDLinda S. Milor
Linda Milor
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- affiliation: Georgia Institute of Technology, Atlanta, USA
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2020 – today
- 2022
[j46]Rui Zhang, Taizhi Liu, Kexin Yang, Linda Milor
:
CacheEM: For Reliability Analysis on Cache Memory Aging Due to Electromigration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 3078-3091 (2022)- 2021
- [j45]Rui Zhang, Kexin Yang, Zhaocheng Liu, Taizhi Liu, Wenshan Cai, Linda Milor:
A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 857-870 (2021) - 2020
- [j44]Rui Zhang, Taizhi Liu, Kexin Yang, Chang-Chih Chen, Linda Milor:
SRAM Stability Analysis and Performance-Reliability Tradeoff for Different Cache Configurations. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 620-633 (2020) - [j43]Yi-Da Wu, Kexin Yang, Shu-Han Hsu, Linda Milor:
Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2658-2671 (2020) - [c37]Rui Zhang, Zhaocheng Liu, Kexin Yang, Taizhi Liu, Wenshan Cai, Linda Milor:
Inverse Design of FinFET SRAM Cells. IRPS 2020: 1-6
2010 – 2019
- 2019
- [j42]Dae-Hyun Kim, Shu-Han Hsu, Linda Milor:
Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1640-1651 (2019) - [c36]Shu-Han Hsu, Kexin Yang, Linda Milor:
Reliability and Accelerated Testing of 14nm FinFET Ring Oscillators. DCIS 2019: 1-7 - [c35]Shu-Han Hsu, Ying-Yuan Huang, Kexin Yang, Linda Milor:
Identification of Failure Modes for Circuit Samples with Confounded Causes of Failure. IOLTS 2019: 257-262 - [c34]Shu-Han Hsu, Kexin Yang, Linda Milor:
Machine Learning for Detection of Competing Wearout Mechanisms. IRPS 2019: 1-9 - [c33]Rui Zhang, Kexin Yang, Taizhi Liu, Linda Milor:
Impact of Front-End Wearout Mechanisms on the Performance of a Ring Oscillator-Based Thermal Sensor. IWASI 2019: 258-263 - 2018
- [j41]Taizhi Liu, Chang-Chih Chen, Linda Milor:
Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors. IEEE Trans. Emerg. Top. Comput. 6(2): 219-232 (2018) - [j40]Kexin Yang, Taizhi Liu, Rui Zhang, Linda Milor:
A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2470-2482 (2018) - [c32]Kexin Yang, Rui Zhang, Taizhi Liu, Dae Hyun Kim, Linda Milor:
Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET Technology. DCIS 2018: 1-6 - [c31]Rui Zhang, Kexin Yang, Taizhi Liu, Linda Milor:
Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout Mechanisms. DCIS 2018: 1-6 - [c30]Kexin Yang, Taizhi Liu, Rui Zhang, Linda Milor:
Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technology. VTS 2018: 1-6 - 2017
- [j39]Dae-Hyun Kim, Linda Milor:
Analysis of errors in estimating wearout characteristics of time-dependent dielectric breakdown using system-level accelerated life test. Microelectron. Reliab. 76-77: 47-52 (2017) - [j38]Kexin Yang, Taizhi Liu, Rui Zhang, Dae Hyun Kim, Linda Milor:
Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuits. Microelectron. Reliab. 76-77: 81-86 (2017) - [j37]Rui Zhang, Taizhi Liu, Kexin Yang, Linda Milor:
Analysis of time-dependent dielectric breakdown induced aging of SRAM cache with different configurations. Microelectron. Reliab. 76-77: 87-91 (2017) - [j36]Dae-Hyun Kim, Linda Milor:
An ECC-Assisted Postpackage Repair Methodology in Main Memory Systems. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2045-2058 (2017) - [j35]Soonyoung Cha, Taizhi Liu, Linda Milor:
Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2271-2284 (2017) - [c29]Woongrae Kim, Taizhi Liu, Linda Milor:
On-line monitoring of system health using on-chip SRAMs as a wearout sensor. IOLTS 2017: 253-258 - [c28]Soonyoung Cha, Linda Milor:
Adaptive supply voltage and duty cycle controller for yield-power optimization of ICs. IWASI 2017: 133-138 - [c27]Dae-Hyun Kim, Linda Milor:
A methodology for estimating memory lifetime using a system-level accelerated life test and error-correcting codes. VTS 2017: 1-6 - 2016
- [j34]Fahad Ahmed, Linda S. Milor:
Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2184-2194 (2016) - [j33]Woongrae Kim, Chang-Chih Chen, Dae Hyun Kim, Linda Milor:
Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2521-2534 (2016) - [j32]Chang-Chih Chen, Taizhi Liu, Linda Milor:
System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2712-2725 (2016) - [c26]Taizhi Liu, Chang-Chih Chen, Jiadong Wu, Linda S. Milor:
SRAM stability analysis for different cache configurations due to Bias Temperature Instability and Hot Carrier Injection. ICCD 2016: 225-232 - [c25]Dae Hyun Kim, Linda S. Milor:
ECC-ASPIRIN: An ECC-assisted post-package repair scheme for aging errors in DRAMs. VTS 2016: 1-6 - 2015
- [j31]Chang-Chih Chen, Taizhi Liu, Soonyoung Cha, Linda S. Milor:
Processor-level reliability simulator for time-dependent gate dielectric breakdown. Microprocess. Microsystems 39(8): 950-960 (2015) - [j30]Taizhi Liu, Chang-Chih Chen, Woongrae Kim, Linda Milor:
Comprehensive reliability and aging analysis on SRAMs within microprocessor systems. Microelectron. Reliab. 55(9-10): 1290-1296 (2015) - [j29]Dae Hyun Kim, Soonyoung Cha, Linda S. Milor:
AVERT: An elaborate model for simulating variable retention time in DRAMs. Microelectron. Reliab. 55(9-10): 1313-1319 (2015) - [j28]Taizhi Liu, Chang-Chih Chen, Soonyoung Cha, Linda Milor:
System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown. Microelectron. Reliab. 55(9-10): 1334-1340 (2015) - [j27]Soonyoung Cha, Dae Hyun Kim, Taizhi Liu, Linda S. Milor:
The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system. Microelectron. Reliab. 55(9-10): 1404-1411 (2015) - [j26]Dae Hyun Kim, Soonyoung Cha, Linda S. Milor:
Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs. Microelectron. Reliab. 55(9-10): 2113-2118 (2015) - [j25]Chang-Chih Chen, Linda S. Milor:
Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout Mechanisms. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2065-2076 (2015) - [c24]Taizhi Liu, Chang-Chih Chen, Linda S. Milor:
Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splines. ISQED 2015: 272-279 - [c23]Woongrae Kim, Chang-Chih Chen, Taizhi Liu, Soonyoung Cha, Linda Milor:
Estimation of remaining life using embedded SRAM for wearout parameter extraction. IWASI 2015: 243-248 - [c22]Woongrae Kim, Chang-Chih Chen, Soonyoung Cha, Linda Milor:
MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array. VTS 2015: 1-6 - [c21]Sule Ozev, Linda Milor:
Panel: Analog/RF BIST: Are we there yet? VTS 2015: 1 - 2014
- [j24]Chang-Chih Chen, Muhammad Bashir, Linda S. Milor, Daehyun Kim, Sung Kyu Lim:
Simulation of system backend dielectric reliability. Microelectron. J. 45(10): 1327-1334 (2014) - [j23]Muhammad Muqarrab Bashir, Chang-Chih Chen, Linda Milor, Dae Hyun Kim, Sung Kyu Lim:
Backend Dielectric Reliability Full Chip Simulator. IEEE Trans. Very Large Scale Integr. Syst. 22(8): 1750-1762 (2014) - [c20]Soonyoung Cha, Chang-Chih Chen, Taizhi Liu, Linda S. Milor:
Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements. VTS 2014: 1-6 - [c19]Woongrae Kim, Linda Milor:
Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells. VTS 2014: 1-6 - 2013
- [j22]Zhengliang Lv, Shiyuan Yang, Hong Wang, Linda Milor:
A Delay Evaluation Circuit for Analog BIST Function. IEICE Trans. Electron. 96-C(3): 393-401 (2013) - [j21]Chang-Chih Chen, Fahad Ahmed, Linda Milor:
Impact of NBTI/PBTIon SRAMs within microprocessor systems: Modeling, simulation, and analysis. Microelectron. Reliab. 53(9-11): 1183-1188 (2013) - [c18]Chang-Chih Chen, Linda Milor:
System-level modeling and microprocessor reliability analysis for backend wearout mechanisms. DATE 2013: 1615-1620 - [c17]Chang-Chih Chen, Linda Milor:
System-level modeling and reliability analysis of microprocessor systems. IWASI 2013: 178-183 - 2012
- [j20]Zhengliang Lv, Linda S. Milor, Shiyuan Yang:
Statistical model of NBTI and reliability simulation for analogue circuits. Microelectron. Reliab. 52(9-10): 1837-1842 (2012) - [j19]Chang-Chih Chen, Fahad Ahmed, Dae Hyun Kim, Sung Kyu Lim, Linda Milor:
Backend dielectric reliability simulator for microprocessor system. Microelectron. Reliab. 52(9-10): 1953-1959 (2012) - [j18]Fahad Ahmed, Linda Milor:
Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 855-864 (2012) - [c16]Zhengliang Lv, Linda Milor, Shiyuan Yang:
Impact of NBTI on analog components. ETS 2012: 1 - [c15]Chang-Chih Chen, Fahad Ahmed, Linda Milor:
A comparative study of wearout mechanisms in state-of-art microprocessors. ICCD 2012: 271-276 - [c14]Fahad Ahmed, Mohamed M. Sabry, David Atienza, Linda Milor:
Wearout-aware compiler-directed register assignment for embedded systems. ISQED 2012: 33-40 - 2011
- [j17]Muhammad Bashir, Linda Milor, Dae Hyun Kim, Sung Kyu Lim:
Impact of irregular geometries on low-k dielectric breakdown. Microelectron. Reliab. 51(9-11): 1582-1586 (2011) - 2010
- [j16]Fahad Ahmed, Linda Milor:
Via wearout detection with on-chip monitors. Microelectron. J. 41(11): 789-800 (2010) - [j15]Muhammad Bashir, Linda S. Milor, Dae Hyun Kim, Sung Kyu Lim:
Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown. Microelectron. Reliab. 50(9-11): 1341-1346 (2010) - [c13]Muhammad Bashir, Linda S. Milor:
Towards a chip level reliability simulator for copper/low-k backend processes. DATE 2010: 279-282 - [c12]Fahad Ahmed, Linda Milor:
Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST. VTS 2010: 63-68
2000 – 2009
- 2009
- [j14]Muhammad Bashir, Linda Milor:
Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements. IEEE Des. Test Comput. 26(6): 18-27 (2009) - [j13]Seyed-Abdollah Aftabjahani, Linda S. Milor:
Timing analysis with compact variation-aware standard cell models. Integr. 42(3): 312-320 (2009) - [j12]Muhammad Bashir, Linda S. Milor:
A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation. Microelectron. Reliab. 49(9-11): 1096-1102 (2009) - [j11]Cheng Jia, Linda Milor:
A DLL Design for Testing I/O Setup and Hold Times. IEEE Trans. Very Large Scale Integr. Syst. 17(11): 1579-1592 (2009) - [c11]Seyed-Abdollah Aftabjahani, Linda S. Milor:
Timing Analysis with Compact Variation-Aware Standard Cell Models. CSIE (3) 2009: 475-479 - [c10]Seyed-Abdollah Aftabjahani, Linda S. Milor:
Fast Variation-Aware Statistical Dynamic Timing Analysis. CSIE (3) 2009: 488-492 - [c9]Fahad Ahmed, Linda S. Milor:
Reliable cache design with detection of gate oxide breakdown using BIST. ICCD 2009: 366-371 - 2008
- [j10]Munkang Choi, Linda S. Milor:
Diagnosis of Optical Lithography Faults With Product Test Sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1657-1669 (2008) - [j9]Cheng Jia, Linda S. Milor:
A BIST Circuit for DLL Fault Detection. IEEE Trans. Very Large Scale Integr. Syst. 16(12): 1687-1695 (2008) - [c8]Seyed-Abdollah Aftabjahani, Linda S. Milor:
Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis. ISQED 2008: 148-151 - 2007
- [j8]Linda Milor, Changsoo Hong:
Backend dielectric breakdown dependence on linewidth and pattern density. Microelectron. Reliab. 47(9-11): 1473-1477 (2007) - [j7]Changsoo Hong, Linda Milor:
Modeling of the breakdown mechanisms for porous copper/low-k process flows. Microelectron. Reliab. 47(9-11): 1478-1482 (2007) - 2006
- [j6]Munkang Choi, Linda S. Milor:
Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1350-1367 (2006) - 2005
- [j5]Changsoo Hong, Linda S. Milor, Munkang Choi, Tom Lin:
Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models. Microelectron. Reliab. 45(9-11): 1305-1310 (2005) - 2004
- [j4]Changsoo Hong, Linda Milor, M. Z. Lin:
Analysis of the layout impact on electric fields in interconnect structures using finite element method. Microelectron. Reliab. 44(9-11): 1867-1871 (2004) - 2003
- [c7]Cheng Jia, Linda S. Milor:
A BIST Solution for The Test of I/O Speed. ITC 2003: 1023-1030 - 2002
- [j3]Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu:
Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5): 544-553 (2002) - 2000
- [c6]Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu:
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. ICCAD 2000: 62-67
1990 – 1999
- 1996
- [c5]Mien Li, Linda S. Milor:
Computing Parametric Yield Adaptively Using Local Linear Models. DAC 1996: 831-836 - [c4]Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jérôme Wojcik:
Is High Frequency Analog DFT Possible? VTS 1996: 214-215 - 1994
- [j2]Linda S. Milor, Alberto L. Sangiovanni-Vincentelli:
Minimizing production test time to detect faults in analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(6): 796-813 (1994) - 1990
- [c3]Linda Milor, Alberto L. Sangiovanni-Vincentelli:
Computing Parametric Yield Accurately and Efficiently. ICCAD 1990: 116-119 - [c2]Linda Milor, Alberto L. Sangiovanni-Vincentelli:
Optimal Test Set Design for Analog Circuits. ICCAD 1990: 294-297
1980 – 1989
- 1989
- [j1]Linda S. Milor, V. Visvanathan:
Detection of catastrophic faults in analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(2): 114-130 (1989) - 1986
- [c1]V. Visvanathan, Linda S. Milor:
An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation. SCG 1986: 207-215
Coauthor Index
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