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ORCIDSoonyoung Cha
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2010 – 2019
- 2018
[b1]Soonyoung Cha:
Frontend reliability analysis and modeling from device to integrated circuits for reliability and yield enhancement system. Georgia Institute of Technology, Atlanta, GA, USA, 2018- 2017
- [j6]Soonyoung Cha, Taizhi Liu, Linda Milor
:
Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements. IEEE Trans. Very Large Scale Integr. Syst. 25(8): 2271-2284 (2017) - [c4]Soonyoung Cha, Linda Milor:
Adaptive supply voltage and duty cycle controller for yield-power optimization of ICs. IWASI 2017: 133-138 - 2015
- [j5]Chang-Chih Chen, Taizhi Liu, Soonyoung Cha, Linda S. Milor:
Processor-level reliability simulator for time-dependent gate dielectric breakdown. Microprocess. Microsystems 39(8): 950-960 (2015) - [j4]Dae Hyun Kim, Soonyoung Cha, Linda S. Milor:
AVERT: An elaborate model for simulating variable retention time in DRAMs. Microelectron. Reliab. 55(9-10): 1313-1319 (2015) - [j3]Taizhi Liu, Chang-Chih Chen, Soonyoung Cha, Linda Milor:
System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown. Microelectron. Reliab. 55(9-10): 1334-1340 (2015) - [j2]Soonyoung Cha, Dae Hyun Kim, Taizhi Liu, Linda S. Milor:
The die-to-die calibrated combined model of negative bias temperature instability and gate oxide breakdown from device to system. Microelectron. Reliab. 55(9-10): 1404-1411 (2015) - [j1]Dae Hyun Kim, Soonyoung Cha, Linda S. Milor:
Built-in self-test for bias temperature instability, hot-carrier injection, and gate oxide breakdown in embedded DRAMs. Microelectron. Reliab. 55(9-10): 2113-2118 (2015) - [c3]Woongrae Kim, Chang-Chih Chen, Taizhi Liu, Soonyoung Cha, Linda Milor:
Estimation of remaining life using embedded SRAM for wearout parameter extraction. IWASI 2015: 243-248 - [c2]Woongrae Kim, Chang-Chih Chen, Soonyoung Cha, Linda Milor:
MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array. VTS 2015: 1-6 - 2014
- [c1]Soonyoung Cha, Chang-Chih Chen, Taizhi Liu, Linda S. Milor:
Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurements. VTS 2014: 1-6
Coauthor Index
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