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ORCIDTad A. Kwasniewski
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- affiliation: Carleton University, Ottawa, Canada
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2010 – 2019
- 2017
[c51]Leonard MacEachem, Xin-Jie Wang, Tad A. Kwasniewski:
On-die power grid broadband model determination using a priori narrowband measurements. MWSCAS 2017: 1493-1496- 2016
- [j12]Xinjie Wang, Tadeusz Kwasniewski:
A reduced reference spur multiplying delay-locked loop. Int. J. Circuit Theory Appl. 44(8): 1620-1627 (2016) - 2015
- [c50]Haizheng Guo, Tadeusz Kwasniewski:
A DLL-based period synthesis. CCECE 2015: 103-106 - [c49]Haizheng Guo, Tadeusz Kwasniewski:
A DLL fractional M/N frequency synthesizer. CCECE 2015: 114-117 - [c48]Zhe Jiang, Haizheng Guo, Tadeusz Kwasniewski:
Low noise CMOS voltage-control oscillator design methodology with emphasis on non-linear effect contributions, 2.4 GHz CMOS design example. CCECE 2015: 686-690 - 2013
- [c47]Haizheng Guo, Xinjie Wang, Tadeusz Kwasniewski:
Spur analysis and reduction of edge combining DLL-based frequency multiplier. CCECE 2013: 1-4 - 2012
- [c46]Haizheng Guo, Tad A. Kwasniewski:
A DLL-based fractional-N frequency synthesizer with a programmable injection clock. CCECE 2012: 1-4 - [c45]Chao He, Tadeusz Kwasniewski:
Bang-Bang CDR's acquisition, locking, and jitter tolerance. CCECE 2012: 1-4 - [c44]Chao He, Tadeusz Kwasniewski:
A novel fractional-N PLL architecture with hybrid of DCO and VCO. CCECE 2012: 1-4 - 2011
- [c43]Harry Tai, Peter Noel, Tad A. Kwasniewski:
A reduced signal feed-through 6-tap pre-emphasis circuit for use in a 10GB/S backplane communications system. SoCC 2011: 114-117 - 2010
- [j11]Huong Ho, Valek Szwarc, Tad A. Kwasniewski:
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination. J. Signal Process. Syst. 61(3): 353-365 (2010) - [c42]Haizheng Guo, Bo Wang, Bangli Liang, Tad A. Kwasniewski, Robert Sobot:
Optimized LNA for analog RF front-end circuit in brain-machine interface. WCNIS 2010: 147-150
2000 – 2009
- 2009
- [j10]Huong Ho, Valek Szwarc, Tad A. Kwasniewski:
A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications. Int. J. Reconfigurable Comput. 2009: 529512:1-529512:14 (2009) - [j9]Lei Zhang, Tadeusz Kwasniewski:
FIR filter optimization using bit-edge equalization in high-speed backplane data transmission. Microelectron. J. 40(10): 1449-1457 (2009) - [j8]Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski:
A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application. IEEE Trans. Very Large Scale Integr. Syst. 17(12): 1742-1748 (2009) - [c41]Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski:
A full-rate truly monolithic CMOS CDR for low-cost applications. CCECE 2009: 1208-1212 - [c40]Dianyong Chen, Bo Wang, Bangli Liang, Tad A. Kwasniewski:
A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously. CCECE 2009: 1213-1216 - [c39]Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tad A. Kwasniewski:
A programmable pre-cursor ISI equalization circuit for high-speed serial link over highly lossy backplane channel. CCECE 2009: 1221-1226 - [c38]Bangli Liang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski, Zhigong Wang:
A monolithic high modulation efficiency CMOS laser diode / modulator driver. ICT 2009: 361-363 - [c37]Bo Wang, Dianyong Chen, Bangli Liang, Jinguang Jiang, Tadeusz Kwasniewski:
Modeling, Simulation and Analysis of High-Speed Serial Link Transceiver over Band-Limited Channel. UKSim 2009: 574-578 - [c36]Dianyong Chen, Bo Wang, Bangli Liang, Tadeusz Kwasniewski:
A Simulator for High-Speed Backplane Transceivers. UKSim 2009: 589-593 - 2008
- [c35]Tingjun Wen, Tadeusz Kwasniewski:
Phase Noise Simulation and Modeling of ADPLL by SystemVerilog. BMAS 2008: 29-34 - [c34]Bangli Liang, Tad A. Kwasniewski, Dianyong Chen:
A 42-Gb/s Decision Circuit in 0.13µm CMOS. CNSR 2008: 339-342 - [c33]Miao Li, Tad A. Kwasniewski, Shoujun Wang:
A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops. ISCAS 2008: 2358-2361 - [c32]Ramin Shariat-Yazdi, Tad A. Kwasniewski:
Low complexity sphere decoding algorithms. ISWCS 2008: 438-442 - [c31]Ramin Shariat-Yazdi, Tad A. Kwasniewski:
A multi-mode sphere detector architecture for WLAN applications. SoCC 2008: 155-158 - 2007
- [j7]Dianyong Chen, Wei Wang, Tadeusz Kwasniewski:
Design Considerations for a Direct RF Sampling Mixer. IEEE Trans. Circuits Syst. II Express Briefs 54-II(11): 934-938 (2007) - [c30]Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski:
A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS. CICC 2007: 543-546 - [c29]Ramin Shariat-Yazdi, Tadeusz Kwasniewski:
Dual Mode K-Best MIMO Detector Architecture and VLSI Implementation. ICECS 2007: 735-738 - [c28]Muhammad Usama, Tad A. Kwasniewski:
A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology. ISCAS 2007: 3047-3050 - 2006
- [j6]Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski:
A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction. IEEE Trans. Circuits Syst. II Express Briefs 53-II(11): 1205-1209 (2006) - [c27]Miao Li, Tad A. Kwasniewski, Shoujun Wang:
A 0.18µm CMOS Receiver with Decision-feedback Equalization for Backplane Applications. APCCAS 2006: 1039-1042 - [c26]Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski:
A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider. CCECE 2006: 701-704 - [c25]Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski:
An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur. CICC 2006: 761-764 - [c24]William Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel:
PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. DAC 2006: 1013-1016 - [c23]Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang:
A 0.18µm CMOS clock and data recovery circuit with extended operation range. ISCAS 2006 - [c22]Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski:
An eye detection technique for clock and data recovery applications. ISCAS 2006 - [c21]Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski:
A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System. SoCC 2006: 123-126 - 2005
- [c20]Miao Li, Tad A. Kwasniewski, Shoujun Wang, Yuming Tao:
A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology. ASP-DAC 2005: 679-682 - [c19]S. I. Ahmed, Kent Orthner, Tadeusz Kwasniewski:
Behavioral test benches for digital clock and data recovery circuits using Verilog-A. CICC 2005: 297-300 - [c18]Shoujun Wang, Haitao Mei, Mashkoor Baig, William Bereza, Tadeusz Kwasniewski, Rakesh H. Patel:
Design considerations for 2nd-order and 3rd-order bang-bang CDR loops. CICC 2005: 317-320 - [c17]Yuming Tao, William Bereza, Rakesh H. Patel, Sergey Y. Shumarayev, Tad A. Kwasniewski:
A signal integrity-based link performance simulation platform. CICC 2005: 725-728 - [c16]Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski:
A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO. Circuits, Signals, and Systems 2005: 128-131 - [c15]Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang:
A 0.18µm CMOS transceiver design for high-speed backplane data communications. ISCAS (2) 2005: 1158-1161 - [c14]Jing Chen, Miao Li, Tad A. Kwasniewski:
Decision feedback equalization for high-speed backplane data communications. ISCAS (2) 2005: 1274-1277 - [c13]S. I. Ahmed, Tad A. Kwasniewski:
An all-digital data recovery circuit optimization using Matlab/Simulink. ISCAS (5) 2005: 4485-4488 - [c12]Farhad Zarkeshvari, Peter Noel, Tad A. Kwasniewski:
PLL-Based Fractional-N Frequency Synthesizers. IWSOC 2005: 85-91 - [c11]Charles E. Berndt, Tad A. Kwasniewski:
A Review of Common Receive-End Adaptive Equalization Schemes and Algorithms for a High-Speed Serial Backplane. IWSOC 2005: 149-153 - [c10]Moeed Israr, Tad A. Kwasniewski:
Turbo Codes - Digital IC Design. IWSOC 2005: 341-346 - [c9]Miao Li, Peter Noel, Tad A. Kwasniewski, Shoujun Wang:
Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications. IWSOC 2005: 500-502 - 2004
- [c8]Arif A. Siddiqi, Tad A. Kwasniewski:
2.4 GHz RF down-conversion mixers in standard CMOS technology. ISCAS (4) 2004: 321-324 - [c7]Muhammad Usama, Tad A. Kwasniewski:
Design and comparison of CMOS Current Mode Logic latches. ISCAS (4) 2004: 353-356 - 2003
- [c6]Jingcheng Zhuang, Qingjin Du, Tad A. Kwasniewski:
A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer. CICC 2003: 301-304 - 2001
- [j5]Lizhong Sun, Tadeusz Kwasniewski:
A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator. IEEE J. Solid State Circuits 36(6): 910-916 (2001)
1990 – 1999
- 1999
- [c5]Lizhong Sun, Tad A. Kwasniewski:
A 1.25 GHz 0.35 μm monolithic CMOS PLL clock generator for data communications. CICC 1999: 265-268 - [c4]Lizhong Sun, Thierry Lepley, Franck Nozahic, Amaud Bellissant, Tad A. Kwasniewski, Bany Heim:
Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis. ISCAS (2) 1999: 152-155 - [c3]Lizhong Sun, Tad A. Kwasniewski, Kris Iniewski:
A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops. ISCAS (2) 1999: 176-179 - 1997
- [j4]Manop Thamsirianunt, Tadeusz Kwasniewski:
CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications. IEEE J. Solid State Circuits 32(10): 1511-1524 (1997) - 1996
- [c2]Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jérôme Wojcik:
Is High Frequency Analog DFT Possible? VTS 1996: 214-215 - 1995
- [j3]Navid Foroudi, Tadeusz Kwasniewski:
CMOS high-speed dual-modulus frequency divider for RF frequency synthesis. IEEE J. Solid State Circuits 30(2): 93-100 (1995) - 1994
- [j2]Valek Szwarc, Luc Desormeaux, Wilson Wong, Clifford P. S. Yeung, Chong H. Chan, Tad A. Kwasniewski:
A chip set for pipeline and parallel pipeline FFT architectures. J. VLSI Signal Process. 8(3): 253-265 (1994) - [c1]D. P. Noel, Tad A. Kwasniewski, Samy A. Mahmoud, Wilf P. LeBlanc:
A low power, single chip realization of a low-speed, low-delay CELP coder/decoder for indoor wireless systems. VTC 1994: 520-524 - 1991
- [j1]P. Mohanraj, David D. Falconer, Tad A. Kwasniewski:
Baseband Trellis-Coded Modulation with Combined Equalization/Decoding for High Bit Rate Digital Subscriber Loops. IEEE J. Sel. Areas Commun. 9(6): 871-875 (1991)
Coauthor Index
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