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2020 – today
- 2024
[c19]Yi-Xuan Huang, Po-Han Huang, Juin-Ming Lu, Tay-Jyi Lin, Tien-Fu Chen:
Efficient Inference of Transformers on Bare-Metal Devices with RISC-V Vector Processors. NewCAS 2024: 393-397- 2023
- [c18]Chia-Wei Chang, Jing-Jia Liou, Chih-Tsun Huang, Wei-Chung Hsu, Juin-Ming Lu:
MultiFuse: Efficient Cross Layer Fusion for DNN Accelerators with Multi-level Memory Hierarchy. ICCD 2023: 614-622 - [c17]Chih-Tsun Huang
, Juin-Ming Lu, Yao-Hua Chen, Ming-Chih Tung, Shih-Chieh Chang:
Optimization of AI SoC with Compiler-assisted Virtual Design Platform. ISPD 2023: 187-193 - [c16]Jyun-Siou Huang, Ting-Han Chou, Juin-Ming Lu, Chih-Tsun Huang, Jing-Jia Liou:
HierArch: A Cluster-Based DNN Accelerator with Hierarchical Buses for Design Space Exploration. SOCC 2023: 1-6 - 2022
- [c15]Kuan-Wei Hou, Hsueh-Hung Cheng, Chi Tung, Cheng-Wen Wu, Juin-Ming Lu:
Fault Modeling and Testing of Memristor-Based Spiking Neural Networks. ITC 2022: 92-99 - [c14]Che-Chang Yang, Yung-Tai Shih, Chun-Chen Chen, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu:
Efficient Segment-wise Pruning for DCNN Inference Accelerators. VLSI-DAT 2022: 1-4 - 2021
- [j2]Jai-Ming Lin, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu:
Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 985-997 (2021) - [j1]Jai-Ming Lin, Wei-Yi Chang, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu:
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC. IEEE Trans. Very Large Scale Integr. Syst. 29(9): 1652-1664 (2021) - [c13]Yang-Tsai Chen, Yu-Xiang Yen, Chun-Tse Chen, Tzu-Yu Chen, Chih-Tsun Huang, Jing-Jia Liou, Juin-Ming Lu:
Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks. AICAS 2021: 1-4 - [c12]Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu:
An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks. DATE 2021: 575-580 - 2020
- [c11]Po-Yao Chuang, Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu:
A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification. DAC 2020: 1-6 - [i1]Pai-Yu Tan, Po-Yao Chuang, Yen-Ting Lin, Cheng-Wen Wu, Juin-Ming Lu:
A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification. CoRR abs/2003.06310 (2020)
2010 – 2019
- 2019
- [c10]Yi-Che Lee, Ting-Shuo Hsu, Chun-Tse Chen, Jing-Jia Liou, Juin-Ming Lu:
NNSim: A Fast and Accurate SystemC/TLM Simulator for Deep Convolutional Neural Network Accelerators. VLSI-DAT 2019: 1-4 - 2018
- [c9]Jai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu:
A fast thermal-aware fixed-outline floorplanning methodology based on analytical models. ICCAD 2018: 1:1-1:8 - [c8]I-Hua Chen, Chung-Ta King, Yao-Hua Chen, Juin-Ming Lu:
Full System Emulation of Embedded Heterogeneous Multicores Based on QEMU. ICPADS 2018: 771-778 - [c7]Lih-Yih Chiou, Chun-Hao Chang, Liang-Ying Lu, Wei-Hsuan Yang, Yeong-Jar Chang, Juin-Ming Lu:
Fast Steady-State Thermal Analysis. ISOCC 2018: 15-16 - 2017
- [c6]Hao-Lun Wei, Chung-Ta King, Bhaskar Das, Mei-Chiao Peng, Chen-Chieh Wang, Hsun-Lun Huang, Juin-Ming Lu:
Application specific component-service-aware trace generation on Android-QEMU. SoCC 2017: 316-321 - [c5]Chun-Wei Chen, Ming-Der Shieh, Juin-Ming Lu, Hsun-Lun Huang, Yao-Hua Chen:
Content-aware line-based power modeling methodology for image signal processor. SoCC 2017: 346-350 - [c4]Ting-Shuo Hsu, Chao-Chieh Wu, Che-Wei Hsu, Chih-Tsun Huang, Jing-Jia Liou, Yao-Hua Chen, Juin-Ming Lu:
Design space exploration with a cycle-accurate systemC/TLM DRAM controller model. VLSI-DAT 2017: 1-4 - 2014
- [c3]Jih-Sheng Shen, Pao-Ann Hsiung, Juin-Ming Lu:
Reconfigurable Network-on-chip design for heterogeneous multi-core system architecture. HPCS 2014: 523-526 - [c2]Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu:
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. SoCC 2014: 286-291
2000 – 2009
- 2000
- [c1]Juin-Ming Lu, Cheng-Wen Wu:
Cost and Benefit Models for Logic and Memory BIST. DATE 2000: 710-714
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