default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDTay-Jyi Lin
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
[c49]Tay-Jyi Lin, Ze Li, Yun-Cheng Chen, Chien-Tung Liu, Tien-Fu Chen, Jinn-Shyan Wang:
A 40-nm 13.88-TOPS/W FC-DNN Engine for 16-bit Intelligent Audio Processing Featuring Weight-Sharing and Approximate Computing. HCS 2024: 1- [c48]Yi-Xuan Huang, Po-Han Huang, Juin-Ming Lu, Tay-Jyi Lin, Tien-Fu Chen:
Efficient Inference of Transformers on Bare-Metal Devices with RISC-V Vector Processors. NewCAS 2024: 393-397 - 2023
- [j13]Tay-Jyi Lin
, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, Jinn-Shyan Wang:
A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. IEEE Trans. Circuits Syst. II Express Briefs 70(12): 4564-4568 (2023) - [c47]Po-Han Chen, Tay-Jyi Lin, Chingwei Yeh, Pei-Zen Chang, Wei-Chang Li:
Force-Sensing Intelligent Vise for Cutting Dynamics Monitoring in Machining. SENSORS 2023: 1-4 - 2022
- [c46]Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang:
A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. ASP-DAC 2022: 7-8 - 2020
- [c45]Jinn-Shyan Wang, Cheng-Xin Xue, Chien-Tung Liu, Tay-Jyi Lin:
A 0.21V 40nm NAND-ROM for IoT Sensing Systems with Long Standby Periods. ISCAS 2020: 1-4
2010 – 2019
- 2018
- [c44]Chien-Tung Liu, Zhe-Wei Chang, Shih-Nung Wei, Jinn-Shyan Wang, Tay-Jyi Lin:
A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs. SoCC 2018: 1-6 - [c43]Pei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen, Chien-Tung Liu, Tay-Jyi Lin, Jinn-Shyan Wang:
Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications. SoCC 2018: 250-253 - 2017
- [j12]Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3341-3354 (2017) - [c42]Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin, Jinn-Shyan Wang:
An all-n-type dynamic adder for ultra-low-leakage IoT devices. ASICON 2017: 68-71 - [c41]Yi-Hsuan Ting, Tay-Jyi Lin, Cheng-Chun Chang, Chih-Chien Hu, Chingwei Yeh, Jinn-Shyan Wang:
Approximate Distributed Arithmetic for Variable-Latency Table Lookup. NGCAS 2017: 137-140 - 2016
- [j11]Po-Hao Wang, Shang-Jen Tsai, Rizal Tanjung, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. Integr. 54: 24-36 (2016) - [j10]Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations. IEEE Trans. Circuits Syst. II Express Briefs 63-II(10): 969-973 (2016) - [j9]Tay-Jyi Lin, Ting-Yu Shyu:
Speculative Lookahead for Energy-Efficient Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 50-57 (2016) - [c40]Chao-Yang Chang, Chung-Hsun Huang, Hui-Fu Chen, Chingwei Yeh, Yuan-Sun Chu, Tay-Jyi Lin:
A low complexity edge-preserved image compression algorithm for LCD overdrive. GCCE 2016: 1-2 - [c39]Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen:
Variable-length VLIW encoding for code size reduction in embedded processors. SoCC 2016: 296-299 - [c38]Yi-Hsuan Ting, Chih-Yang Wang, Yu-Sian Chang, Tay-Jyi Lin, Shih-Chieh Chang, Jinn-Shyan Wang:
Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation. SoCC 2016: 350-355 - 2015
- [j8]Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Tay-Jyi Lin, Chih-Wen Hsueh, Naehyuck Chang:
System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach. ACM Trans. Embed. Comput. Syst. 14(1): 8:1-8:26 (2015) - [c37]Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang:
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches. ASICON 2015: 1-4 - 2014
- [c36]Chung-Hsun Huang, Wei-Jen Chen, Keng-Jui Chang, Yi-Hsuan Ting, Keng-Chang Hsu, Yu-Fu Pan, Chao-Chun Chen, Yuan-Hua Chu, Tay-Jyi Lin, Jinn-Shyan Wang:
Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET). Hot Chips Symposium 2014: 1 - [c35]Chingwei Yeh, Chen-Yao Tsai, Tay-Jyi Lin, Jiun-In Guo:
Maintaining color fidelity for dual-shot HDR imaging. ICCE-TW 2014: 65-66 - 2013
- [c34]Tay-Jyi Lin, Cheng-An Chien, Pei-Yao Chang, Ching-Wen Chen, Po-Hao Wang, Ting-Yu Shyu, Chien-Yung Chou, Shien-Chun Luo, Jiun-In Guo, Tien-Fu Chen, Gene C. H. Chuang, Yuan-Hua Chu, Liang-Chia Cheng, Hong-Men Su, Chewnpu Jou, Meikei Ieong, Cheng-Wen Wu, Jinn-Shyan Wang:
A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. ISSCC 2013: 158-159 - [c33]Po-Hao Wang, Wei-Chung Cheng, Yung-Hui Yu, Tang-Chieh Kao, Chi-Lun Tsai, Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen:
Variation-aware and adaptive-latency accesses for reliable low voltage caches. VLSI-SoC 2013: 358-363 - 2012
- [j7]Pei-Yao Chang, Tay-Jyi Lin, Jinn-Shyan Wang, Yen-Hsiang Yu:
A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 908-912 (2012) - [c32]Shyang-Chyun Chen, Chao-Chuan Chen, Wen-Chi Guo, Tay-Jyi Lin, Ching-Wei Yeh:
Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications. ASP-DAC 2012: 473-474 - [c31]Tay-Jyi Lin, Yu-Ting Kuo, Yu-Jung Tsai, Ting-Yu Shyu, Yuan-Hua Chu:
Energy-efficient RISC design with on-demand circuit-level timing speculation. ASP-DAC 2012: 477-478 - [c30]Shih-Hao Ou, Che-Wei Yeh, Tay-Jyi Lin, Chih-Wei Liu:
A smart stream controller for efficient implementation of streaming applications on the heterogeneous multicore processor. ISCAS 2012: 1335-1338 - 2011
- [j6]Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu:
Complexity-Aware Quantization and Lightweight VLSI Implementation of FIR Filters. EURASIP J. Adv. Signal Process. 2011 (2011) - [j5]Shu-Hsuan Chou, Chien-Chih Chen, Chi-Neng Wen, Tien-Fu Chen, Tay-Jyi Lin:
Hierarchical circuit-switched NoC for multicore video processing. Microprocess. Microsystems 35(2): 182-199 (2011) - [j4]David Chih-Wei Chang, Tay-Jyi Lin, Chung-Ju Wu, Jenq Kuen Lee, Yuan-Hua Chu, An-Yeu Wu:
Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools. J. Signal Process. Syst. 62(3): 373-382 (2011) - 2010
- [j3]Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chih-Wei Liu:
Design and Implementation of Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1684-1696 (2010) - [c29]Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Tay-Jyi Lin:
RunAssert: A non-intrusive run-time assertion for parallel programs debugging. DATE 2010: 287-290 - [c28]Tay-Jyi Lin, Pi-Chen Hsiao, Chi-Hung Lin, Shu-Chang Kuo, Chou-Kun Lin, Yu-Ting Kuo, Chih-Wei Liu, Yuan-Hua Chu:
Collaborative voltage scaling with online STA and variable-latency datapath. ACM Great Lakes Symposium on VLSI 2010: 347-352 - [c27]Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang:
Hierarchical memory scheduling for multimedia MPSoCs. ICCAD 2010: 190-196 - [c26]Kuo-Chiang Chang, Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu:
Complexity-effective dynamic range compression for digital hearing aids. ISCAS 2010: 2378-2381 - [c25]Shih-Hao Ou, Yen-Cheng Lin, Tay-Jyi Lin, Chih-Wei Liu:
Improving energy efficiency of functional units by exploiting their data-dependent latency. ISCAS 2010: 4165-4168
2000 – 2009
- 2009
- [c24]Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chou-Kun Lin, Chih-Wei Liu:
Ultra low-power ANSI S1.11 filter bank for digital hearing aids. ASP-DAC 2009: 115-116 - [c23]Shin-Kai Chen, Tay-Jyi Lin, Chih-Wei Liu:
Parallel object detection on multicore platforms. SiPS 2009: 075-080 - 2008
- [j2]Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao:
Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications. J. Signal Process. Syst. 51(3): 209-223 (2008) - [c22]Shih-Hao Ou, Tay-Jyi Lin, Xiang Sheng Deng, Zhi Hong Zhuo, Chih-Wei Liu:
Multithreaded coprocessor interface for multi-core multimedia SoC. ASP-DAC 2008: 115-116 - [c21]Jwo-An Lin, Yung-Chou Tsai, Tay-Jyi Lin, Yarsun Hsu:
Cycle Stealing and Channel Management for On-Chip Networks. HPCC 2008: 53-60 - [c20]Yu-Ting Kuo, Tay-Jyi Lin, Wei-Han Chang, Yueh-Tai Li, Chih-Wei Liu, Shuenn-Tsong Young:
Complexity-effective auditory compensation for digital hearing aids. ISCAS 2008: 1472-1475 - [c19]Shih-Hao Ou, Yi Cho, Tay-Jyi Lin, Chih-Wei Liu:
Improving datapathutilization of programmable DSP with composite functional units. ISCAS 2008: 3438-3441 - 2007
- [c18]Li-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu:
Single-Issue 1500MIPS Embedded DSP with Ultra Compact Codes. ASP-DAC 2007: 110-111 - [c17]Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Wei-Han Chang, Chih-Wei Liu, Shuenn-Tsong Young:
Design of ANSI S1.11 Filter Bank for Digital Hearing Aids. ICECS 2007: 242-245 - [c16]Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu:
Rapid C to FPGA Prototyping with Multithreaded Emulation Engine. ISCAS 2007: 409-412 - [c15]Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen:
Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. ISCAS 2007: 3506-3509 - 2006
- [j1]Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chih-Wei Jen:
A Compact DSP Core with Static Floating-Point Arithmetic. J. VLSI Signal Process. 42(2): 127-138 (2006) - [c14]Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen:
A 52mW 1200MIPS compact DSP for multi-core media SoC. ASP-DAC 2006: 118-119 - [c13]Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen:
Programmable FIR filter with adder-based computing engine. ISCAS 2006 - 2005
- [c12]Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen:
A unified processor architecture for RISC & VLIW DSP. ACM Great Lakes Symposium on VLSI 2005: 50-55 - [c11]Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen:
Architecture for area-efficient 2-D transform in H.264/AVC. ICME 2005: 1126-1129 - [c10]Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen:
Pipelining technique for energy-aware datapaths. ISCAS (2) 2005: 1218-1221 - [c9]Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen:
Hierarchical instruction encoding for VLIW digital signal processors. ISCAS (4) 2005: 3503-3506 - 2004
- [c8]Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen:
A compact DSP core with static floating-point unit & its microcode generation. ACM Great Lakes Symposium on VLSI 2004: 57-60 - [c7]Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen:
Static floating-point unit with implicit exponent tracking for embedded DSP. ISCAS (2) 2004: 821-824 - 2003
- [c6]Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen:
An Efficient VLIW DSP Architecture for Baseband Processing. ICCD 2003: 307-312 - [c5]Tay-Jyi Lin, Chin-Chi Chang, Tsung-Hsun Yang, Yu-Ming Chang, Chien-Hung Lin, Chen-Chia Lee, Hung-Yueh Lin, Chein-Wei Jen:
Performance evaluation of ring-structure register file in multimedia applications. ICME 2003: 121-124 - [c4]Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen:
Coefficient optimization for area-effective multiplier-less FIR filters. ICME 2003: 125-128 - [c3]Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen:
Area-effective FIR filter design for multiplier-less implementation. ISCAS (5) 2003: 173-176 - 2002
- [c2]Tay-Jyi Lin, Chein-Wei Jen:
CASCADE - configurable and scalable DSP environment. ISCAS (4) 2002: 870-873 - 2001
- [c1]Tay-Jyi Lin, Chein-Wei Jen:
An efficient 2-D DWT architecture via resource cycling. ISCAS (4) 2001: 914-917
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-10 22:15 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
