"A unified processor architecture for RISC & VLIW DSP."

Tay-Jyi Lin et al. (2005)

> Home

Details and statistics

DOI: 10.1145/1057661.1057675

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/LinCLHCLLJ05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/LinCLHCLLJ05
Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen:
A unified processor architecture for RISC & VLIW DSP. ACM Great Lakes Symposium on VLSI 2005: 50-55

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.