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2020 – today
- 2024
[c33]Che-Yu Hsu, Po-Han Chen, Ting-Yi Chen, Shang-Yu Lin, Ching-Jen Wang, Chingwei Yeh, Tay-Jyi Lin, Pei-Zen Chang, Wei-Chang Li:
Performance Evaluation of MEMS Vibration Sensors for Throat Microphones. IEEE SENSORS 2024: 1-4- 2023
- [j24]Tay-Jyi Lin
, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, Jinn-Shyan Wang:
A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN. IEEE Trans. Circuits Syst. II Express Briefs 70(12): 4564-4568 (2023) - [c32]Po-Han Chen, Tay-Jyi Lin, Chingwei Yeh, Pei-Zen Chang, Wei-Chang Li:
Force-Sensing Intelligent Vise for Cutting Dynamics Monitoring in Machining. SENSORS 2023: 1-4 - 2022
- [c31]Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang:
A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients. ASP-DAC 2022: 7-8
2010 – 2019
- 2017
- [c30]Yi-Hsuan Ting, Tay-Jyi Lin, Cheng-Chun Chang, Chih-Chien Hu, Chingwei Yeh, Jinn-Shyan Wang:
Approximate Distributed Arithmetic for Variable-Latency Table Lookup. NGCAS 2017: 137-140 - 2016
- [c29]Chao-Yang Chang, Chung-Hsun Huang, Hui-Fu Chen, Chingwei Yeh, Yuan-Sun Chu, Tay-Jyi Lin:
A low complexity edge-preserved image compression algorithm for LCD overdrive. GCCE 2016: 1-2 - [c28]Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen:
Variable-length VLIW encoding for code size reduction in embedded processors. SoCC 2016: 296-299 - 2014
- [c27]Chingwei Yeh, Chen-Yao Tsai, Tay-Jyi Lin, Jiun-In Guo:
Maintaining color fidelity for dual-shot HDR imaging. ICCE-TW 2014: 65-66 - 2013
- [j23]Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang:
Embedding Repeaters in Silicon IPs for Cross-IP Interconnections. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 597-601 (2013) - [c26]Jian-Shiun Chen, Chingwei Yeh, Jinn-Shyan Wang:
Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS. ISSCC 2013: 426-427 - 2012
- [j22]Chingwei Yeh, Yuan-Chang Chen, Jinn-Shyan Wang:
Towards Process Variation-Aware Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1929-1937 (2012) - [c25]Shyang-Chyun Chen, Chao-Chuan Chen, Wen-Chi Guo, Tay-Jyi Lin, Ching-Wei Yeh:
Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications. ASP-DAC 2012: 473-474 - 2011
- [j21]Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh:
Design of High-Performance CMOS Level Converters Considering PVT Variations. IEICE Trans. Electron. 94-C(5): 913-916 (2011) - [j20]Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh:
Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy. ACM Trans. Archit. Code Optim. 8(3): 16:1-16:27 (2011) - [c24]Jinn-Shyan Wang, Tsung-Han Hsieh, Keng-Jui Chang, Chingwei Yeh:
Low power shift registers for megabits CMOS image sensors. ASICON 2011: 17-20 - [c23]Chingwei Yeh, Yan-Nan Liu, Jinn-Shyan Wang, Pei-Yao Chang:
Variation-resilient voltage generation for SRAM weak cell testing. ASICON 2011: 248-251 - [c22]Jinn-Shyan Wang, Keng-Jui Chang, Shu-Yi Yang, Tsung-Han Hsieh, Chingwei Yeh:
RSCE-aware ultra-low-voltage 40-nm CMOS circuits. ISOCC 2011: 131-134 - 2010
- [j19]Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh:
Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays. IEICE Trans. Electron. 93-C(10): 1540-1543 (2010) - [j18]Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh:
Adaptive Pipeline voltage Scaling in High Performance Microprocessor. J. Circuits Syst. Comput. 19(8): 1817-1834 (2010)
2000 – 2009
- 2008
- [j17]Chao-Ching Wang, Jinn-Shyan Wang, Chingwei Yeh:
High-Speed and Low-Power Design Techniques for TCAM Macros. IEEE J. Solid State Circuits 43(2): 530-540 (2008) - 2007
- [c21]Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh:
Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling. HiPEAC 2007: 105-119 - [c20]Jinn-Shyan Wang, Jian-Shiun Chen, Yi-Ming Wang, Chingwei Yeh:
A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS. ISSCC 2007: 294-604 - 2006
- [j16]Hung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang, Chingwei Yeh:
An AND-type match-line scheme for high-performance energy-efficient content addressable memories. IEEE J. Solid State Circuits 41(5): 1108-1119 (2006) - [j15]Chi-Shong Wang, Chingwei Yeh:
Performance-driven technology mapping with MSG partition and selective gate duplication. ACM Trans. Design Autom. Electr. Syst. 11(4): 953-973 (2006) - [j14]Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh:
Power minimization for dynamic PLAs. IEEE Trans. Very Large Scale Integr. Syst. 14(6): 616-624 (2006) - [c19]De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh:
Timing driven power gating. DAC 2006: 121-124 - [c18]Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang:
An 830mW, 586kbps 1024-bit RSA chip design. DATE Designers' Forum 2006: 24-29 - [c17]Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang:
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications. DATE Designers' Forum 2006: 239-243 - [c16]Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu:
Design of STR level converters for SoCs using the multi-island dual-VDD design technique. ISCAS 2006 - [c15]Jinn-Shyan Wang, Chao-Ching Wang, Chingwei Yeh:
TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines. ISSCC 2006: 577-586 - 2005
- [j13]Jinn-Shyan Wang, Hung-Yu Li, Chingwei Yeh, Tien-Fu Chen:
Design techniques for single-low-VDD CMOS systems. IEEE J. Solid State Circuits 40(5): 1157-1165 (2005) - [j12]Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen:
An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. IEEE Trans. Circuits Syst. Video Technol. 15(5): 704-715 (2005) - [c14]Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh:
Power minimization for dynamic PLAs. ASP-DAC 2005: 1010-1013 - [c13]Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh:
A low-power high-SFDR CMOS direct digital frequency synthesizer. ISCAS (2) 2005: 1670-1673 - 2004
- [j11]Chung-Hsun Huang, Jinn-Shyan Wang, Chingwei Yeh, Chih-Jen Fang:
The CMOS carry-forward adders. IEEE J. Solid State Circuits 39(2): 327-336 (2004) - [c12]Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh:
A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding. ICME 2004: 1683-1686 - [c11]Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen:
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms. ISCAS (2) 2004: 141-144 - [c10]Jinn-Shyan Wang, Shang-Jyh Shieh, Ching-Wei Yeh, Yuan-Hsun Yeh:
Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs. ISCAS (2) 2004: 401-404 - 2001
- [j10]Jinn-Shyan Wang, Ching-Rong Chang, Chingwei Yeh:
Analysis and design of high-speed and low-power CMOS PLAs. IEEE J. Solid State Circuits 36(8): 1250-1262 (2001) - [j9]Wen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, Sunil R. Das:
An adaptive path selection method for delay testing. IEEE Trans. Instrum. Meas. 50(5): 1109-1118 (2001) - [j8]Chingwei Yeh, Yin-Shuin Kang:
Cell-based layout techniques supporting gate-level voltage scaling for low power. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 983-986 (2001) - 2000
- [j7]Chingwei Yeh, Yin-Shuin Kang:
Cell-based layout techniques supporting gate-level voltage scaling for low power. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 629-633 (2000)
1990 – 1999
- 1999
- [c9]Ching-Wei Yeh, Min-Cheng Chang, Yin-Shuin Kang:
Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs. ARVLSI 1999: 155-169 - [c8]Ching-Wei Yeh, Chin-Chao Chang, Jinn-Shyan Wang:
Technnology Mapping for Low Power. ASP-DAC 1999: 145-148 - [c7]Ching-Wei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang:
Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs. DAC 1999: 62-67 - [c6]Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone:
Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. DAC 1999: 68-71 - [c5]Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone:
Power reduction through iterative gate sizing and voltage scaling. ISCAS (1) 1999: 246-249 - [c4]Chingwei Yeh, Yin-Shuin Kang:
A simulated annealing based method supporting dual supply voltages in standard cell placement. ISCAS (1) 1999: 310-313 - [c3]Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang:
A cell selection strategy for low power applications. ISCAS (6) 1999: 416-419 - 1996
- [j6]Chingwei Yeh, Chi-Shong Wang:
On the integration of partitioning and global routing for rectilinear placement problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1): 83-91 (1996) - 1995
- [j5]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimization by iterative improvement: an experimental evaluation on two-way partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 145-153 (1995) - [j4]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Circuit clustering using a stochastic flow injection method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 154-162 (1995) - [j3]Ching-Wei Yeh:
On the acceleration of flow-oriented circuit clustering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(10): 1305-1308 (1995) - 1994
- [j2]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
A general purpose, multiple-way partitioning algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12): 1480-1488 (1994) - [j1]Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel:
Block-oriented programmable design with switching network interconnect. IEEE Trans. Very Large Scale Integr. Syst. 2(1): 45-53 (1994) - 1992
- [c2]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
A probabilistic multicommodity-flow solution to circuit clustering problems. ICCAD 1992: 428-431 - 1991
- [c1]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
A General Purpose Multiple Way Partitioning Algorithm. DAC 1991: 421-426
Coauthor Index
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