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2020 – today
- 2021
[j4]Chen-Fu Chien
, Chia-Cheng Chen:
Adaptive parametric yield enhancement via collinear multivariate analytics for semiconductor intelligent manufacturing. Appl. Soft Comput. 108: 107385 (2021)
2010 – 2019
- 2017
- [c4]Chen-Fu Chien, Peng-Chieh Lee, Runliang Dou, Ying-Jen Chen, Chia-Cheng Chen:
Modeling collinear WATs for parametric yield enhancement in semiconductor manufacturing. CASE 2017: 739-743 - 2014
- [c3]Ching-Wei Wu, Ming-Hung Chang, Chia-Cheng Chen, Robin Lee, Hung-Jen Liao, Jonathan Chang:
A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS. A-SSCC 2014: 145-148 - 2013
- [j3]Chia-Cheng Chen, Huiman X. Barnhart:
Assessing agreement with intraclass correlation coefficient and concordance correlation coefficient for data with repeated measures. Comput. Stat. Data Anal. 60: 132-145 (2013) - [c2]Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih:
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. ISCAS 2013: 1468-1471 - 2012
- [c1]Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang:
A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. ISLPED 2012: 79-84
2000 – 2009
- 2008
- [j2]Chia-Cheng Chen, Huiman X. Barnhart:
Comparison of ICC and CCC for assessing agreement for data without and with replications. Comput. Stat. Data Anal. 53(2): 554-564 (2008) - 2006
- [j1]Hung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang, Chingwei Yeh:
An AND-type match-line scheme for high-performance energy-efficient content addressable memories. IEEE J. Solid State Circuits 41(5): 1108-1119 (2006)
Coauthor Index
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