"A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line ..."

Chi-Shin Chang et al. (2013)

> Home

Details and statistics

DOI: 10.1109/ISCAS.2013.6572134

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iscas/ChangYLLLCCHJTHHKCWWLCS13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iscas/ChangYLLLCCHJTHHKCWWLCS13
Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih:
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. ISCAS 2013: 1468-1471

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.