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ORCIDChung-Kuan Cheng
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- affiliation: University of California, San Diego, USA
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2020 – today
- 2024
[i12]Chester Holtz, Yucheng Wang, Chung-Kuan Cheng, Bill Lin:
On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbations. CoRR abs/2403.00103 (2024)- 2023
- [j94]Chung-Kuan Cheng
, Chester Holtz, Andrew B. Kahng, Bill Lin, Uday Mallappa:
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs. ACM Trans. Design Autom. Electr. Syst. 28(4): 52:1-52:31 (2023) - [c205]Pengwen Chen, Chung-Kuan Cheng, Albert Chern, Chester Holtz, Aoxi Li, Yucheng Wang:
Placement Initialization via Sequential Subspace Optimization with Sphere Constraints. ISPD 2023: 133-140 - [c204]Chung-Kuan Cheng, Andrew B. Kahng, Sayak Kundu, Yucheng Wang, Zhiang Wang:
Assessment of Reinforcement Learning for Macro Placement. ISPD 2023: 158-166 - [c203]Chung-Kuan Cheng, Andrew B. Kahng, Bill Lin, Yucheng Wang, Dooseok Yoon:
Gear-Ratio-Aware Standard Cell Layout Framework for DTCO Exploration. SLIP 2023: 2:1-2:10 - [c202]Chung-Kuan Cheng, Bill Lin, Byeonggon Kang, Yucheng Wang:
Invited Paper: The Scope and Challenges of Scaling in Advanced Technologies. SLIP 2023: 6:1-6:8 - [i11]Chung-Kuan Cheng, Andrew B. Kahng, Sayak Kundu, Yucheng Wang, Zhiang Wang:
Assessment of Reinforcement Learning for Macro Placement. CoRR abs/2302.11014 (2023) - [i10]Kuan-Jung Chiang, Steven Dong, Chung-Kuan Cheng, Tzyy-Ping Jung:
Using EEG Signals to Assess Workload during Memory Retrieval in a Real-world Scenario. CoRR abs/2305.08044 (2023) - [i9]Chester Holtz, Pengwen Chen, Alexander Cloninger, Chung-Kuan Cheng, Gal Mishne:
Semi-Supervised Laplacian Learning on Stiefel Manifolds. CoRR abs/2308.00142 (2023) - 2022
- [j93]Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin:
Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform. IEEE Access 10: 65971-65981 (2022) - [j92]Uday Mallappa, Chung-Kuan Cheng, Bill Lin:
JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation. IEEE Des. Test 39(6): 16-27 (2022) - [j91]Uday Mallappa, Chung-Kuan Cheng, Bill Lin:
Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation. IEEE Embed. Syst. Lett. 14(4): 175-178 (2022) - [j90]Daeyeal Lee, Bill Lin, Chung-Kuan Cheng:
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing. ACM Trans. Archit. Code Optim. 19(1): 5:1-5:21 (2022) - [j89]Chung-Kuan Cheng, Andrew B. Kahng, Hayoung Kim, Minsoo Kim, Daeyeal Lee, Dongwon Park, Mingyu Woo:
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1495-1508 (2022) - [j88]Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Daeyeal Lee, Bill Lin:
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis. IEEE Trans. Very Large Scale Integr. Syst. 30(8): 1059-1072 (2022) - [c201]Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz:
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. ASP-DAC 2022: 288-293 - [c200]Pengwen Chen, Chung-Kuan Cheng, Albert Chern, Chester Holtz, Aoxi Li, Yucheng Wang:
Placement initialization via a projected eigenvector algorithm: late breaking results. DAC 2022: 1398-1399 - [i8]Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz:
Net Separation-Oriented Printed Circuit Board Placement via Margin Maximization. CoRR abs/2210.14259 (2022) - 2021
- [j87]Daeyeal Lee, Bill Lin, Chung-Kuan Cheng:
SMT-Based Contention-Free Task Mapping and Scheduling on SMART NoC. IEEE Embed. Syst. Lett. 13(4): 158-161 (2021) - [j86]Pengwen Chen, Chung-Kuan Cheng, Xinyuan Wang:
Arnoldi Algorithms with Structured Orthogonalization. SIAM J. Numer. Anal. 59(1): 370-400 (2021) - [j85]He-Teng Zhang, Masahiro Fujita, Chung-Kuan Cheng, Jie-Hong R. Jiang:
SAT-Based On-Track Bus Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 735-747 (2021) - [j84]Daeyeal Lee, Dongwon Park, Chia-Tung Ho, Ilgweon Kang, Hayoung Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng:
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2142-2155 (2021) - [j83]Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin, Dongwon Park:
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1178-1191 (2021) - [c199]Ting-Chou Lin, Devon J. Merrill, Yen-Yi Wu, Chester Holtz, Chung-Kuan Cheng:
A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs. ASP-DAC 2021: 170-175 - [c198]Uday Mallappa, Chung-Kuan Cheng:
GRA-LPO: Graph Convolution Based Leakage Power Optimization. ASP-DAC 2021: 697-702 - [c197]Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Minsoo Kim, Daeyeal Lee, Bill Lin, Dongwon Park, Mingyu Woo:
CoRe-ECO: Concurrent Refinement of Detailed Place-and-Route for an Efficient ECO Automation. ICCD 2021: 366-373 - [c196]Chung-Kuan Cheng, Chia-Tung Ho, Chester Holtz, Bill Lin:
Design and System Technology Co-Optimization Sensitivity Prediction for VLSI Technology Development using Machine Learning. SLIP 2021: 8-15 - 2020
- [j82]Eric Chang, Chung-Kuan Cheng, Anushka Gupta, Po-Ya Hsu, Amanda Moffitt, Alissa Ren, Irene Tsaur, Samuel Wang:
Empirical study on sufficient numbers of minimum cuts in strongly connected directed random graphs. Networks 76(1): 106-121 (2020) - [j81]Xinyuan Wang, Pengwen Chen, Chung-Kuan Cheng:
Stability and Convergency Exploration of Matrix Exponential Integration on Power Delivery Network Transient Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2735-2748 (2020) - [j80]Dongwon Park, Daeyeal Lee, Ilgweon Kang, Chester Holtz, Sicun Gao, Bill Lin, Chung-Kuan Cheng:
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5097-5110 (2020) - [c195]Dongwon Park, Daeyeal Lee, Ilgweon Kang, Sicun Gao, Bill Lin, Chung-Kuan Cheng:
SP&R: Simultaneous Placement and Routing framework for standard cell synthesis in sub-7nm. ASP-DAC 2020: 345-350 - [c194]Po-Ya Hsu, Chung-Kuan Cheng:
Arrhythmia Classification using Deep Learning and Machine Learning with Features Extracted from Waveform-based Signal Processing. EMBC 2020: 292-295 - [c193]Po-Ya Hsu, Chung-Kuan Cheng:
R-peak Detection Using a Hybrid of Gaussian and Threshold Sensitivity. EMBC 2020: 4470-4474 - [c192]Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Dongwon Park:
A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT. ICCAD 2020: 158:1-158:8 - [c191]Chung-Kuan Cheng, Daeyeal Lee, Dongwon Park:
Standard-Cell Scaling Framework with Guaranteed Pin-Accessibility. ISCAS 2020: 1-5 - [i7]Pengwen Chen, Chung-Kuan Cheng, Xinyuan Wang:
Arnoldi algorithms with structured orthogonalization. CoRR abs/2005.14468 (2020)
2010 – 2019
- 2019
- [j79]Chung-Kuan Cheng, Andrew B. Kahng, Ilgweon Kang, Lutong Wang:
RePlAce: Advancing Solution Quality and Routability Validation in Global Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1717-1730 (2019) - [j78]Ilgweon Kang, Fang Qiao, Dongwon Park, Daniel Kane, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham:
Three-dimensional Floorplan Representations by Using Corner Links and Partial Order. ACM Trans. Design Autom. Electr. Syst. 24(1): 13:1-13:33 (2019) - [c190]Eric Chang, Chung-Kuan Cheng, Anushka Gupta, Po-Han Hsu, Po-Ya Hsu, Hsin-Li Liu, Amanda Moffitt, Alissa Ren, Irene Tsaur, Samuel Wang:
Cuff-Less Blood Pressure Monitoring with a 3-Axis Accelerometer. EMBC 2019: 6834-6837 - [c189]Dongwon Park, Ilgweon Kang, Yeseong Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng:
ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques. ISPD 2019: 65-72 - 2018
- [c188]Ilgweon Kang, Dongwon Park, Changho Han, Chung-Kuan Cheng:
Fast and precise routability analysis with conditional design rules. SLIP@DAC 2018: 4:1-4:8 - [c187]Po-Ya Hsu, Chun-Han Yao, Yuwei Wang, Chung-Kuan Cheng:
Adaptive sensitivity analysis with nonlinear power load modeling. SLIP@DAC 2018: 5:1-5:6 - [c186]Pengwen Chen, Chung-Kuan Cheng, Dongwon Park, Xinyuan Wang:
Transient circuit simulation for differential algebraic systems using matrix exponential. ICCAD 2018: 99 - [c185]Chung-Kuan Cheng, Ronald L. Graham, Ilgweon Kang, Dongwon Park, Xinyuan Wang:
Tree Structures and Algorithms for Physical Design. ISPD 2018: 120-125 - [c184]Chung-Kuan Cheng, T. C. Hu, Andrew B. Kahng:
Theory and Algorithms of Physical Design. ISPD 2018: 130-131 - 2017
- [c183]Xinyuan Wang, Hao Zhuang, Chung-Kuan Cheng:
Exploring the exponential integrators with Krylov subspace algorithms for nonlinear circuit simulation. ICCAD 2017: 163-168 - [c182]Ilgweon Kang, Chung-Kuan Cheng:
Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond. ISPD 2017: 123-128 - 2016
- [j77]Quan Chen, Wim Schoenmaker, Shih-Hung Weng, Chung-Kuan Cheng, Guan-Hua Chen, Lijun Jiang, Ngai Wong:
A fast time-domain EM-TCAD coupled simulation framework via matrix exponential with stiffness reduction. Int. J. Circuit Theory Appl. 44(4): 833-850 (2016) - [j76]Qinggao Mei, Wim Schoenmaker, Shih-Hung Weng, Hao Zhuang, Chung-Kuan Cheng, Quan Chen:
An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 832-843 (2016) - [j75]Hao Zhuang, Wenjian Yu, Shih-Hung Weng, Ilgweon Kang, Jeng-Hau Lin, Xiang Zhang, Ryan Coutts, Chung-Kuan Cheng:
Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1681-1694 (2016) - [c181]Fang Qiao, Ilgweon Kang, Daniel Kane, Fung Yu Young, Chung-Kuan Cheng, Ronald L. Graham:
3D floorplan representations: Corner links and partial order. 3DIC 2016: 1-5 - [c180]Jingwei Lu, Hao Zhuang, Ilgweon Kang, Pengwen Chen, Chung-Kuan Cheng:
ePlace-3D: Electrostatics based Placement for 3D-ICs. ISPD 2016: 11-18 - 2015
- [j74]Jingwei Lu, Hao Zhuang, Pengwen Chen, Hongliang Chang, Chin-Chih Chang, Yiu-Chung Wong, Lu Sha, Dennis J.-H. Huang, Yufeng Luo, Chin-Chi Teng, Chung-Kuan Cheng:
ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 685-698 (2015) - [j73]Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng:
ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method. ACM Trans. Design Autom. Electr. Syst. 20(2): 17:1-17:34 (2015) - [c179]Jeng-Hau Lin, Hao Liu, Chia-Hung Liu, Phillip Lam, Gung-Yu Pan, Hao Zhuang, Ilgweon Kang, Patrick P. Mercier, Chung-Kuan Cheng:
An interdigitated non-contact ECG electrode for impedance compensation and signal restoration. BioCAS 2015: 1-4 - [c178]Hao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, Chung-Kuan Cheng:
An algorithmic framework for efficient large-scale circuit simulation using exponential integrators. DAC 2015: 163:1-163:6 - [c177]Yu-Te Wang, Masaki Nakanishi, Simon Lind Kappel, Preben Kidmose, Danilo P. Mandic, Yijun Wang, Chung-Kuan Cheng, Tzyy-Ping Jung:
Developing an online steady-state visual evoked potential-based brain-computer interface system using EarEEG. EMBC 2015: 2271-2274 - [c176]Xiang Zhang, Yang Liu, Ryan Coutts, Chung-Kuan Cheng:
Power line communication for hybrid power/signal pin SOC design. SLIP 2015: 1-8 - [i6]Hao Zhuang, Wenjian Yu, Shih-Hung Weng, Ilgweon Kang, Jeng-Hau Lin, Xiang Zhang, Ryan Coutts, Jingwei Lu, Chung-Kuan Cheng:
Simulation Algorithms with Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks. CoRR abs/1505.06699 (2015) - [i5]Hao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, Chung-Kuan Cheng:
An Algorithmic Framework for Efficient Large-Scale Circuit Simulation Using Exponential Integrators. CoRR abs/1511.04515 (2015) - [i4]Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng:
MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks. CoRR abs/1511.04519 (2015) - [i3]Jingwei Lu, Hao Zhuang, Ilgweon Kang, Pengwen Chen, Chung-Kuan Cheng:
ePlace-3D: Electrostatics based Placement for 3D-ICs. CoRR abs/1512.08291 (2015) - 2014
- [j72]Xiang Hu, Peng Du, Shih-Hung Weng, Chung-Kuan Cheng:
Worst Case Noise Prediction With Nonzero Current Transition Times for Power Grid Planning. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 607-620 (2014) - [j71]Shih-Hung Weng, Yulei Zhang, James F. Buckwalter, Chung-Kuan Cheng:
Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 938-942 (2014) - [c175]Hao Zhuang, Shih-Hung Weng, Jeng-Hau Lin, Chung-Kuan Cheng:
MATEX: A Distributed Framework for Transient Simulation of Power Distribution Networks. DAC 2014: 81:1-81:6 - [c174]Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis J.-H. Huang, Chin-Chi Teng, Chung-Kuan Cheng:
ePlace: Electrostatics Based Placement Using Nesterov's Method. DAC 2014: 121:1-121:6 - [c173]Xiang Zhang, Jingwei Lu, Yang Liu, Chung-Kuan Cheng:
Worst-case noise area prediciton of on-chip power distribution network. SLIP 2014: 2:1-2:8 - 2013
- [j70]Xiang Hu, Peng Du, James F. Buckwalter, Chung-Kuan Cheng:
Modeling and Analysis of Power Distribution Networks in 3-D ICs. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 354-366 (2013) - [c172]Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng:
FFTPL: An analytic placement algorithm using fast fourier transform for density equalization. ASICON 2013: 1-4 - [c171]Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng:
Power grid simulation using matrix exponential method with rational Krylov subspaces. ASICON 2013: 1-4 - [c170]Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang, Chung-Kuan Cheng:
Layer minimization in escape routing for staggered-pin-array PCBs. ASP-DAC 2013: 187-192 - [c169]Liya Huang, Xiaoxia Huang, Yu-Te Wang, Yijun Wang, Tzyy-Ping Jung, Chung-Kuan Cheng:
Empirical mode decomposition improves detection of SSVEP. EMBC 2013: 3901-3904 - [c168]Yu-Te Wang, Yijun Wang, Chung-Kuan Cheng, Tzyy-Ping Jung:
Developing stimulus presentation on mobile devices for a truly portable SSVEP-based BCI. EMBC 2013: 5271-5274 - [c167]Xiang Zhang, Yang Liu, Chung-Kuan Cheng:
Worst-case noise prediction using power network impedance profile. SLIP 2013: 1-8 - [i2]Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng:
Power Grid Simulation using Matrix Exponential Method with Rational Krylov Subspaces. CoRR abs/1309.5333 (2013) - [i1]Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng:
FFTPL: An Analytic Placement Algorithm Using Fast Fourier Transform for Density Equalization. CoRR abs/1312.4587 (2013) - 2012
- [j69]Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong:
A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(1): 109-120 (2012) - [j68]Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Grantham K. H. Pang, Ngai Wong:
Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3): 452 (2012) - [j67]Quan Chen, Shih-Hung Weng, Chung-Kuan Cheng:
A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(7): 1031-1040 (2012) - [j66]Shih-Hung Weng, Quan Chen, Chung-Kuan Cheng:
Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(8): 1180-1193 (2012) - [c166]Peng Du, Wenbo Zhao, Shih-Hung Weng, Chung-Kuan Cheng, Ronald L. Graham:
Character design and stamp algorithms for Character Projection Electron-Beam Lithography. ASP-DAC 2012: 725-730 - [c165]Yu-Te Wang, Chung-Kuan Cheng, Kuan-Chih Huang, Chin-Teng Lin, Yijun Wang, Tzyy-Ping Jung:
Cell-phone based Drowsiness Monitoring and Management system. BioCAS 2012: 200-203 - [c164]Yu-Te Wang, Yijun Wang, Chung-Kuan Cheng, Tzyy-Ping Jung:
Measuring Steady-State Visual Evoked Potentials from non-hair-bearing areas. EMBC 2012: 1806-1809 - [c163]Shih-Hung Weng, Quan Chen, Ngai Wong, Chung-Kuan Cheng:
Circuit simulation via matrix exponential method for stiffness handling and parallel processing. ICCAD 2012: 407-414 - [c162]Quan Chen, Wim Schoenmaker, Shih-Hung Weng, Chung-Kuan Cheng, Guan-Hua Chen, Lijun Jiang, Ngai Wong:
A fast time-domain EM-TCAD coupled simulation framework via matrix exponential. ICCAD 2012: 422-428 - [c161]Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-Hung Weng:
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph. ISPD 2012: 105-112 - [c160]Ying-Chi Li, Quan Chen, Shih-Hung Weng, Chung-Kuan Cheng, Ngai Wong:
Globally stable, highly parallelizable fast transient circuit simulation via faber series. NEWCAS 2012: 177-180 - [c159]Guang Sun, Shih-Hung Weng, Chung-Kuan Cheng, Bill Lin, Lieguang Zeng:
An on-chip global broadcast network design with equalized transmission lines in the 1024-core era. SLIP 2012: 11-18 - 2011
- [j65]Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham:
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 167-179 (2011) - [j64]Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng:
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 520-524 (2011) - [j63]Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin, James F. Buckwalter, Chung-Kuan Cheng:
Prediction and Comparison of High-Performance On-Chip Global Interconnection. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1154-1166 (2011) - [c158]Peng Du, Shih-Hung Weng, Xiang Hu, Chung-Kuan Cheng:
Power grid sizing via convex programming. ASICON 2011: 337-340 - [c157]Shih-Hung Weng, Quan Chen, Chung-Kuan Cheng:
Circuit simulation using matrix exponential method. ASICON 2011: 369-372 - [c156]Amirali Shayan Arani, Xiang Hu, Chung-Kuan Cheng, Wenjian Yu, Christopher Pan:
Linear Dropout Regulator based power distribution design under worst loading. ASICON 2011: 539-542 - [c155]Xiang Hu, Peng Du, Chung-Kuan Cheng:
Exploring 3D power distribution network physics. ASICON 2011: 562-565 - [c154]Zheng Zhang, Xiang Hu, Chung-Kuan Cheng, Ngai Wong:
A block-diagonal structured model reduction scheme for power grid networks. DATE 2011: 44-49 - [c153]Shih-Hung Weng, Peng Du, Chung-Kuan Cheng:
A fast and stable explicit integration method by matrix exponential operator for large scale circuit simulation. ISCAS 2011: 1467-1470 - [c152]Chung-Kuan Cheng:
Placement and beyond in honor of Ernest S. Kuh. ISPD 2011: 5-8 - [c151]Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Grantham K. H. Pang, Yuanzhe Wang, Ngai Wong:
More realistic power grid verification based on hierarchical current and power constraints. ISPD 2011: 159-166 - 2010
- [j62]Shan Zeng, Wenjian Yu, Xianlong Hong, Chung-Kuan Cheng:
Efficient Power Network Analysis with Modeling of Inductive Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(6): 1196-1203 (2010) - [j61]Renshen Wang, Evangeline F. Y. Young, Chung-Kuan Cheng:
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness. ACM Trans. Design Autom. Electr. Syst. 15(4): 33:1-33:22 (2010) - [c150]Xiang Hu, Thomas Toms, Riko Radojcic, Matt Nowak, Nick Yu, Chung-Kuan Cheng:
Enabling power distribution network analysis flows for 3D ICs. 3DIC 2010: 1-4 - [c149]Wanping Zhang, Ling Zhang, Amirali Shayan Arani, Wenjian Yu, Xiang Hu, Zhi Zhu, A. Ege Engin, Chung-Kuan Cheng:
On-chip power network optimization with decoupling capacitors and controlled-ESRs. ASP-DAC 2010: 119-124 - [c148]Xiang Hu, Wenbo Zhao, Peng Du, Amirali Shayan Arani, Chung-Kuan Cheng:
An adaptive parallel flow for power distribution network simulation using discrete Fourier transform. ASP-DAC 2010: 125-130 - [c147]Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng:
Bus via reduction based on floorplan revising. ACM Great Lakes Symposium on VLSI 2010: 9-14 - [c146]Renshen Wang, Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng:
Physical synthesis of bus matrix for high bandwidth low power on-chip communications. ISPD 2010: 91-96 - [c145]Peng Du, Xiang Hu, Shih-Hung Weng, Amirali Shayan Arani, Xiaoming Chen, A. Ege Engin, Chung-Kuan Cheng:
Worst-case noise prediction with non-zero current transition times for early power distribution system verification. ISQED 2010: 624-631 - [c144]Yulei Zhang, James F. Buckwalter, Chung-Kuan Cheng:
Performance prediction of throughput-centric pipelined global interconnects with voltage scaling. SLIP 2010: 69-76 - [c143]Chung-Kuan Cheng, Andrew B. Kahng, Kambiz Samadi, Amirali Shayan Arani:
Worst-case performance prediction under supply voltage and temperature variation. SLIP 2010: 91-96
2000 – 2009
- 2009
- [j60]Wenjian Yu, Rui Shi, Chung-Kuan Cheng:
Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design. IEICE Trans. Electron. 92-C(4): 444-452 (2009) - [j59]Shan Zeng, Wenjian Yu, Jin Shi, Xianlong Hong, Chung-Kuan Cheng:
Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6): 1476-1484 (2009) - [j58]Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng:
Efficient Power Network Analysis Considering Multidomain Clock Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1348-1358 (2009) - [j57]Yi Zhu, Thomas Weng, Chung-Kuan Cheng:
Enhancing Learning Effectiveness in Digital Design Courses Through the Use of Programmable Logic Boards. IEEE Trans. Educ. 52(1): 151-156 (2009) - [j56]Yi Zhu, Yuanfang Hu, Michael B. Taylor, Chung-Kuan Cheng:
Energy and switch area optimizations for FPGA global routing architectures. ACM Trans. Design Autom. Electr. Syst. 14(1): 13:1-13:25 (2009) - [c142]Chung-Kuan Cheng:
Design Space Exploration for Power-Efficient Mixed-Radix Ling Adders. IEEE Symposium on Computer Arithmetic 2009: 212 - [c141]Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng:
High performance on-chip differential signaling using passive compensation for global communication. ASP-DAC 2009: 385-390 - [c140]Wanping Zhang, Yi Zhu, Wenjian Yu, Amirali Shayan Arani, Renshen Wang, Zhi Zhu, Chung-Kuan Cheng:
Noise minimization during power-up stage for a multi-domain power network. ASP-DAC 2009: 391-396 - [c139]He Peng, Chung-Kuan Cheng:
Parallel transistor level circuit simulation using domain decomposition methods. ASP-DAC 2009: 397-402 - [c138]Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng:
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications. DAC 2009: 166-171 - [c137]Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kuan Cheng, Wenjian Yu, Mikhail Popovich, Thomas Toms, Xiaoming Chen:
Reliability aware through silicon via planning for 3D stacked ICs. DATE 2009: 288-291 - [c136]He Peng, Chung-Kuan Cheng:
Parallel transistor level full-chip circuit simulation. DATE 2009: 304-307 - [c135]Renshen Wang, Chung-Kuan Cheng:
Octilinear redistributive routing in bump arrays. ACM Great Lakes Symposium on VLSI 2009: 191-196 - [c134]Renshen Wang, Chung-Kuan Cheng:
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design. ACM Great Lakes Symposium on VLSI 2009: 257-262 - [c133]Renshen Wang, Takumi Okamoto, Chung-Kuan Cheng:
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations. ICCD 2009: 23-28 - [c132]Amirali Shayan Arani, Xiang Hu, Wanping Zhang, Chung-Kuan Cheng, A. Ege Engin, Xiaoming Chen, Mikhail Popovich:
3D stacked power distribution considering substrate coupling. ICCD 2009: 225-230 - [c131]Yulei Zhang, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng:
Design methodology of high performance on-chip global interconnect using terminated transmission-line. ISQED 2009: 451-458 - [c130]Amirali Shayan Arani, Xiang Hu, He Peng, Wenjian Yu, Wanping Zhang, Chung-Kuan Cheng, Mikhail Popovich, Xiaoming Chen, Lew Chua-Eoan, Xiaohua Kong:
Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network. ISQED 2009: 576-581 - [c129]Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng:
Efficient power network analysis with complete inductive modeling. ISQED 2009: 770-775 - [c128]Yulei Zhang, Xiang Hu, Alina Deutsch, A. Ege Engin, James F. Buckwalter, Chung-Kuan Cheng:
Prediction of high-performance on-chip global interconnection. SLIP 2009: 61-68 - [c127]Xiang Hu, Wenbo Zhao, Peng Du, Yulei Zhang, Amirali Shayan Arani, Christopher Pan, A. Ege Engin, Chung-Kuan Cheng:
On the bound of time-domain power supply noise based on frequency-domain target impedance. SLIP 2009: 69-76 - [c126]Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng:
Predicting the worst-case voltage violation in a 3D power network. SLIP 2009: 93-98 - [e1]Chung-Kuan Cheng, Sherief Reda:
The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings. ACM 2009, ISBN 978-1-60558-576-5 [contents] - 2008
- [j55]Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng:
Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3474-3480 (2008) - [j54]Yi Zhu, Amirali Shayan Arani, Wanping Zhang, Tong Lee Chen, Tzyy-Ping Jung, Jeng-Ren Duann, Scott Makeig, Chung-Kuan Cheng:
Analyzing High-Density ECG Signals Using ICA. IEEE Trans. Biomed. Eng. 55(11): 2528-2537 (2008) - [c125]Yi Zhu, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng:
Timing-power optimization for mixed-radix Ling adders by integer linear programming. ASP-DAC 2008: 131-137 - [c124]Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto:
High performance current-mode differential logic. ASP-DAC 2008: 720-725 - [c123]Ling Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng:
Low power passive equalizer optimization using tritonic step response. DAC 2008: 570-573 - [c122]Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng:
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. DATE 2008: 537-540 - [c121]Ling Zhang, Wenjian Yu, Yulei Zhang, Renshen Wang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng:
Low Power Passive Equalizer Design for Computer Memory Links. Hot Interconnects 2008: 51-56 - [c120]Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng:
A novel fixed-outline floorplanner with zero deadspace for hierarchical design. ICCAD 2008: 16-23 - [c119]Yi Zhu, Michael B. Taylor, Scott B. Baden, Chung-Kuan Cheng:
Advancing supercomputer performance through interconnection topology synthesis. ICCAD 2008: 555-558 - [c118]Rui Shi, Wenjian Yu, Yi Zhu, Chung-Kuan Cheng, Ernest S. Kuh:
Efficient and accurate eye diagram prediction for high speed signaling. ICCAD 2008: 655-661 - [c117]Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng:
On-chip high performance signaling using passive compensation. ICCD 2008: 182-187 - [c116]Renshen Wang, Evangeline F. Y. Young, Yi Zhu, Fan Chung Graham, Ronald L. Graham, Chung-Kuan Cheng:
3-D floorplanning using labeled tree and dual sequences. ISPD 2008: 54-59 - [c115]Ling Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang, Chung-Kuan Cheng:
Clock Skew Analysis via Vector Fitting in Frequency Domain. ISQED 2008: 476-479 - 2007
- [j53]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 645-658 (2007) - [j52]Zhengyong Zhu, He Peng, Chung-Kuan Cheng, Khosro Rouz, Manjit Borah, Ernest S. Kuh:
Two-Stage Newton-Raphson Method for Transistor-Level Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 881-895 (2007) - [j51]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng:
Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 959-969 (2007) - [c114]Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis:
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. ASP-DAC 2007: 609-615 - [c113]Haikun Zhu, Yi Zhu, Chung-Kuan Cheng, David M. Harris:
An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization. ASP-DAC 2007: 616-621 - [c112]Haikun Zhu, Rui Shi, Chung-Kuan Cheng, Hongyu Chen:
Approaching Speed-of-light Distortionless Communication for On-chip Interconnect. ASP-DAC 2007: 684-689 - [c111]Amirali Shayan Arani, Yi Zhu, Yi-Ning Cheng, Chung-Kuan Cheng, Shien-Fong Lin, Peng-Sheng Chen:
Exploring Cardioneural Signals from Noninvasive ECG Measurement. BIBE 2007: 1134-1138 - [c110]Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng:
Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration. CICC 2007: 869-872 - [c109]Yuanfang Hu, Yi Zhu, Michael B. Taylor, Chung-Kuan Cheng:
FPGA global routing architecture optimization using a multicommodity flow approach. ICCD 2007: 144-151 - [c108]Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng:
Fast power network analysis with multiple clock domains. ICCD 2007: 456-463 - [c107]Chun-Chen Liu, Haikun Zhu, Chung-Kuan Cheng:
Passive compensation for high performance inter-chip communication. ICCD 2007: 547-552 - [c106]Wanping Zhang, Chung-Kuan Cheng:
Incremental Power Impedance Optimization Using Vector Fitting Modeling. ISCAS 2007: 2439-2442 - [c105]He Peng, Chung-Kuan Cheng:
Fast Transient Simulation of Lossy Transmission Lines. ISCAS 2007: 2706-2709 - [c104]Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng:
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. ISQED 2007: 251-256 - 2006
- [j50]Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. 21(6): 922-926 (2006) - [j49]Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng:
VLSI Block Placement With Alignment Constraints. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 622-626 (2006) - [j48]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2637-2646 (2006) - [j47]Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham:
On the construction of zero-deficiency parallel prefix circuits with minimum depth. ACM Trans. Design Autom. Electr. Syst. 11(2): 387-409 (2006) - [c103]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton:
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. ASP-DAC 2006: 73-78 - [c102]Zhengyong Zhu, Rui Shi, Chung-Kuan Cheng, Ernest S. Kuh:
An unconditional stable general operator splitting method for transistor level transient analysis. ASP-DAC 2006: 428-433 - [c101]Yi Zhu, Tong Lee Chen, Wanping Zhang, Tzyy-Ping Jung, Jeng-Ren Duann, Scott Makeig, Chung-Kuan Cheng:
Noninvasive Study of the Human Heart using Independent Component Analysis. BIBE 2006: 340-347 - [c100]Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng:
Communication latency aware low power NoC synthesis. DAC 2006: 574-579 - [c99]Rui Shi, Chung-Kuan Cheng:
Efficient escape routing for hexagonal array of high density I/Os. DAC 2006: 1003-1008 - [c98]Jianhua Liu, Michael Chang, Chung-Kuan Cheng:
An iterative division algorithm for FPGAs. FPGA 2006: 83-89 - [c97]Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng:
Timing model reduction for hierarchical timing analysis. ICCAD 2006: 415-422 - [c96]Renshen Wang, Rui Shi, Chung-Kuan Cheng:
Layer minimization of escape routing in area array packaging. ICCAD 2006: 815-819 - [c95]Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Integrating dynamic thermal via planning with 3D floorplanning algorithm. ISPD 2006: 178-185 - 2005
- [j46]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao:
The Y architecture for on-chip interconnect: analysis and methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 588-599 (2005) - [j45]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu:
Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 609-621 (2005) - [c94]Hongyu Chen, Chung-Kuan Cheng:
A multi-level transmission line network approach for multi-giga hertz clock distribution. ASP-DAC 2005: 103-106 - [c93]Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen:
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? ASP-DAC 2005 - [c92]Zhengyong Zhu, Khosro Rouz, Manjit Borah, Chung-Kuan Cheng, Ernest S. Kuh:
Efficient transient simulation for transistor-level analysis. ASP-DAC 2005: 240-243 - [c91]Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham:
Constructing zero-deficiency parallel prefix adder of minimum depth. ASP-DAC 2005: 883-888 - [c90]Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng:
Integrated algorithmic logical and physical design of integer multiplier. ASP-DAC 2005: 1014-1017 - [c89]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris:
Improving the efficiency of static timing analysis with false paths. ICCAD 2005: 527-531 - [c88]Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng:
Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz. ICCD 2005: 111-118 - [c87]Hongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris:
Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications. ICCD 2005: 497-502 - [c86]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) 2005: 1863-1866 - [c85]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng:
VLSI block placement with alignment constraints based on corner block list. ISCAS (6) 2005: 6222-6225 - [c84]Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris:
Unified quadratic programming approach for mixed mode placement. ISPD 2005: 193-199 - [c83]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED 2005: 213-219 - [c82]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng:
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED 2005: 628-633 - 2004
- [j44]Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Corner block list representation and its application with boundary constraints. Sci. China Ser. F Inf. Sci. 47(1): 1-19 (2004) - [j43]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm for chip-level floorplanning. Sci. China Ser. F Inf. Sci. 47(6): 763-776 (2004) - [j42]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu:
Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. 19(6): 973-980 (2004) - [j41]Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen:
Fast postplacement optimization using functional symmetries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 102-118 (2004) - [j40]Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu:
UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3): 358-365 (2004) - [j39]Xiaohai Wu, Xianlong Hong, Yici Cai, Zuying Luo, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai:
Area minimization of power distribution network using efficient nonlinear programming techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1086-1094 (2004) - [j38]Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Corner block list representation and its application to floorplan optimization. IEEE Trans. Circuits Syst. II Express Briefs 51-II(5): 228-233 (2004) - [j37]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. 9(2): 199-211 (2004) - [c81]Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng:
A multiple level network approach for clock skew minimization with process variations. ASP-DAC 2004: 263-268 - [c80]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang:
Optimal planning for mesh-based power distribution. ASP-DAC 2004: 444-449 - [c79]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm with congestion optimization. ASP-DAC 2004: 615-620 - [c78]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Buffer allocation algorithm with consideration of routing congestion. ASP-DAC 2004: 621-623 - [c77]Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris:
Fast adders in modern FPGAs. FPGA 2004: 250 - [r1]Zhou Feng, Bo Yao, Chung-Kuan Cheng:
Floorplan Representation in VLSI. Handbook of Data Structures and Applications 2004 - 2003
- [j36]Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham:
Floorplan representations: Complexity and connections. ACM Trans. Design Autom. Electr. Syst. 8(1): 55-80 (2003) - [c76]Zhanhai Qin, Chung-Kuan Cheng:
RCLK-VJ network reduction with Hurwitz polynomial approximation. ASP-DAC 2003: 283-291 - [c75]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm based on dead space redistribution. ASP-DAC 2003: 435-438 - [c74]Tong Jing, Xianlong Hong, Haiyun Bao, Yici Cai, Jingyu Xu, Chung-Kuan Cheng, Jun Gu:
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing. ASP-DAC 2003: 834-839 - [c73]Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng:
The Y-architecture: yet another on-chip interconnect solution. ASP-DAC 2003: 840-847 - [c72]Zhengyong Zhu, Bo Yao, Chung-Kuan Cheng:
Power network analysis using an adaptive algebraic multigrid approach. DAC 2003: 105-108 - [c71]Zhanhai Qin, Chung-Kuan Cheng:
Realizable parasitic reduction using generalized Y-Delta transformation. DAC 2003: 220-225 - [c70]Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu:
An algebraic multigrid solver for analytical placement with layout based clustering. DAC 2003: 794-799 - [c69]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC 2003: 806-811 - [c68]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao:
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. ICCAD 2003: 13-20 - [c67]Jianhua Liu, Shuo Zhou, Haikun Zhu, Chung-Kuan Cheng:
An Algorithmic Approach for Generic Parallel Adders. ICCAD 2003: 734-740 - [c66]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu:
Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) 2003: 493-496 - [c65]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) 2003: 708-711 - [c64]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
An integrated floorplanning with an efficient buffer planning algorithm. ISPD 2003: 136-142 - [c63]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang:
Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. SLIP 2003: 71-76 - [c62]Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham:
A hierarchical three-way interconnect architecture for hexagonal processors. SLIP 2003: 133-139 - 2002
- [j35]Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai:
An Optimum Placement Search Algorithm Based on Extended Corner Block List. J. Comput. Sci. Technol. 17(6): 699-707 (2002) - [j34]Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt:
Toward better wireload models in the presence of obstacles. IEEE Trans. Very Large Scale Integr. Syst. 10(2): 177-189 (2002) - [c61]Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng:
Physical Planning Of On-Chip Interconnect Architectures. ICCD 2002: 30-35 - [c60]Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham:
Balancing the Interconnect Topology for Arrays of Processors between Cost and Power. ICCD 2002: 180-186 - [c59]Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng:
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction. SLIP 2002: 85-89 - [c58]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. ASP-DAC/VLSI Design 2002: 387-392 - 2001
- [j33]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with abutment constraints based on corner block list. Integr. 31(1): 65-77 (2001) - [j32]Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, Takeshi Yoshimura:
Floorplanning using a tree representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 281-289 (2001) - [c57]Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC 2001: 509-514 - [c56]Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt:
Toward better wireload models in the presence of obstacles. ASP-DAC 2001: 527-532 - [c55]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC 2001: 770-775 - [c54]Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai:
Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. ICCAD 2001: 153-157 - [c53]Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham:
Revisiting floorplan representations. ISPD 2001: 138-143 - [c52]Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
ECBL: an extended corner block list with solution space including optimum placement. ISPD 2001: 150-155 - [c51]Yingxin Pang, Chung-Kuan Cheng, Koen Lampaert, Weize Xie:
Rectilinear block packing using O-tree representation. ISPD 2001: 156-161 - [c50]Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu:
Interconnect implications of growth-based structural models for VLSI circuits. SLIP 2001: 99-106 - 2000
- [j31]Sao-Jie Chen, Chung-Kuan Cheng:
Tutorial on VLSI Partitioning. VLSI Design 11(3): 175-218 (2000) - [c49]Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng:
A new efficient waveform simulation method for RLC interconnect via amplitude and phase approximation. ASP-DAC 2000: 463-468 - [c48]Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska:
Fast post-placement rewiring using easily detectable functional symmetries. DAC 2000: 286-289 - [c47]Yingxin Pang, Florin Balasa, Koen Lampaert, Chung-Kuan Cheng:
Block placement with symmetry constraints based on the O-tree non-slicing representation. DAC 2000: 464-467 - [c46]Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. ICCAD 2000: 8-12 - [c45]Xiaodong Yang, Chung-Kuan Cheng, Walter H. Ku, Robert J. Carragher:
Hurwitz Stable Reduced Order Modelling for RLC Interconnect Trees. ICCAD 2000: 222-228 - [c44]Yingxin Pang, Chung-Kuan Cheng, Takeshi Yoshimura:
An enhanced perturbing algorithm for floorplan design using the O-tree representation. ISPD 2000: 168-173
1990 – 1999
- 1999
- [j30]John Lillis, Chung-Kuan Cheng:
Timing optimization for multisource nets: characterization andoptimal repeater insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 322-331 (1999) - [j29]Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng:
Sequence-pair approach for rectilinear module placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 484-493 (1999) - [j28]Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng:
Empirical Study of Block Placement by Cluster Refinement. VLSI Design 10(1): 71-86 (1999) - [c43]Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arunabha Sen:
A Performance-Driven I/O Pin Routing Algorithm. ASP-DAC 1999: 129-132 - [c42]Pei-Ning Guo, Chung-Kuan Cheng, Takeshi Yoshimura:
An O-Tree Representation of Non-Slicing Floorplan and Its Applications. DAC 1999: 268-273 - [c41]Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng:
RLC interconnect delay estimation via moments of amplitude and phase response. ICCAD 1999: 208-213 - 1998
- [j27]Jianmin Li, Chung-Kuan Cheng:
Routability improvement using dynamic interconnect architecture. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 498-501 (1998) - [c40]Fang-Jou Liu, Chung-Kuan Cheng:
Extending Moment Computation to 2-Port Circuit Representations. DAC 1998: 473-476 - [c39]Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng:
Rectilinear block placement using sequence-pair. ISPD 1998: 173-178 - 1997
- [j26]Xianlong Hong, Tianxiong Xue, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh:
TIGER: an efficient timing-driven global router for gate array and standard cell layout design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1323-1331 (1997) - [c38]Fang-Jou Liu, John Lillis, Chung-Kuan Cheng:
A new layout-driven timing model for incremental layout optimization. ASP-DAC 1997: 127-131 - [c37]Jonathan Dufour, Robert McBride, Ping Zhang, Chung-Kuan Cheng:
A building block placement tool. ASP-DAC 1997: 271-276 - [c36]John Lillis, Chung-Kuan Cheng:
Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion. DAC 1997: 214-219 - [c35]Ming-Ter Kuo, Chung-Kuan Cheng:
A Network Flow Approach for Hierarchical Tree Partitioning. DAC 1997: 512-517 - [c34]Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng:
Cluster Refinement for Block Placement. DAC 1997: 762-765 - 1996
- [j25]John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE J. Solid State Circuits 31(3): 437-447 (1996) - [j24]Robert C. Carden IV, Jianmin Li, Chung-Kuan Cheng:
A global router with a theoretical bound on the optimal solution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2): 208-216 (1996) - [j23]Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng:
Performance driven bus buffer insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(4): 429-437 (1996) - [j22]Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong, Masahiro Fujita, Ramamohan Paturi:
Solving the net matching problem in high-performance chip design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8): 902-911 (1996) - [j21]Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau:
A wire length estimation technique utilizing neighborhood density equations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8): 912-922 (1996) - [c33]Jianmin Li, John Lillis, Lung-Tien Liu, Chung-Kuan Cheng:
New Spectral Linear Placement and Clustering Approach. DAC 1996: 88-93 - [c32]Huoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng:
Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming. DAC 1996: 274-279 - [c31]John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho:
New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing. DAC 1996: 395-400 - [c30]Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng:
Network Partitioning into Tree Hierarchies. DAC 1996: 477-482 - [c29]John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Simultaneous Routing and Buffer Insertion for High Performance Interconnect. Great Lakes Symposium on VLSI 1996: 148-153 - 1995
- [j20]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimization by iterative improvement: an experimental evaluation on two-way partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 145-153 (1995) - [j19]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Circuit clustering using a stochastic flow injection method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 154-162 (1995) - [j18]So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo:
A cell-based hierarchical pitchmatching compaction using minimal LP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(4): 523-526 (1995) - [j17]Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu:
A replication cut for two-way partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5): 623-630 (1995) - [j16]Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof:
Local ratio cut and set covering partitioning for huge logic emulation systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1085-1092 (1995) - [j15]Jiao Fan, D. Zaleta, Chung-Kuan Cheng, S. H. Lee:
Physical models and algorithms for optoelectronic MCM layout. IEEE Trans. Very Large Scale Integr. Syst. 3(1): 124-135 (1995) - [j14]Nan-Chi Chou, Chung-Kuan Cheng:
On general zero-skew clock net construction. IEEE Trans. Very Large Scale Integr. Syst. 3(1): 141-146 (1995) - [c28]Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Performance driven multiple-source bus synthesis using buffer insertion. ASP-DAC 1995 - [c27]Lung-Tien Liu, Ming-Ter Kuo, Chung-Kuan Cheng, T. C. Hu:
Performance-Driven Partitioning Using a Replication Graph Approach. DAC 1995: 206-210 - [c26]Jianmin Li, Chung-Kuan Cheng:
Routability improvement using dynamic interconnect architecture. FCCM 1995: 61-67 - [c25]John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimal wire sizing and buffer insertion for low power and a generalized delay model. ICCAD 1995: 138-143 - [c24]Jianmin Li, John Lillis, Chung-Kuan Cheng:
Linear decomposition algorithm for VLSI design applications. ICCAD 1995: 223-228 - [c23]Lung-Tien Liu, Ming-Ter Kuo, Shih-Chen Huang, Chung-Kuan Cheng:
A gradient method on the initial partition of Fiduccia-Mattheyses algorithm. ICCAD 1995: 229-234 - [c22]Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng:
Simple tree-construction heuristics for the fanout problem . ICCD 1995: 671-679 - [c21]Ming-Ter Kuo, Lung-Tien Liu, Chung-Kuan Cheng:
Finite State Machine Decomposition for I/O Minimization. ISCAS 1995: 1061-1064 - [c20]Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin:
Optimization of power dissipation and skew sensitivity in clock buffer synthesis. ISLPD 1995: 179-184 - 1994
- [j13]So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu:
A multi-probe approach for MCM substrate testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1): 110-121 (1994) - [j12]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
A general purpose, multiple-way partitioning algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12): 1480-1488 (1994) - [j11]Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel:
Block-oriented programmable design with switching network interconnect. IEEE Trans. Very Large Scale Integr. Syst. 2(1): 45-53 (1994) - [c19]Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof:
Circuit Partitioning for Huge Logic Emulation Systems. DAC 1994: 244-249 - [c18]Lung-Tien Liu, Minshine Shih, Chung-Kuan Cheng:
Data Flow Partitioning for Clock Period and Latency Minimization. DAC 1994: 658-663 - [c17]Jae Chung, Chung-Kuan Cheng:
Skew sensitivity minimization of buffered clock tree. ICCAD 1994: 280-283 - 1993
- [c16]Xianlong Hong, Tianxiong Xue, Ernest S. Kuh, Chung-Kuan Cheng, Jin Huang:
Performance-Driven Steiner Tree Algorithm for Global Routing. DAC 1993: 177-181 - [c15]So-Zen Yao, Chung-Kuan Cheng, Debaprosad Dutt, Surendra Nahar, Chi-Yuan Lo:
Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP. DAC 1993: 395-400 - [c14]Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau:
Prime: A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network Approach. DAC 1993: 531-536 - [c13]Jin Huang, Xianlong Hong, Chung-Kuan Cheng, Ernest S. Kuh:
An Efficient Timing-Driven Global Routing Algorithm. DAC 1993: 596-600 - [c12]Lung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku:
Performance-driven partitioning using retiming and replication. ICCAD 1993: 296-299 - [c11]Robert J. Carragher, Chung-Kuan Cheng, Masahiro Fujita:
An efficient algorithm for the net matching problem. ICCAD 1993: 640-644 - 1992
- [j10]Chung-Kuan Cheng, T. C. Hu:
Maximum Concurrent Flows and Minimum Cuts. Algorithmica 8(3): 233-249 (1992) - [j9]Chung-Kuan Cheng:
The optimal partitioning of networks. Networks 22(3): 297-315 (1992) - [j8]Chung-Kuan Cheng, David N. Deutsch, Craig Shohara, Mark Taparauskas, Mark Bubien:
Geometric compaction on channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(1): 115-127 (1992) - [j7]Chung-Kuan Cheng, Xiaotie Deng, Yuh-Zen Liao, So-Zen Yao:
Symbolic layout compaction under conditional design rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(4): 475-486 (1992) - [c10]Takeo Hamada, Chung-Kuan Cheng, Paul M. Chau:
A Wire Length Estimation Technique Utilizing Neighborhood Density Equations. DAC 1992: 57-61 - [c9]Xianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh:
FARM: An Efficient Feed-Through Pin Assignment Algorithm. DAC 1992: 530-535 - [c8]So-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu:
An optimal probe testing algorithm for the connectivity verification of MCM substrates. ICCAD 1992: 264-267 - [c7]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
A probabilistic multicommodity-flow solution to circuit clustering problems. ICCAD 1992: 428-431 - 1991
- [j6]Chung-Kuan Cheng, T. C. Hu:
Ancestor tree for arbitrary multi-terminal cut functions. Ann. Oper. Res. 33(3): 199-213 (1991) - [j5]Chung-Kuan Cheng, So-Zen Yao, T. C. Hu:
The Orientation of Modules Based on Graph Decomposition. IEEE Trans. Computers 40(6): 774-780 (1991) - [j4]Yen-Chuen A. Wei, Chung-Kuan Cheng:
Ratio cut partitioning for hierarchical designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(7): 911-921 (1991) - [j3]Chung-Kuan Cheng, Yen-Chuen A. Wei:
An improved two-way partitioning algorithm with stable performance [VLSI]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(12): 1502-1511 (1991) - [c6]Robert C. Carden IV, Chung-Kuan Cheng:
A Global Router Using An Efficient Approximate Multicommodity Multiterminal Flow Algorithm. DAC 1991: 316-321 - [c5]Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin:
A General Purpose Multiple Way Partitioning Algorithm. DAC 1991: 421-426 - 1990
- [c4]Yen-Chuen A. Wei, Chung-Kuan Cheng:
A Two-Level Two-Way Partitioning Algorithm. ICCAD 1990: 516-519 - [c3]Chung-Kuan Cheng, T. C. Hu:
Ancestor Tree for Arbitrary Multi-Terminal Cut Functions. IPCO 1990: 115-127
1980 – 1989
- 1989
- [c2]Yen-Chuen A. Wei, Chung-Kuan Cheng:
Towards efficient hierarchical designs by ratio cut partitioning. ICCAD 1989: 298-301 - 1988
- [c1]Chung-Kuan Cheng, David N. Deutsch:
Improved Channel Routing by Via Minimization and Shifting. DAC 1988: 677-680 - 1987
- [j2]Chung-Kuan Cheng:
Linear placement algorithms and applications to VLSI design. Networks 17(4): 439-464 (1987) - 1984
- [j1]Chung-Kuan Cheng, Ernest S. Kuh:
Module Placement Based on Resistive Network Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(3): 218-225 (1984)
Coauthor Index
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