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Changge Qiao
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2000 – 2009
- 2009
- [c5]Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer:
On improving optimization effectiveness in interconnect-driven physical synthesis. ISPD 2009: 51-58 - 2002
- [c4]Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng:
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction. SLIP 2002: 85-89
1990 – 1999
- 1999
- [c3]Xiaohai Wu, Changge Qiao, Xianlong Hong:
Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells. ASP-DAC 1999: 21- - [c2]Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai:
A Timing-Driven Block Placer Based on Sequence Pair Model. ASP-DAC 1999: 249-252 - 1997
- [c1]Tianming Kong, Xianlong Hong, Changge Qiao:
VEAP: Global optimization based efficient algorithm for VLSI placement. ASP-DAC 1997: 277-280
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last updated on 2024-04-24 22:54 CEST by the dblp team
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