default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID16th SLIP 2014: San Francisco, CA, USA
- ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2014, San Francisco, CA, USA, June 1, 2014. IEEE Computer Society 2014, ISBN 978-1-4503-3053-4
- Inna Vaisband, Eby G. Friedman:
Power network-on-chip for scalable power delivery. 1:1-1:5 - Xiang Zhang, Jingwei Lu, Yang Liu, Chung-Kuan Cheng:
Worst-case noise area prediciton of on-chip power distribution network. 2:1-2:8 - Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li, Charles J. Alpert, Cliff C. N. Sze:
Pacman: driving nonuniform clock grid loads for low-skew robust clock network. 3:1-3:5 - Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong
:
UI-route: An ultra-fast incremental maze routing algorithm. 4:1-4:8 - Julian Kemmerer, Baris Taskin:
Range-based dynamic routing of hierarchical on chip network traffic. 5:1-5:9 - Wei-Ting Jonas Chan, Andrew B. Kahng, Siddhartha Nath:
Methodology for electromigration signoff in the presence of adaptive voltage scaling. 6:1-6:7 - Qiaosha Zou, Yuan Xie:
Compact models and model standard for 2.5D and 3D integration. 7:1-7:7
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-22 19:49 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
