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ORCIDMartin D. F. Wong
D. F. Wong 0001 – Martin Ding Fat Wong
Person information
- affiliation: Hong Kong Baptist University, Hong Kong
- affiliation (former): University of Illinois at Urbana-Champaign, IL, USA
- affiliation (former): University of Texas at Austin, TX, USA
- affiliation (PhD 1987): University of Illinois at Urbana-Champaign, IL, USA
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2020 – today
- 2024
[j129]Binwu Zhu
, Su Zheng, Ziyang Yu, Guojin Chen, Yuzhe Ma, Fan Yang, Bei Yu, Martin D. F. Wong:
L2O-ILT: Learning to Optimize Inverse Lithography Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 944-955 (2024)- [j128]Lixin Liu, Bangqi Fu, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young, Martin D. F. Wong:
Xplace: An Extremely Fast and Extensible Placement Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1872-1885 (2024) - [j127]Guojin Chen, Zixiao Wang, Bei Yu, David Z. Pan, Martin D. F. Wong:
Ultrafast Source Mask Optimization via Conditional Discrete Diffusion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(7): 2140-2150 (2024) - [j126]Wenqian Zhao, Xufeng Yao, Shuo Yin, Yang Bai, Ziyang Yu, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
AdaOPC 2.0: Enhanced Adaptive Mask Optimization Framework for via Layers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2674-2686 (2024) - [j125]Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration. ACM Trans. Design Autom. Electr. Syst. 29(1): 20:1-20:23 (2024) - [c327]Chen Bai, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning. AAAI 2024: 12-20 - [c326]Bangqi Fu, Lixin Liu, Yang Sun, Wing Ho Lau, Martin D. F. Wong, Evangeline F. Y. Young:
CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs. ASPDAC 2024: 65-70 - [c325]Shiju Lin, Guannan Guo, Tsung-Wei Huang, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong:
GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis. DAC 2024: 71:1-71:6 - [c324]Su Zheng, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
EMOGen: Enhancing Mask Optimization via Pattern Generation. DAC 2024: 148:1-148:6 - [c323]Yang Sun, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young:
Massively Parallel AIG Resubstitution. DAC 2024: 157:1-157:6 - [c322]Qin Luo, Xinshi Zang, Qijing Wang, Fangzhou Wang, Evangeline F. Y. Young, Martin D. F. Wong:
A Routability-Driven Ultrascale FPGA Macro Placer with Complex Design Constraints. FCCM 2024: 1-7 - [c321]Qijing Wang, Jinwei Liu, Martin D. F. Wong, Evangeline F. Y. Young:
A Multi-agent Generative Model for Collaborative Global Routing Refinement. ACM Great Lakes Symposium on VLSI 2024: 383-389 - [c320]Xinshi Zang, Qin Luo, Zhongwei Shao, Jifeng Zhang, Evangeline F. Y. Young, Martin D. F. Wong:
Dynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and Routing. ACM Great Lakes Symposium on VLSI 2024: 433-439 - [c319]Qijing Wang, Xiaopeng Zhang, Martin D. F. Wong, Evangeline F. Y. Young:
ControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern Generation. ACM Great Lakes Symposium on VLSI 2024: 511-515 - [c318]Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong:
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs. ISPD 2024: 75-82 - [c317]Martin D. F. Wong:
ISPD 2024 Lifetime Achievement Award Bio. ISPD 2024: 231 - 2023
- [j124]Shiju Lin, Jinwei Liu, Evangeline F. Y. Young, Martin D. F. Wong:
GAMER: GPU-Accelerated Maze Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 583-593 (2023) - [j123]Bentian Jiang, Xinshi Zang, Martin D. F. Wong, Evangeline F. Y. Young:
Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 3067-3077 (2023) - [j122]Wenqian Zhao, Yang Bai, Qi Sun, Wenbo Li, Haisheng Zheng, Nianjuan Jiang, Jiangbo Lu, Bei Yu, Martin D. F. Wong:
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3210-3223 (2023) - [j121]Ziyang Yu, Peiyu Liao, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3402-3411 (2023) - [j120]Guannan Guo, Tsung-Wei Huang, Yibo Lin, Zizheng Guo, Sushma Yellapragada, Martin D. F. Wong:
A GPU-Accelerated Framework for Path-Based Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4219-4232 (2023) - [j119]Su Zheng, Hao Geng, Chen Bai, Bei Yu, Martin D. F. Wong:
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization. ACM Trans. Design Autom. Electr. Syst. 28(5): 74:1-74:23 (2023) - [j118]Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong:
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction. ACM Trans. Design Autom. Electr. Syst. 28(5): 80:1-80:18 (2023) - [c316]Su Zheng, Bei Yu, Martin D. F. Wong:
OpenILT: An Open Source Inverse Lithography Technique Framework (Invited Paper). ASICON 2023: 1-4 - [c315]Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields. DAC 2023: 1-6 - [c314]Peiyu Liao, Hongduo Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
On a Moreau Envelope Wirelength Model for Analytical Global Placement. DAC 2023: 1-6 - [c313]Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement. DAC 2023: 1-6 - [c312]Su Zheng, Lancheng Zou, Siting Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
Mitigating Distribution Shift for Congestion Optimization in Global Placement. DAC 2023: 1-6 - [c311]Guannan Guo, Tsung-Wei Huang, Martin D. F. Wong:
Fast STA Graph Partitioning Framework for Multi-GPU Acceleration. DATE 2023: 1-6 - [c310]Xinshi Zang, Lei Chen, Xing Li, Wilson W. K. Thong, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong:
CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems. ACM Great Lakes Symposium on VLSI 2023: 357-361 - [c309]Xinshi Zang, Evangeline F. Y. Young, Martin D. F. Wong:
SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems. ACM Great Lakes Symposium on VLSI 2023: 593-598 - [c308]Ziyang Yu, Chen Bai, Shoubo Hu, Ran Chen, Taohai He, Mingxuan Yuan, Bei Yu, Martin D. F. Wong:
IT-DSE: Invariance Risk Minimized Transfer Microarchitecture Design Space Exploration. ICCAD 2023: 1-9 - [c307]Su Zheng, Lancheng Zou, Peng Xu, Siting Liu, Bei Yu, Martin D. F. Wong:
Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction. ICCAD 2023: 1-9 - [c306]Zhen Zhuang, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong:
Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding. ICCAD 2023: 1-9 - [c305]Su Zheng, Haoyu Yang, Binwu Zhu, Bei Yu, Martin D. F. Wong:
LithoBench: Benchmarking AI Computational Lithography for Semiconductor Manufacturing. NeurIPS 2023 - [i3]Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
Physics-Informed Optical Kernel Regression Using Complex-valued Neural Fields. CoRR abs/2303.08435 (2023) - [i2]Wenqian Zhao, Qi Sun, Yang Bai, Wenbo Li, Haisheng Zheng, Bei Yu, Martin D. F. Wong:
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU. CoRR abs/2303.08999 (2023) - [i1]Wenqian Zhao, Xufeng Yao, Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
AdaOPC: A Self-Adaptive Mask Optimization Framework For Real Design Patterns. CoRR abs/2303.12723 (2023) - 2022
- [c304]Shiju Lin, Jinwei Liu, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young:
NovelRewrite: node-level parallel AIG rewriting. DAC 2022: 427-432 - [c303]Jinwei Liu, Xiaopeng Zhang, Shiju Lin, Xinshi Zang, Jingsong Chen, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young:
Partition and place finite element model on wafer-scale engine. DAC 2022: 631-636 - [c302]Qijing Wang, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young:
A2-ILT: GPU accelerated ILT with spatial attention mechanism. DAC 2022: 967-972 - [c301]Lixin Liu, Bangqi Fu, Martin D. F. Wong, Evangeline F. Y. Young:
Xplace: an extremely fast and extensible global placement framework. DAC 2022: 1309-1314 - [c300]Shiju Lin, Martin D. F. Wong:
Superfast Full-Scale CPU-Accelerated Global Routing. ICCAD 2022: 51:1-51:8 - [c299]Wenqian Zhao, Xufeng Yao, Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
AdaOPC: A Self-Adaptive Mask Optimization Framework for Real Design Patterns. ICCAD 2022: 123:1-123:9 - [c298]Qijing Wang, Martin D. F. Wong:
WaferHSL: Wafer Failure Pattern Classification with Efficient Human-Like Staged Learning. ICCAD 2022: 125:1-125:8 - [c297]Xinshi Zang, Fangzhou Wang, Jinwei Liu, Martin D. F. Wong:
ATLAS: A Two-Level Layer-Aware Scheme for Routing with Cell Movement. ICCAD 2022: 128:1-128:7 - [c296]Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong:
Efficient Design Rule Checking Script Generation via Key Information Extraction. MLCAD 2022: 77-82 - [p2]S. T. Choden Konigsmark, Wei Ren, Martin D. F. Wong, Deming Chen:
High-Level Synthesis for Minimizing Power Side-Channel Information Leakage. Behavioral Synthesis for Hardware Security 2022: 291-317 - 2021
- [j117]Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong:
OpenTimer v2: A Parallel Incremental Timing Analysis Engine. IEEE Des. Test 38(2): 62-68 (2021) - [j116]Tsung-Wei Huang, Guannan Guo, Chun-Xun Lin, Martin D. F. Wong:
OpenTimer v2: A New Parallel Incremental Timing Analysis Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 776-789 (2021) - [j115]Tsung-Wei Huang, Yibo Lin, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong:
Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1687-1700 (2021) - [c295]Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong:
GPU-accelerated Path-based Timing Analysis. DAC 2021: 721-726 - [c294]Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework. ICCAD 2021: 1-9 - [c293]Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong:
GPU-accelerated Critical Path Generation with Path Constraints. ICCAD 2021: 1-9 - [c292]Shiju Lin, Jinwei Liu, Martin D. F. Wong:
GAMER: GPU Accelerated Maze Routing. ICCAD 2021: 1-8 - [c291]Fangzhou Wang, Lixin Liu, Jingsong Chen, Jinwei Liu, Xinshi Zang, Martin D. F. Wong:
Starfish: An Efficient P&R Co-Optimization Engine with A*-based Partial Rerouting. ICCAD 2021: 1-9 - [c290]Wenqian Zhao, Qi Sun, Yang Bai, Wenbo Li, Haisheng Zheng, Bei Yu, Martin D. F. Wong:
A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU. ICCAD 2021: 1-9 - [c289]Dan Zheng, Xinshi Zang, Martin D. F. Wong:
TopoPart: a Multi-level Topology-Driven Partitioning Framework for Multi-FPGA Systems. ICCAD 2021: 1-8 - [c288]Binwu Zhu, Ran Chen, Xinyun Zhang, Fan Yang, Xuan Zeng, Bei Yu, Martin D. F. Wong:
Hotspot Detection via Multi-task Learning and Transformer Encoder. ICCAD 2021: 1-8 - 2020
- [j114]Daifeng Guo, Hongbo Zhang, Martin D. F. Wong:
On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1205-1216 (2020) - [c287]Guannan Guo, Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong:
An Efficient Critical Path Generation Algorithm Considering Extensive Path Constraints. DAC 2020: 1-6 - [c286]Zhuolun He, Yuzhe Ma, Lu Zhang, Peiyu Liao, Ngai Wong, Bei Yu, Martin D. F. Wong:
Learn to Floorplan through Acquisition of Effective Local Search Heuristics. ICCD 2020: 324-331 - [c285]Chun-Xun Lin, Tsung-Wei Huang, Martin D. F. Wong:
An Efficient Work-Stealing Scheduler for Task Dependency Graph. ICPADS 2020: 64-71
2010 – 2019
- 2019
- [j113]Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong:
DtCraft: A High-Performance Distributed Execution Engine at Scale. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1070-1083 (2019) - [c284]Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong:
Essential Building Blocks for Creating an Open-source EDA Project. DAC 2019: 78 - [c283]Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong:
Distributed Timing Analysis at Scale. DAC 2019: 229 - [c282]Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, Martin D. F. Wong:
An Efficient and Composable Parallel Task Programming Library. HPEC 2019: 1-7 - [c281]Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong:
Cpp-Taskflow: Fast Task-Based Parallel Programming Using Modern C++. IPDPS 2019: 974-983 - [c280]Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, Martin D. F. Wong:
A Modern C++ Parallel Task Programming Library. ACM Multimedia 2019: 2284-2287 - 2018
- [c279]Tin-Yin Lai, Martin D. F. Wong:
A highly compressed timing macro-modeling algorithm for hierarchical and incremental timing analysis. ASP-DAC 2018: 166-171 - [c278]Daifeng Guo, Hongbo Zhang, Martin D. F. Wong:
On coloring rectangular and diagonal grid graphs for multiple patterning lithography. ASP-DAC 2018: 387-392 - [c277]Chun-Xun Lin, Martin D. F. Wong:
Accelerate analytical placement with GPU: A generic approach. DATE 2018: 1345-1350 - [c276]Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, Martin D. F. Wong:
MtDetector: A High-performance Marine Traffic Detector at Stream Scale. DEBS 2018: 205-208 - [c275]Chun-Xun Lin, Tsung-Wei Huang, Ting Yu, Martin D. F. Wong:
A Distributed Power Grid Analysis Framework from Sequential Stream Graph. ACM Great Lakes Symposium on VLSI 2018: 183-188 - [c274]Chun-Xun Lin, Tsung-Wei Huang, Martin D. F. Wong:
Routing at compile time. ISQED 2018: 169-175 - [c273]Leslie Hwang, Beomjin Kwon, Martin D. F. Wong:
Accurate Models for Optimizing Tapered Microchannel Heat Sinks in 3D ICs. ISVLSI 2018: 58-63 - [c272]Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong:
A General-purpose Distributed Programming System using Data-parallel Streams. ACM Multimedia 2018: 1360-1363 - 2017
- [c271]S. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong:
High-Level Synthesis for side-channel defense. ASAP 2017: 37-44 - [c270]Tin-Yin Lai, Tsung-Wei Huang, Martin D. F. Wong:
LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs. DAC 2017: 65:1-65:6 - [c269]Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong:
DtCraft: A distributed execution engine for compute-intensive applications. ICCAD 2017: 757-765 - 2016
- [j112]Sven Tenzing Choden Konigsmark, Deming Chen, Martin D. F. Wong:
PolyPUF: Physically Secure Self-Divergence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7): 1053-1066 (2016) - [j111]Tsung-Wei Huang, Martin D. F. Wong:
UI-Timer 1.0: An Ultrafast Path-Based Timing Analysis Algorithm for CPPR. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11): 1862-1875 (2016) - [c268]Zigang Xiao, Chun-Xun Lin, Martin D. F. Wong, Hongbo Zhang:
Contact layer decomposition to enable DSA with multi-patterning technique for standard cell based layout. ASP-DAC 2016: 95-102 - [c267]S. T. Choden Konigsmark, Deming Chen, Martin D. F. Wong:
Information dispersion for trojan defense through high-level synthesis. DAC 2016: 87:1-87:6 - [c266]Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran:
A distributed timing analysis framework for large designs. DAC 2016: 116:1-116:6 - [c265]Martin D. F. Wong:
Early Days of Automatic Floorplan Design. ISPD 2016: 107 - [c264]Haitong Tian, Martin D. F. Wong:
Performance evaluation considering mask misalignment in multiple patterning decomposition. ISQED 2016: 192-197 - [r5]Martin D. F. Wong, Hannah Honghua Yang:
Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach. Encyclopedia of Algorithms 2016: 295-301 - [r4]Haitong Tian, Martin D. F. Wong:
Layout Decomposition for Multiple Patterning. Encyclopedia of Algorithms 2016: 1059-1062 - 2015
- [j110]Fan Zhang, Chen Hu, Pei-Ci Wu, Hongbo Zhang, Martin D. F. Wong:
Accelerating aerial image simulation using improved CPU/GPU collaborative computing. Comput. Electr. Eng. 46: 176-189 (2015) - [c263]Haitong Tian, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong:
An efficient linear time triple patterning solver. ASP-DAC 2015: 208-213 - [c262]Zigang Xiao, Yuelin Du, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang:
Contact pitch and location prediction for Directed Self-Assembly template verification. ASP-DAC 2015: 644-651 - [c261]Daifeng Guo, Yuelin Du, Martin D. F. Wong:
Polynomial time optimal algorithm for stencil row planning in e-beam lithography. ASP-DAC 2015: 658-664 - [c260]Zigang Xiao, Daifeng Guo, Martin D. F. Wong, He Yi, Maryann C. Tung, H.-S. Philip Wong:
Layout optimization and template pattern verification for directed self-assembly (DSA). DAC 2015: 199:1-199:6 - [c259]Tsung-Wei Huang, Martin D. F. Wong:
OpenTimer: A High-Performance Timing Analysis Tool. ICCAD 2015: 895-902 - [c258]Tsung-Wei Huang, Martin D. F. Wong:
Accelerated Path-Based Timing Analysis with MapReduce. ISPD 2015: 103-110 - [c257]Martin D. F. Wong:
Early Days of Circuit Placement. ISPD 2015: 129 - [c256]Tsung-Wei Huang, Martin D. F. Wong:
On fast timing closure: speeding up incremental path-based timing analysis with mapreduce. SLIP 2015: 1-6 - 2014
- [c255]S. T. Choden Konigsmark, Leslie Hwang, Deming Chen, Martin D. F. Wong:
CNPUF: A Carbon Nanotube-based Physically Unclonable Function for secure low-energy hardware design. ASP-DAC 2014: 73-78 - [c254]Ting Yu, Martin D. F. Wong:
Efficient simulation-based optimization of power grid with on-chip voltage regulator. ASP-DAC 2014: 531-536 - [c253]S. T. Choden Konigsmark, Leslie K. Hwang, Deming Chen, Martin D. F. Wong:
System-of-PUFs: Multilevel security for embedded systems. CODES+ISSS 2014: 27:1-27:10 - [c252]Pei-Ci Wu, Martin D. F. Wong, Ivailo Nedelchev, Sarvesh Bhardwaj, Vidyamani Parkhe:
On Timing Closure: Buffer Insertion for Hold-Violation Removal. DAC 2014: 6:1-6:6 - [c251]Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang:
Directed Self-Assembly (DSA) Template Pattern Verification. DAC 2014: 55:1-55:6 - [c250]Yuelin Du, Martin D. F. Wong:
Optimization of standard cell based detailed placement for 16 nm FinFET process. DATE 2014: 1-6 - [c249]Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong:
Triple patterning aware detailed placement with constrained pattern assignment. ICCAD 2014: 116-123 - [c248]Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong:
Fast path-based timing analysis for CPPR. ICCAD 2014: 596-599 - [c247]Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong:
UI-timer: an ultra-fast clock network pessimism removal algorithm. ICCAD 2014: 758-765 - [c246]Tsung-Wei Huang, Pei-Ci Wu, Martin D. F. Wong:
UI-route: An ultra-fast incremental maze routing algorithm. SLIP 2014: 4:1-4:8 - 2013
- [j109]Zigang Xiao, Yuelin Du, Hongbo Zhang, Martin D. F. Wong:
A Polynomial Time Exact Algorithm for Overlay-Resistant Self-Aligned Double Patterning (SADP) Layout Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(8): 1228-1239 (2013) - [j108]Tan Yan, Qiang Ma, Scott Chilstedt, Martin D. F. Wong, Deming Chen:
A routing algorithm for graphene nanoribbon circuit. ACM Trans. Design Autom. Electr. Syst. 18(4): 61:1-61:18 (2013) - [c245]Ismail Bustany, Igor L. Markov, Martin D. F. Wong:
The nature of optimization problem challenges in physical synthesis. ACC 2013: 6057-6059 - [c244]Pei-Ci Wu, Qiang Ma, Martin D. F. Wong:
An ILP-based automatic bus planner for dense PCBs. ASP-DAC 2013: 181-186 - [c243]Pei-Ci Wu, Martin D. F. Wong:
Network flow modeling for escape routing on staggered pin arrays. ASP-DAC 2013: 193-198 - [c242]Yuelin Du, Hongbo Zhang, Qiang Ma, Martin D. F. Wong:
Linear time algorithm to find all relocation positions for EUV defect mitigation. ASP-DAC 2013: 261-266 - [c241]Yuelin Du, Qiang Ma, Hua Song, James P. Shiely, Gerard Luk-Pat, Alexander Miloslavsky, Martin D. F. Wong:
Spacer-is-dielectric-compliant detailed routing for self-aligned double patterning lithography. DAC 2013: 93:1-93:6 - [c240]Pei-Ci Wu, Tan Yan, Hongbo Zhang, Martin D. F. Wong:
Efficient aerial image simulation on multi-core SIMD CPU. ICCAD 2013: 24-31 - [c239]Zigang Xiao, Yuelin Du, Haitong Tian, Martin D. F. Wong:
Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time. ICCAD 2013: 32-39 - [c238]Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong:
Constrained pattern assignment for standard cell based triple patterning lithography. ICCAD 2013: 178-185 - [c237]Yuelin Du, Daifeng Guo, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang, Qiang Ma:
Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library. ICCAD 2013: 186-193 - [c236]Ting Yu, Martin D. F. Wong:
A novel and efficient method for power pad placement optimization. ISQED 2013: 158-163 - [c235]Martin D. F. Wong:
Advances in wire routing. ISQED 2013: 257 - 2012
- [j107]Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng:
A Practical Low-Power Nonregular Interconnect Design With Manufacturing for Design Approach. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 322-332 (2012) - [j106]Tan Yan, Qiang Ma, Martin D. F. Wong:
Advances in PCB Routing. Inf. Media Technol. 7(2): 535-543 (2012) - [j105]Tan Yan, Qiang Ma, Martin D. F. Wong:
Advances in PCB Routing. IPSJ Trans. Syst. LSI Des. Methodol. 5: 14-22 (2012) - [j104]Tan Yan, Martin D. F. Wong:
Correctly Model the Diagonal Capacity in Escape Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 285-293 (2012) - [j103]Qiang Ma, Martin D. F. Wong:
NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1356-1365 (2012) - [c234]Lijuan Luo, Martin D. F. Wong, Lance Leong:
Parallel implementation of R-trees on the GPU. ASP-DAC 2012: 353-358 - [c233]Yuelin Du, Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao:
Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design. ASP-DAC 2012: 707-712 - [c232]Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Rasit Onur Topaloglu:
Efficient pattern relocation for EUV blank defect mitigation. ASP-DAC 2012: 719-724 - [c231]Qiang Ma, Hongbo Zhang, Martin D. F. Wong:
Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology. DAC 2012: 591-596 - [c230]Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Yunfei Deng, Pawitter Mangat:
Layout small-angle rotation and shift for EUV defect mitigation. ICCAD 2012: 43-49 - [c229]Haitong Tian, Hongbo Zhang, Qiang Ma, Zigang Xiao, Martin D. F. Wong:
A polynomial time triple patterning algorithm for cell based row-structure layout. ICCAD 2012: 57-64 - [c228]Ting Yu, Zigang Xiao, Martin D. F. Wong:
Efficient parallel power grid analysis via Additive Schwarz Method. ICCAD 2012: 399-406 - [c227]Ting Yu, Martin D. F. Wong:
PGT_SOLVER: An efficient solver for power grid transient analysis. ICCAD 2012: 647-652 - [c226]Zigang Xiao, Yuelin Du, Hongbo Zhang, Martin D. F. Wong:
A polynomial time exact algorithm for self-aligned double patterning layout decomposition. ISPD 2012: 17-24 - [c225]Martin D. F. Wong:
On simulated annealing in EDA. ISPD 2012: 63-64 - [c224]Leslie Hwang, Kevin L. Lin, Martin D. F. Wong:
Thermal via structural design in three-dimensional integrated circuits. ISQED 2012: 103-108 - [c223]Qiang Ma, Zigang Xiao, Martin D. F. Wong:
Algorithmic study on the routing reliability problem. ISQED 2012: 483-488 - [c222]Hongbo Zhang, Yunfei Deng, Jongwook Kye, Martin D. F. Wong:
Impact of lithography retargeting process on low level interconnect in 20nm technology. SLIP 2012: 3-10 - 2011
- [j102]Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya:
A New Strategy for Simultaneous Escape Based on Boundary Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 205-214 (2011) - [j101]Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang:
Thermal-Driven Analog Placement Considering Device Matching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 325-336 (2011) - [c221]Tan Yan, Qiang Ma, Scott Chilstedt, Martin D. F. Wong, Deming Chen:
Routing with graphene nanoribbons. ASP-DAC 2011: 323-329 - [c220]Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao:
Mask cost reduction with circuit performance consideration for self-aligned double patterning. ASP-DAC 2011: 787-792 - [c219]Qiang Ma, Hui Kong, Martin D. F. Wong, Evangeline F. Y. Young:
A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing. ASP-DAC 2011: 843-848 - [c218]Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Rasit Onur Topaloglu:
Self-aligned double patterning decomposition for overlay minimization and hot spot detection. DAC 2011: 71-76 - [c217]Qiang Ma, Evangeline F. Y. Young, Martin D. F. Wong:
An optimal algorithm for layer assignment of bus escape routing on PCBs. DAC 2011: 176-181 - [c216]Hongbo Zhang, Tan Yan, Martin D. F. Wong, Sanjay J. Patel:
Accelerating aerial image simulation with GPU. ICCAD 2011: 178-184 - [c215]Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao:
Lithography-aware layout modification considering performance impact. ISQED 2011: 437-441 - 2010
- [j100]Quang Dinh, Deming Chen, Martin D. F. Wong:
A Routing Approach to Reduce Glitches in Low Power FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(2): 235-240 (2010) - [c214]Hui Kong, Tan Yan, Martin D. F. Wong:
Optimal simultaneous pin assignment and escape routing for dense PCBs. ASP-DAC 2010: 275-280 - [c213]Qiang Ma, Martin D. F. Wong, Kai-Yuan Chao:
Configurable multi-product floorplanning. ASP-DAC 2010: 549-554 - [c212]Quang Dinh, Deming Chen, Martin D. F. Wong:
Dynamic power estimation for deep submicron circuits with process variation. ASP-DAC 2010: 587-592 - [c211]Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao:
On process-aware 1-D standard cell design. ASP-DAC 2010: 838-842 - [c210]Lijuan Luo, Martin D. F. Wong, Wen-mei W. Hwu:
An effective GPU implementation of breadth-first search. DAC 2010: 52-55 - [c209]Hui Kong, Qiang Ma, Tan Yan, Martin D. F. Wong:
An optimal algorithm for finding disjoint rectangles and its application to PCB routing. DAC 2010: 212-217 - [c208]Tan Yan, Martin D. F. Wong:
Recent research development in PCB layout. ICCAD 2010: 398-403 - [c207]Tan Yan, Pei-Ci Wu, Qiang Ma, Martin D. F. Wong:
On the escape routing of differential pairs. ICCAD 2010: 614-620 - [c206]Quang Dinh, Deming Chen, Martin D. F. Wong:
BDD-based circuit restructuring for reducing dynamic power. ICCD 2010: 548-554 - [c205]Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya:
B-escape: a simultaneous escape routing algorithm based on boundary routing. ISPD 2010: 19-25 - [c204]Yu Zhong, Martin D. F. Wong:
Fast block-iterative domain decomposition algorithm for IR drop analysis in large power grid. ISQED 2010: 277-283 - [c203]Qiang Ma, Tan Yan, Martin D. F. Wong:
A negotiated congestion based router for simultaneous escape routing. ISQED 2010: 606-610 - [c202]Martin D. F. Wong:
Advances in PCB routing. SLIP 2010: 33-34
2000 – 2009
- 2009
- [j99]Huaizhi Wu, Martin D. F. Wong:
Incremental Improvement of Voltage Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 217-230 (2009) - [j98]Muhammet Mustafa Ozdal, Martin D. F. Wong:
Archer: A History-Based Global Routing Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(4): 528-540 (2009) - [j97]Tan Yan, Martin D. F. Wong:
BSG-Route: A Length-Constrained Routing Scheme for General Planar Topology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1679-1690 (2009) - [j96]Tan Yan, Martin D. F. Wong:
Theories and algorithms on single-detour routing for untangling twisted bus. ACM Trans. Design Autom. Electr. Syst. 14(3): 46:1-46:21 (2009) - [c201]Lijuan Luo, Martin D. F. Wong:
On using SAT to ordered escape problems. ASP-DAC 2009: 594-599 - [c200]Hui Kong, Tan Yan, Martin D. F. Wong:
Automatic bus planner for dense PCBs. DAC 2009: 326-331 - [c199]Tan Yan, Martin D. F. Wong:
A correct network flow model for escape routing. DAC 2009: 332-335 - [c198]Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang:
Flip-chip routing with unified area-I/O pad assignments for package-board co-design. DAC 2009: 336-339 - [c197]Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang:
Thermal-driven analog placement considering device matching. DAC 2009: 593-598 - [c196]Tan Yan, Hui Kong, Martin D. F. Wong:
Optimal layer assignment for escape routing of buses. ICCAD 2009: 245-248 - [c195]Quang Dinh, Deming Chen, Martin D. F. Wong:
A routing approach to reduce glitches in low power FPGAs. ISPD 2009: 99-106 - [c194]Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng:
Wire shaping is practical. ISPD 2009: 131-138 - 2008
- [j95]Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger:
Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 84-95 (2008) - [j94]Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong:
Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 621-632 (2008) - [j93]Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong:
Fast Dummy-Fill Density Analysis With Coupling Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 633-642 (2008) - [j92]Lei Cheng, Deming Chen, Martin D. F. Wong:
DDBDD: Delay-Driven BDD Synthesis for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1203-1213 (2008) - [j91]Lei Cheng, Deming Chen, Martin D. F. Wong:
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. ACM Trans. Design Autom. Electr. Syst. 13(2): 34:1-34:15 (2008) - [j90]Huaizhi Wu, Martin D. F. Wong, Wilsin Gosti:
Postplacement voltage assignment under performance constraints. ACM Trans. Design Autom. Electr. Syst. 13(3): 46:1-46:20 (2008) - [j89]Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger:
Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules. ACM Trans. Design Autom. Electr. Syst. 13(4): 68:1-68:20 (2008) - [c193]Lijuan Luo, Martin D. F. Wong:
Ordered escape routing based on Boolean satisfiability. ASP-DAC 2008: 244-249 - [c192]Quang Dinh, Deming Chen, Martin D. F. Wong:
Efficient ASIP design for configurable processors with fine-grained resource sharing. FPGA 2008: 99-106 - [c191]Tan Yan, Martin D. F. Wong:
BSG-Route: a length-matching router for general topology. ICCAD 2008: 499-505 - [c190]Yu Zhong, Martin D. F. Wong:
Thermal-Aware IR Drop Analysis in Large Power Grid. ISQED 2008: 194-199 - [r3]Hannah Honghua Yang, Martin D. F. Wong:
Circuit Partitioning: A Network-Flow-Based Balanced Min-Cut Approach. Encyclopedia of Algorithms 2008 - [r2]Muhammet Mustafa Ozdal, Martin D. F. Wong:
Global Routing Formulation and Maze Routing. Handbook of Algorithms for Physical Design Automation 2008 - [r1]Ting-Chi Wang, Martin D. F. Wong:
Slicing Floorplans. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j88]Huaizhi Wu, Martin D. F. Wong, I-Min Liu, Yusu Wang:
Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1256-1269 (2007) - [c189]David M. Pawlowski, Liang Deng, Martin D. F. Wong:
Fast and Accurate OPC for Standard-Cell Layouts. ASP-DAC 2007: 7-12 - [c188]Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang:
Coupling-aware Dummy Metal Insertion for Lithography. ASP-DAC 2007: 13-18 - [c187]Yu Zhong, Martin D. F. Wong:
Fast Placement Optimization of Power Supply Pads. ASP-DAC 2007: 763-767 - [c186]Yu Zhong, Martin D. F. Wong:
Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid. ASP-DAC 2007: 768-773 - [c185]Lei Cheng, Deming Chen, Martin D. F. Wong:
GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. DAC 2007: 318-323 - [c184]Huaizhi Wu, Martin D. F. Wong:
Improving Voltage Assignment by Outlier Detection and Incremental Placement. DAC 2007: 459-464 - [c183]Lei Cheng, Deming Chen, Martin D. F. Wong:
DDBDD: Delay-Driven BDD Synthesis for FPGAs. DAC 2007: 910-915 - [c182]Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig:
Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. ICCAD 2007: 370-375 - [c181]Hui Kong, Tan Yan, Martin D. F. Wong, Muhammet Mustafa Ozdal:
Optimal bus sequencing for escape routing in dense PCBs. ICCAD 2007: 390-395 - [c180]Tan Yan, Martin D. F. Wong:
Untangling twisted nets for bus routing. ICCAD 2007: 396-400 - [c179]Muhammet Mustafa Ozdal, Martin D. F. Wong:
Archer: a history-driven global routing algorithm. ICCAD 2007: 488-495 - [c178]Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong:
Dummy fill density analysis with coupling constraints. ISPD 2007: 3-10 - [c177]Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong:
Is your layout density verification exact?: a fast exact algorithm for density calculation. ISPD 2007: 19-26 - [c176]Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong:
OPC-Friendly Bus Driven Floorplanning. ISQED 2007: 847-852 - 2006
- [j87]Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong, Sachin S. Sapatnekar:
Temperature-Aware Placement for SOCs. Proc. IEEE 94(8): 1502-1518 (2006) - [j86]Muhammet Mustafa Ozdal, Martin D. F. Wong:
Algorithmic study of single-layer bus routing for high-speed boards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 490-503 (2006) - [j85]Muhammet Mustafa Ozdal, Martin D. F. Wong:
Algorithms for simultaneous escape routing and Layer assignment of dense PCBs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(8): 1510-1522 (2006) - [j84]Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong:
Minimizing wire length in floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1744-1753 (2006) - [j83]Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong:
An ECO routing algorithm for eliminating coupling-capacitance violations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1754-1762 (2006) - [j82]Hung-Ming Chen, I-Min Liu, Martin D. F. Wong:
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2552-2556 (2006) - [j81]Muhammet Mustafa Ozdal, Martin D. F. Wong:
A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2784-2794 (2006) - [j80]Lei Cheng, Martin D. F. Wong:
Floorplan Design for Multimillion Gate FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2795-2805 (2006) - [j79]Muhammet Mustafa Ozdal, Martin D. F. Wong:
Two-layer bus routing for high-speed printed circuit boards. ACM Trans. Design Autom. Electr. Syst. 11(1): 213-227 (2006) - [c175]Sebastian Vogel, Martin D. F. Wong:
Closed form solution for optimal buffer sizing using the Weierstrass elliptic function. ASP-DAC 2006: 315-319 - [c174]Liang Deng, Martin D. F. Wong:
An exact algorithm for the statistical shortest path problem. ASP-DAC 2006: 965-970 - [c173]Lei Cheng, Liang Deng, Deming Chen, Martin D. F. Wong:
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. DAC 2006: 117-120 - [c172]Huaizhi Wu, Martin D. F. Wong, I-Min Liu:
Timing-constrained and voltage-island-aware voltage assignment. DAC 2006: 429-432 - 2005
- [j78]Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong:
Simultaneous power supply planning and noise avoidance in floorplan design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 578-587 (2005) - [j77]Hua Xiang, Xiaoping Tang, Martin D. F. Wong:
An algorithm for integrated pin assignment and buffer planning. ACM Trans. Design Autom. Electr. Syst. 10(3): 561-572 (2005) - [c171]Lei Cheng, Liang Deng, Martin D. F. Wong:
Floorplanning for 3-D VLSI design. ASP-DAC 2005: 405-411 - [c170]Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong:
Optimal redistribution of white space for wire length minimization. ASP-DAC 2005: 412-417 - [c169]Yongseok Cheon, Martin D. F. Wong:
Crowdedness-balanced multilevel partitioning for uniform resource utilization. ASP-DAC 2005: 418-423 - [c168]Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong:
CMP aware shuttle mask floorplanning. ASP-DAC 2005: 1111-1114 - [c167]Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong:
Redundant-via enhanced maze routing for yield improvement. ASP-DAC 2005: 1148-1151 - [c166]Liang Deng, Martin D. F. Wong:
Energy optimization in memory address bus structure for application-specific systems. ACM Great Lakes Symposium on VLSI 2005: 232-237 - [c165]Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang:
Post-placement voltage island generation under performance requirement. ICCAD 2005: 309-316 - [c164]Liang Deng, Martin D. F. Wong:
Buffer insertion under process variations for delay minimization. ICCAD 2005: 317-321 - [c163]Yu Zhong, Martin D. F. Wong:
Fast algorithms for IR drop analysis in large power grid. ICCAD 2005: 351-357 - [c162]Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger:
An escape routing framework for dense boards with high-speed design constraints. ICCAD 2005: 759-766 - [c161]Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger:
Optimal routing algorithms for pin clusters in high-density multichip modules. ICCAD 2005: 767-774 - [c160]Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong:
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. ISQED 2005: 181-186 - [c159]Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong:
Current Calculation on VLSI Signal Interconnects. ISQED 2005: 580-585 - [c158]Hua Xiang, I-Min Liu, Martin D. F. Wong:
Wire Planning with Bounded Over-the-Block Wires. ISQED 2005: 622-627 - [c157]Muzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong:
IR Drop and Ground Bounce Awareness Timing Model. ISVLSI 2005: 226-231 - 2004
- [j76]Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu:
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 141-147 (2004) - [j75]Hua Xiang, Xiaoping Tang, Martin D. F. Wong:
Bus-driven floorplanning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(11): 1522-1530 (2004) - [c156]Xiaoping Tang, Martin D. F. Wong:
On handling arbitrary rectilinear shape constraint. ASP-DAC 2004: 38-41 - [c155]Xiaoping Tang, Martin D. F. Wong:
Tradeoff routing resource, runtime and quality in buffered routing. ASP-DAC 2004: 430-433 - [c154]Li-Da Huang, Martin D. F. Wong:
Optical proximity correction (OPC): friendly maze routing. DAC 2004: 186-191 - [c153]Liang Deng, Martin D. F. Wong:
Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus. DATE 2004: 1104-1109 - [c152]Lei Cheng, Martin D. F. Wong:
Floorplan design for multi-million gate FPGAs. ICCAD 2004: 292-299 - [c151]Muhammet Mustafa Ozdal, Martin D. F. Wong:
Simultaneous escape routing and layer assignment for dense PCBs. ICCAD 2004: 822-829 - [c150]Muhammet Mustafa Ozdal, Martin D. F. Wong:
A provably good algorithm for high performance bus routing. ICCAD 2004: 830-837 - [c149]Muhammet Mustafa Ozdal, Martin D. F. Wong:
A Two-Layer Bus Routing Algorithm for High-Speed Boards. ICCD 2004: 99-105 - [c148]Martin D. F. Wong:
Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers. ICCD 2004: 106-110 - [c147]Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang:
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. ICCD 2004: 562-567 - [c146]Esra Erdem, Martin D. F. Wong:
Rectilinear Steiner Tree Construction Using Answer Set Programming. ICLP 2004: 386-399 - [c145]Hua Xiang, Kai-Yuan Chao, D. F. Wong:
An ECO algorithm for eliminating crosstalk violations. ISPD 2004: 41-46 - 2003
- [j74]Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao:
Maze routing with buffer insertion under transition time constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 91-95 (2003) - [j73]Yongseok Cheon, Martin D. F. Wong:
Design hierarchy-guided multilevel circuit partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 420-427 (2003) - [j72]Seokjin Lee, Martin D. F. Wong:
Timing-driven routing for FPGAs based on Lagrangian relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 506-510 (2003) - [j71]Hua Xiang, Xiaoping Tang, Martin D. F. Wong:
Min-cost flow-based algorithm for simultaneous pin assignment and routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 870-878 (2003) - [j70]Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong:
Analysis of FPGA/FPIC switch modules. ACM Trans. Design Autom. Electr. Syst. 8(1): 11-37 (2003) - [c144]Muzhou Shao, D. F. Wong, Youxin Gao, Huijing Cao, Li-Pen Yuan:
A fast and accurate method for interconnect current calculation. ASP-DAC 2003: 37-42 - [c143]Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong:
Floorplanning with power supply noise avoidance. ASP-DAC 2003: 427-430 - [c142]John F. Croix, D. F. Wong:
Blade and razor: cell and interconnect delay analysis using current-based models. DAC 2003: 386-389 - [c141]Li-Da Huang, Hung-Ming Chen, D. F. Wong:
Global Wire Bus Configuration with Minimum Delay Uncertainty. DATE 2003: 10050-10055 - [c140]Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun:
Wire type assignment for FPGA routing. FPGA 2003: 61-67 - [c139]Hua Xiang, Xiaoping Tang, Martin D. F. Wong:
Bus-Driven Floorplanning. ICCAD 2003: 66-73 - [c138]Seokjin Lee, Yongseok Cheon, Martin D. F. Wong:
A Min-Cost Flow Based Detailed Router for FPGAs. ICCAD 2003: 388-393 - [c137]Muhammet Mustafa Ozdal, Martin D. F. Wong:
Length-Matching Routing for High-Speed Printed Circuit Boards. ICCAD 2003: 394-400 - [c136]Yongseok Cheon, Seokjin Lee, Martin D. F. Wong:
Stable Multiway Circuit Partitioning for ECO. ICCAD 2003: 718-725 - [c135]Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee:
Explicit gate delay model for timing evaluation. ISPD 2003: 32-38 - 2002
- [j69]Ruiqi Tian, Xiaoping Tang, Martin D. F. Wong:
Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 63-71 (2002) - [j68]Minghorng Lai, Martin D. F. Wong:
Maze routing with buffer insertion and wiresizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1205-1209 (2002) - [j67]Yu-Min Lee, Charlie Chung-Ping Chen, Yao-Wen Chang, Martin D. F. Wong:
Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation. VLSI Design 15(3): 587-594 (2002) - [c134]Hua Xiang, D. F. Wong, Xiaoping Tang:
An algorithm for integrated pin assignment and buffer planning. DAC 2002: 584-589 - [c133]Xiaoping Tang, D. F. Wong:
Floorplanning with alignment and performance constraints. DAC 2002: 848-853 - [c132]Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu:
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. DATE 2002: 470-475 - [c131]Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao:
Maze Routing with Buffer Insertion under Transition Time Constraints. DATE 2002: 702-707 - [c130]K. K. Lee, D. F. Wong:
Incremental reconfiguration of multi-FPGA systems. FPGA 2002: 206-213 - [c129]Hua Xiang, Kai-Yuan Chao, D. F. Wong:
ECO algorithms for removing overlaps between power rails and signal wires. ICCAD 2002: 67-74 - [c128]Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao:
Shaping interconnect for uniform current density. ICCAD 2002: 254-259 - [c127]Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D. F. Wong:
On mask layout partitioning for electron projection lithography. ICCAD 2002: 514-518 - [c126]Yongseok Cheon, D. F. Wong:
Design hierarchy guided multilevel circuit partitioning. ISPD 2002: 30-35 - [c125]Seokjin Lee, D. F. Wong:
Timing-driven routing for FPGAs based on Lagrangian relaxation. ISPD 2002: 176-181 - 2001
- [j66]Chris C. N. Chu, D. F. Wong:
VLSI Circuit Performance Optimization by Geometric Programming. Ann. Oper. Res. 105(1-4): 37-60 (2001) - [j65]Xiaoping Tang, D. F. Wong:
Network flow based buffer planning. Integr. 30(2): 143-155 (2001) - [j64]Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong:
Matching-based algorithm for FPGA channel segmentation design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 784-791 (2001) - [j63]Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang:
On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 800-807 (2001) - [j62]Ruiqi Tian, Martin D. F. Wong, Robert Boone:
Model-based dummy feature placement for oxide chemical-mechanicalpolishing manufacturability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(7): 902-910 (2001) - [j61]Xiaoping Tang, Ruiqi Tian, Martin D. F. Wong:
Fast evaluation of sequence pair in block placement by longestcommon subsequence computation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(12): 1406-1413 (2001) - [j60]Chris C. N. Chu, D. F. Wong:
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. ACM Trans. Design Autom. Electr. Syst. 6(3): 343-371 (2001) - [c124]Minghorng Lai, D. F. Wong:
Memory-efficient interconnect optimization. ASP-DAC 2001: 198-202 - [c123]Xiaoping Tang, D. F. Wong:
FAST-SP: a fast algorithm for block placement based on sequence pair. ASP-DAC 2001: 521-526 - [c122]Youxin Gao, D. F. Wong:
A fast and accurate delay estimation method for buffered interconnects. ASP-DAC 2001: 533-538 - [c121]I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong:
Integrated power supply planning and floorplanning. ASP-DAC 2001: 589-594 - [c120]Minghorng Lai, D. F. Wong:
Slicing tree is a complete floorplan representation. DATE 2001: 228-232 - [c119]Youxin Gao, D. F. Wong:
A graph based algorithm for optimal buffer insertion under accurate delay models. DATE 2001: 535-539 - [c118]K. K. Lee, D. F. Wong:
LRoute: a delay minimal router for hierarchical CPLDs. FPGA 2001: 12-20 - [c117]Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang:
Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI 2001: 62-67 - [c116]Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong:
A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. ICCAD 2001: 49-56 - [c115]Hua Xiang, Xiaoping Tang, D. F. Wong:
An Algorithm for Simultaneous Pin Assignment and Routing. ICCAD 2001: 232- - [c114]Ruiqi Tian, Xiaoping Tang, D. F. Wong:
Dummy feature placement for chemical-mechanical polishing uniformity in a shallow trench isolation process. ISPD 2001: 118-123 - 2000
- [j59]Wai-Kei Mak, D. F. Wong:
A fast hypergraph min-cut algorithm for circuit partitioning. Integr. 30(1): 1-11 (2000) - [j58]Martin D. F. Wong, Dwight D. Hill:
Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 173-174 (2000) - [j57]Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang:
Slicing floorplans with range constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 272-278 (2000) - [j56]Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz:
Simultaneous routing and buffer insertion with restrictions onbuffer locations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7): 819-824 (2000) - [j55]Yao-Wen Chang, Kai Zhu, D. F. Wong:
Timing-driven routing for symmetrical array-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 5(3): 433-450 (2000) - [j54]Huiqun Liu, Kai Zhu, D. F. Wong:
FPGA Partitioning with Complex Resource Constraints. VLSI Design 11(3): 219-235 (2000) - [c113]Esra Erdem, Vladimir Lifschitz, Martin D. F. Wong:
Wire Routing and Satisfiability Planning. Computational Logic 2000: 822-836 - [c112]Hai Zhou, D. F. Wong:
Optimal low power X OR gate decomposition. DAC 2000: 104-107 - [c111]Minghorng Lai, D. F. Wong:
Maze routing with buffer insertion and wiresizing. DAC 2000: 374-378 - [c110]Ruiqi Tian, D. F. Wong, Robert Boone:
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability. DAC 2000: 667-670 - [c109]Xiaoping Tang, D. F. Wong, Ruiqi Tian:
Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation. DATE 2000: 106-111 - [c108]I-Min Liu, Adnan Aziz, D. F. Wong:
Meeting Delay Constraints in DSM by Minimal Repeater Insertion. DATE 2000: 436-440 - [c107]Youxin Gao, D. F. Wong:
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. DATE 2000: 512-516 - [c106]I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong:
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. ISPD 2000: 33-38 - [c105]Xiaoping Tang, D. F. Wong:
Planning buffer locations by network flows. ISPD 2000: 180-185
1990 – 1999
- 1999
- [j53]Youxin Gao, D. F. Wong:
Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance. Integr. 27(2): 165-178 (1999) - [j52]Fung Yu Young, Chris C. N. Chu, D. F. Wong:
Generation of Universal Series-Parallel Boolean Functions. J. ACM 46(3): 416-435 (1999) - [j51]Chris C. N. Chu, Martin D. F. Wong:
Greedy wire-sizing is linear time. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 398-405 (1999) - [j50]Chris C. N. Chu, Martin D. F. Wong:
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6): 787-798 (1999) - [j49]Youxin Gao, Martin D. F. Wong:
Optimal shape function for a bidirectional wire under Elmore delay model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7): 994-999 (1999) - [j48]Chung-Ping Chen, Chris C. N. Chu, Martin D. F. Wong:
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7): 1014-1025 (1999) - [j47]Chris C. N. Chu, Martin D. F. Wong:
An efficient and optimal algorithm for simultaneous buffer and wire sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1297-1304 (1999) - [j46]Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang:
Slicing floorplans with boundary constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1385-1389 (1999) - [j45]Hai Zhou, Martin D. F. Wong:
Global routing with crosstalk constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1683-1688 (1999) - [j44]Youxin Gao, Martin D. F. Wong:
Wire-sizing optimization with inductance consideration using transmission-line model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12): 1759-1767 (1999) - [c104]Fung Yu Young, D. F. Wong:
Slicing Floorplans with Boundary Constraint. ASP-DAC 1999: 17-20 - [c103]Youxin Gao, D. F. Wong:
Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. ASP-DAC 1999: 217-220 - [c102]Chung-Ping Chen, D. F. Wong:
Error Bounded Padé Approximation via Bilinear Conformal Transformation. DAC 1999: 7-12 - [c101]Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz:
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. DAC 1999: 96-99 - [c100]Huiqun Liu, D. F. Wong:
Circuit Partitioning for Dynamically Reconfigurable FPGAs. FPGA 1999: 187-194 - [c99]Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani:
Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357 - [c98]Huiqun Liu, D. F. Wong:
A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning. ICCAD 1999: 400-405 - [c97]Jacob White, Jacob Avidan, Ibrahim Abe M. Elfadel, D. F. Wong:
Advances in transistor timing, simulation, and optimization (tutorial abstract). ICCAD 1999: 611 - [c96]I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou:
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. ICCD 1999: 210-215 - [c95]K. K. Lee, D. F. Wong:
An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs. ICCD 1999: 216-221 - [c94]Wai-Kei Mak, D. F. Wong:
A fast hypergraph minimum cut algorithm. ISCAS (6) 1999: 170-173 - [c93]Fung Yu Young, D. F. Wong:
Slicing floorplans with range constraint. ISPD 1999: 97-102 - [e1]D. F. Wong:
Proceedings of the 1999 International Symposium on Physical Design, ISPD 1999, Monterey, CA, USA, April 12-14, 1999. ACM 1999, ISBN 1-58113-089-9 [contents] - 1998
- [j43]Huiqun Liu, Martin D. F. Wong:
Network-flow-based multiway partitioning with area and pin constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1): 50-59 (1998) - [j42]Kai Zhu, Martin D. F. Wong:
Switch bound allocation for maximizing routability in timing-driven routing of FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(4): 316-323 (1998) - [j41]Chris C. N. Chu, Martin D. F. Wong:
A matrix synthesis approach to thermal placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11): 1166-1174 (1998) - [j40]Hannah Honghua Yang, Martin D. F. Wong:
Optimal min-area min-cut replication in partitioned circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11): 1175-1183 (1998) - [j39]Hai Zhou, D. F. Wong:
Optimal river routing with crosstalk constraints. ACM Trans. Design Autom. Electr. Syst. 3(3): 496-514 (1998) - [j38]Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong:
Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing. VLSI Design 7(1): 73-84 (1998) - [c92]Hai Zhou, D. F. Wong:
Global Routing with Crosstalk Constraints. DAC 1998: 374-377 - [c91]Madhukar R. Korupolu, K. K. Lee, D. F. Wong:
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs. DAC 1998: 708-711 - [c90]Chris C. N. Chu, D. F. Wong:
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. DATE 1998: 479-485 - [c89]Huiqun Liu, Kai Zhu, D. F. Wong:
Circuit Partitioning with Complex Resource Constraints in FPGAs. FPGA 1998: 77-84 - [c88]Wai-Kei Mak, D. F. Wong:
Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). FPGA 1998: 260 - [c87]Yao-Wen Chang, Jai-Ming Lin, D. F. Wong:
Graph matching-based algorithms for FPGA segmentation design. ICCAD 1998: 34-39 - [c86]Fung Yu Young, D. F. Wong:
Slicing floorplans with pre-placed modules. ICCAD 1998: 252-258 - [c85]Huiqun Liu, D. F. Wong:
Network flow based circuit partitioning for time-multiplexed FPGAs. ICCAD 1998: 497-504 - [c84]Youxin Gao, D. F. Wong:
Shaping a VLSI wire to minimize delay using transmission line model. ICCAD 1998: 611-616 - [c83]Chung-Ping Chen, Chris C. N. Chu, D. F. Wong:
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. ICCAD 1998: 617-624 - [c82]Wai-Kei Mak, D. F. Wong:
Performance-driven board-level routing for FPGA-based logic emulation. ICCD 1998: 199-201 - [c81]Huiqun Liu, D. F. Wong:
Integrated partitioning and scheduling for hardware/software co-design. ICCD 1998: 609-614 - [c80]Kai Zhu, Yao-Wen Chang, D. F. Wong:
Timing-driven routing for symmetrical-array-based FPGAs. ICCD 1998: 628-633 - [c79]Chris C. N. Chu, D. F. Wong:
Greedy wire-sizing is linear time. ISPD 1998: 39-44 - 1997
- [j37]F. Y. Young, D. F. Wong:
How good are slicing floorplans? Integr. 23(1): 61-73 (1997) - [j36]Yao-Ping Chen, D. F. Wong:
On retiming for FPGA logic module minimization. Integr. 24(2): 135-145 (1997) - [j35]Yao-Ping Chen, D. F. Wong:
A graph theoretic approach to feed-through pin assignment. Integr. 24(2): 147-158 (1997) - [j34]Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan:
Algorithms for an FPGA switch module routing problem with application to global routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 32-46 (1997) - [j33]Wai-Kei Mak, Martin D. F. Wong:
On optimal board-level routing for FPGA-based logic emulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3): 282-289 (1997) - [j32]Kai Zhu, Martin D. F. Wong:
Clock skew minimization during FPGA placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(4): 376-385 (1997) - [j31]T. W. Her, Martin D. F. Wong:
Module implementation selection and its application to transistor placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(6): 645-651 (1997) - [j30]Hannah Honghua Yang, Martin D. F. Wong:
Circuit clustering for delay minimization under area and pin constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9): 976-986 (1997) - [j29]Wai-Kei Mak, Martin D. F. Wong:
Minimum replication min-cut partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10): 1221-1227 (1997) - [j28]Wai-Kei Mak, D. F. Wong:
Board-level multiterminal net routing for FPGA-based logic emulation. ACM Trans. Design Autom. Electr. Syst. 2(2): 151-167 (1997) - [c78]John F. Croix, D. F. Wong:
A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis. DAC 1997: 337-340 - [c77]Chung-Ping Chen, D. F. Wong:
Optimal Wire-Sizing Function with Fringing Capacitance Consideration. DAC 1997: 604-607 - [c76]Hai Zhou, D. F. Wong:
An exact gate decomposition algorithm for low-power technology mapping. ICCAD 1997: 575-580 - [c75]Chris C. N. Chu, D. F. Wong:
A new approach to simultaneous buffer insertion and wire sizing. ICCAD 1997: 614-621 - [c74]Youxin Gao, D. F. Wong:
Optimal shape function for a bi-directional wire under Elmore delay model. ICCAD 1997: 622-627 - [c73]Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi:
Clustering and Load Balancing for Buffered Clock Tree Synthesis. ICCD 1997: 217-223 - [c72]Fung Yu Young, D. F. Wong:
On the Construction of Universal Series-Parallel Functions for Logic Module Design. ICCD 1997: 482-488 - [c71]Wai-Kei Mak, D. F. Wong:
Channel Segmentation Design for Symmentrical FPGAs. ICCD 1997: 496-501 - [c70]Hai Zhou, D. F. Wong:
Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation. ICCD 1997: 628-633 - [c69]Huiqun Liu, D. F. Wong:
Network flow based multi-way partitioning with area and pin constraints. ISPD 1997: 12-17 - [c68]Fung Yu Young, D. F. Wong:
How good are slicing floorplans?. ISPD 1997: 144-149 - [c67]Chris C. N. Chu, D. F. Wong:
A matrix synthesis approach to thermal placement. ISPD 1997: 163-168 - [c66]Chris C. N. Chu, D. F. Wong:
Closed form solution to simultaneous buffer insertion/sizing and wire sizing. ISPD 1997: 192-197 - 1996
- [j27]Shashidhar Thakur, D. F. Wong:
Simultaneous area and delay minimum K-LUT mapping for K-exact networks. Integr. 20(3): 287-302 (1996) - [j26]Glenn G. Lai, Donald S. Fussell, Martin D. F. Wong:
Hinted quad trees for VLSI geometry DRC based on efficient searching for neighbors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(3): 317-324 (1996) - [j25]Mohankumar Guruswamy, Martin D. F. Wong:
Echelon: a multilayer detailed area router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1126-1136 (1996) - [j24]Hannah Honghua Yang, Martin D. F. Wong:
Balanced partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1533-1540 (1996) - [j23]Yao-Wen Chang, D. F. Wong, C. K. Wong:
Universal switch modules for FPGA design. ACM Trans. Design Autom. Electr. Syst. 1(1): 80-101 (1996) - [j22]Shashidhar Thakur, D. F. Wong:
Series-parallel functions and FPGA logic module design. ACM Trans. Design Autom. Electr. Syst. 1(1): 102-122 (1996) - [c65]Shashidhar Thakur, D. F. Wong, Shankar Krishnamoorthy:
Delay Minimal Decomposition of Multiplexers in Technology Mapping. DAC 1996: 254-257 - [c64]Chung-Ping Chen, Yao-Wen Chang, D. F. Wong:
Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation. DAC 1996: 405-408 - [c63]Chung-Ping Chen, Yao-Ping Chen, D. F. Wong:
Optimal Wire-Sizing Formular Under the Elmore Delay Model. DAC 1996: 487-490 - [c62]Y. P. Chen, D. F. Wong:
An Algorithm for Zero-Skew Clock Tree Routing with Buffer Insertion. ED&TC 1996: 230-236 - [c61]Shashidhar Thakur, D. F. Wong:
Universal Logic Modules for Series-Parallel Functions. FPGA 1996: 31-37 - [c60]Yao-Wen Chang, D. F. Wong, C. K. Wong:
Universal Switch-Module Design for Symmetric-Array-Based FPGAs. FPGA 1996: 80-86 - [c59]Chung-Ping Chen, Hai Zhou, D. F. Wong:
Optimal non-uniform wire-sizing under the Elmore delay model. ICCAD 1996: 38-43 - [c58]Wai-Kei Mak, D. F. Wong:
Minimum replication min-cut partitioning. ICCAD 1996: 205-210 - [c57]Hai Zhou, D. F. Wong:
An optimal algorithm for river routing with crosstalk constraints. ICCAD 1996: 310-315 - [c56]Yung-Ming Fang, D. F. Wong:
Multiplexor Network Generation in High Level Synthesis. ICCD 1996: 78-83 - 1995
- [j21]Ting-Chi Wang, Martin D. F. Wong, Yachyang Sun, Chak-Kuen Wong:
Optimal net assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 265-269 (1995) - [j20]T. W. Her, Martin D. F. Wong:
On over-the-cell channel routing with cell orientations consideration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 766-772 (1995) - [j19]T. W. Her, Ting-Chi Wang, Martin D. F. Wong:
Performance-driven channel pin assignment algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7): 849-857 (1995) - [j18]Rajmohan Rajaraman, Martin D. F. Wong:
Optimum clustering for delay minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1490-1495 (1995) - [c55]Wai-Kei Mak, D. F. Wong:
On Optimal Board-Level Routing for FPGA-Based Logic Emulation. DAC 1995: 552-556 - [c54]Honghua Yang, D. F. Wong:
Circuit clustering for delay minimization under area and pin constraints. ED&TC 1995: 65-70 - [c53]Shashidhar Thakur, D. F. Wong:
On Designing ULM-based FPGA Logic Modules. FPGA 1995: 3-9 - [c52]Hannah Honghua Yang, D. F. Wong:
New algorithms for min-cut replication in partitioned circuits. ICCAD 1995: 216-222 - [c51]Wai-Kei Mak, D. F. Wong:
Board-level multi-terminal net routing for FPGA-based logic emulation. ICCAD 1995: 339-344 - [c50]Kai-Yuan Chao, D. F. Wong:
Signal integrity optimization on the pad assignment for high-speed VLSI design. ICCAD 1995: 720-725 - [c49]Kai-Yuan Chao, D. F. Wong:
Thermal placement for high-performance multichip modules. ICCD 1995: 218-223 - [c48]Yao-Wen Chang, D. F. Wong, C. K. Wong:
FPGA global routing based on a new congestion metric. ICCD 1995: 372-378 - [c47]Yao-Wen Chang, D. F. Wong, C. K. Wong:
Design and analysis of FPGA/FPIC switch modules. ICCD 1995: 394-401 - [c46]Shashidhar Thakur, D. F. Wong:
Simultaneous area and delay minimum K-LUT mapping for K-exact networks. ICCD 1995: 402-408 - [c45]Kai-Yuan Chao, D. F. Wong:
Floorplanning for Low Power Designs. ISCAS 1995: 45-48 - [c44]Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong:
An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. ISCAS 1995: 207-210 - [c43]Yao-Ping Chen, D. F. Wong:
A Graph Theoretic Approach to Feed-Through Pin Assignment. ISCAS 1995: 1687-1690 - 1994
- [j17]Yang Cai, Martin D. F. Wong:
On shifting blocks and terminals to minimize channel density. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2): 178-186 (1994) - [j16]Yang Cai, D. F. Wong, Jason Cong:
Channel Density Minimization by Pin Permutation. VLSI Design 2(2): 171-183 (1994) - [c42]Kai Zhu, D. F. Wong:
Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAs. DAC 1994: 165-170 - [c41]Kai Zhu, D. F. Wong:
Clock Skew Minimization During FPGA Placement. DAC 1994: 232-237 - [c40]Shashidhar Thakur, D. F. Wong, S. Muthukrishnan:
Algorithms for a switch module routing problem. EURO-DAC 1994: 265-270 - [c39]Honghua Yang, D. F. Wong:
Efficient network flow based min-cut balanced partitioning. ICCAD 1994: 50-55 - [c38]Hannah Honghua Yang, D. F. Wong:
Edge-map: optimal performance driven technology mapping for iterative LUT based FPGA designs. ICCAD 1994: 150-155 - [c37]Yung-Ming Fang, D. F. Wong:
Simultaneous functional-unit binding and floorplanning. ICCAD 1994: 317-321 - [c36]Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong:
A new global routing algorithm for FPGAs. ICCAD 1994: 356-361 - [c35]Kai-Yuan Chao, D. F. Wong:
Layer assignment for high-performance multi-chip modules. ICCAD 1994: 680-685 - [c34]Yao-Ping Chen, D. F. Wong:
On Retiming for FPGA Logic Module Minimization. ICCD 1994: 394-397 - [c33]T. W. Her, D. F. Wong:
Over-the-Cell Routing with Cell Orientations Consideration. ISCAS 1994: 471-474 - 1993
- [j15]Ting-Chi Wang, D. F. Wong:
Graph-based techniques to speed up floorplan area optimization. Integr. 15(2): 179-199 (1993) - [j14]Yang Cai, Martin D. F. Wong:
On minimizing the number of L-shaped channels in building-block layout [VLSI]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(6): 757-769 (1993) - [j13]Yang Cai, Martin D. F. Wong:
Efficient via shifting algorithms in channel compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12): 1848-1857 (1993) - [c32]Glenn G. Lai, Donald S. Fussell, D. F. Wong:
HV/VH Trees: A New Spatial Data Structure for Fast Region Queries. DAC 1993: 43-47 - [c31]Rajmohan Rajaraman, D. F. Wong:
Optimal Clustering for Delay Minimization. DAC 1993: 309-314 - [c30]Ting-Chi Wang, D. F. Wong, Yachyang Sun, C. K. Wong:
On over-the-cell channel routing. EURO-DAC 1993: 110-115 - [c29]T. W. Her, D. F. Wong:
Cell area minimization by transistor folding. EURO-DAC 1993: 172-177 - [c28]Kai Zhu, D. F. Wong:
Fast Boolean matching for field-programmable gate arrays. EURO-DAC 1993: 352-357 - [c27]Kai Zhu, D. F. Wong, Yao-Wen Chang:
Switch module design with application to two-dimensional segmentation design. ICCAD 1993: 480-485 - [c26]Yao-Ping Chen, Ting-Chi Wang, D. F. Wong:
A Graph Partitioning Problem for Multiple-chip Design. ISCAS 1993: 1778-1781 - [c25]Yao-Ping Chen, D. F. Wong:
On optimal approximation of orthogonal polygons. ISCAS 1993: 2533-2536 - [p1]Ting-Chi Wang, D. F. Wong:
A note on the Complexity of Stockmeyer's floorplan Optimization Technique. Algorithmic Aspects of VLSI Layout 1993: 309-320 - 1992
- [j12]Ting-Chi Wang, Martin D. F. Wong:
Optimal floorplan area optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(8): 992-1002 (1992) - [j11]Shinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell:
Topological channel routing [VLSI]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(10): 1177-1197 (1992) - [c24]Ting-Chi Wang, D. F. Wong:
A Graph Theoretic Technique to Speed up Floorplan Area Optimization. DAC 1992: 62-68 - [c23]Kai Zhu, D. F. Wong:
On channel segmentation design for row-based FPGAs. ICCAD 1992: 26-29 - [c22]Yang Cai, D. F. Wong:
Channel Density Minimization by Pin Permutation. ICCD 1992: 378-382 - 1991
- [j10]D. F. Wong, Edward M. Reingold:
Probabilistic Analysis of a Grouping Algorithm. Algorithmica 6(2): 192-206 (1991) - [j9]Khe-Sing The, Martin D. F. Wong, Jason Cong:
A layout modification approach to via minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4): 536-541 (1991) - [j8]Yang Cai, Martin D. F. Wong:
Optimal channel pin assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(11): 1413-1424 (1991) - [j7]Martin D. F. Wong, Mohankumar Guruswamy:
Channel ordering for VLSI layout with rectilinear modules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(11): 1425-1431 (1991) - [j6]Yang Cai, Martin D. F. Wong:
Channel/switchbox definition for VLSI building-block layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(12): 1485-1493 (1991) - [c21]Yang Cai, D. F. Wong:
On Minimizing the Number of L-Shaped Channels. DAC 1991: 328-334 - [c20]Mohankumar Guruswamy, D. F. Wong:
A General Multi-Layer Area Router. DAC 1991: 335-340 - [c19]Ting-Chi Wang, D. F. Wong:
Efficient shape curve construction in floorplan design. EURO-DAC 1991: 356-360 - [c18]T. W. Her, D. F. Wong:
Optimal Module Implementation and Its Application to Transistor Placement. ICCAD 1991: 98-101 - [c17]Yang Cai, D. F. Wong:
Minimizing Channel Density by Shifting Blocks and Terminals. ICCAD 1991: 524-527 - [c16]John C. Chan, Baxter F. Womack, D. F. Wong:
On the Manisfestation of Faults to Errors in Signature Analysis. ICCD 1991: 360-363 - [c15]Khe-Sing The, D. F. Wong:
Area Optimization for Higher Order Hierarchical Floorplans. ICCD 1991: 520-523 - 1990
- [j5]Jingsheng Cong, D. F. Wong:
Generating more compactable channel routing solutions. Integr. 9(2): 199-214 (1990) - [c14]Ting-Chi Wang, D. F. Wong:
An Optimal Algorithm for Floorplan Area Optimization. DAC 1990: 180-186 - [c13]Yang Cai, D. F. Wong:
A Channel/Switchbox Definition Algorithm for Building-Block Layout. DAC 1990: 638-641 - [c12]Yang Cai, D. F. Wong:
Optimal via-shifting in channel compaction. EURO-DAC 1990: 186-190 - [c11]Shinichiro Haruyama, D. F. Wong, Donald S. Fussell:
Topological Routing Using Geometric Information. ICCAD 1990: 6-9 - [c10]Yang Cai, D. F. Wong:
An Optimal Channel Pin Assignment Algorithm. ICCAD 1990: 10-13 - [c9]T. W. Her, D. F. Wong, T. H. Freeman:
Optimal Orientations of Transistor Chains. ICCAD 1990: 524-527
1980 – 1989
- 1989
- [j4]D. F. Wong, C. L. Liu:
Floorplan Design of VLSI Circuits. Algorithmica 4(2): 263-291 (1989) - [j3]Thomas R. Mueller, D. F. Wong, C. L. Liu:
An enhanced bottom-up algorithm for floorplan design. Integr. 7(2): 189-201 (1989) - [c8]D. F. Wong, P. S. Sakhamuri:
Efficient Floorplan Area Optimization. DAC 1989: 586-589 - [c7]Khe-Sing The, D. F. Wong, Jason Cong:
VIA Minimization by Layout Modification. DAC 1989: 799-802 - [c6]D. F. Wong, Khe-Sing The:
An algorithm for hierarchical floorplan design. ICCAD 1989: 484-487 - 1988
- [j2]Jason Cong, Martin D. F. Wong, C. L. Liu:
A new approach to three- or four-layer channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(10): 1094-1104 (1988) - [c5]Jingsheng Cong, D. F. Wong:
How to Obtain More Compactable Channel Routing Solutions. DAC 1988: 663-666 - [c4]Mohankumar Guruswamy, Martin D. F. Wong:
Channel routing order for building-block layout with rectilinear modules. ICCAD 1988: 184-187 - [c3]Shinichiro Haruyama, Martin D. F. Wong, Donald S. Fussell:
Topological channel routing. ICCAD 1988: 406-409 - 1987
- [b1]Martin D. F. Wong:
Algorithmic Aspects of Vlsi Circuit Layout (Channel Routing, Logic Array). University of Illinois Urbana-Champaign, USA, 1987 - [c2]D. F. Wong, C. L. Liu:
Array Optimization for VLSI Synthesis. DAC 1987: 537-543 - 1986
- [j1]D. F. Wong, C. L. Liu:
Compacted channel routing with via placement restrictions. Integr. 4(4): 287-307 (1986) - [c1]D. F. Wong, C. L. Liu:
A new algorithm for floorplan design. DAC 1986: 101-107
Coauthor Index
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