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2020 – today
- 2021
[c26]Ravi Ledalla, Debjit Sinha, Adil Bhanji, Chaobo Li, Gregory Schaeffer, Hemlata Gupta, Jennifer Basile:
Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure. DATE 2021: 1558-1563- 2020
- [c25]Debjit Sinha, Vasant Rao, Chaitanya Peddawad, Michael H. Wood, Jeffrey G. Hemmett, Suriya Skariah, Patrick Williams:
Statistical Timing Analysis considering Multiple-Input Switching. DAC 2020: 1-6
2010 – 2019
- 2016
- [c24]Debjit Sinha, Vladimir Zolotov, Sheshashayee K. Raghunathan, Michael H. Wood, Kerim Kalafala:
Practical statistical static timing analysis with current source models. DAC 2016: 113:1-113:6 - [c23]Vasant Rao, Debjit Sinha, Nitin Srimal, Prabhat K. Maurya:
Statistical path tracing in timing graphs. DAC 2016: 114:1-114:6 - [c22]Tsung-Wei Huang, Martin D. F. Wong
, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran:
A distributed timing analysis framework for large designs. DAC 2016: 116:1-116:6 - [c21]Debjit Sinha, Vladimir Zolotov, Jin Hu, Sheshashayee K. Raghunathan, Adil Bhanji, Christine M. Casey:
Generation and use of statistical timing macro-models considering slew and load variability. ICCAD 2016: 98 - [c20]Debjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael H. Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma:
Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains. VLSID 2016: 493-498 - 2014
- [c19]Jin Hu, Debjit Sinha, Igor Keller:
TAU 2014 contest on removing common path pessimism during timing analysis. ICCAD 2014: 591 - [c18]Jin Hu, Debjit Sinha, Igor Keller:
TAU 2014 contest on removing common path pessimism during timing analysis. ISPD 2014: 153-160 - 2013
- [c17]Vimitha A. Kuruvilla, Debjit Sinha, Jeff Piaget, Chandu Visweswariah, Nitin Chandrachoodan:
Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization. DAC 2013: 182:1-182:7 - [c16]Debjit Sinha, Luís Guerra e Silva, Jia Wang, Shesha Raghunathan, Dileep Netrabile, Ahmed Shebaita:
TAU 2013 variation aware timing analysis contest. ISPD 2013: 171-178 - 2012
- [c15]Vladimir Zolotov, Debjit Sinha, Jeffrey G. Hemmett, Eric A. Foreman, Chandu Visweswariah, Jinjun Xiong, Jeremy Leitzen, Natesan Venkateswaran:
Timing analysis with nonseparable statistical and deterministic variations. DAC 2012: 1061-1066 - [c14]Debjit Sinha, Chandu Visweswariah, Natesan Venkateswaran, Jinjun Xiong, Vladimir Zolotov:
Reversible statistical max/min operation: concept and applications to timing. DAC 2012: 1067-1073
2000 – 2009
- 2009
- [j7]Debjit Sinha, Alex Rubin, Chandu Visweswariah, Frank Borkam, Gregory Schaeffer, Soroush Abbaspour:
Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 1096-1100 (2009) - [j6]DiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail:
A Timing-Dependent Power Estimation Framework Considering Coupling. IEEE Trans. Very Large Scale Integr. Syst. 17(6): 843-847 (2009) - 2008
- [c13]Peter Feldmann, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta:
Driver waveform computation for timing analysis with multiple voltage threshold driver models. DAC 2008: 425-428 - [c12]Debjit Sinha, Gregory Schaeffer, Soroush Abbaspour, Alex Rubin, Frank Borkam:
Constrained aggressor set selection for maximum coupling noise. ICCAD 2008: 790-796 - 2007
- [j5]Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou:
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 447-455 (2007) - [j4]Debjit Sinha, Hai Zhou, Narendra V. Shenoy:
Advances in Computation of the Maximum of a Set of Gaussian Random Variables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1522-1533 (2007) - [c11]Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou:
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design 2007: 875-880 - 2006
- [j3]Debjit Sinha, Hai Zhou:
Gate-size optimization under timing constraints for coupling-noise reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1064-1074 (2006) - [j2]Debjit Sinha, Hai Zhou:
Statistical Timing Analysis With Coupling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2965-2975 (2006) - [j1]Debjit Sinha, Narendra V. Shenoy, Hai Zhou:
Statistical Timing Yield Optimization by Gate Sizing. IEEE Trans. Very Large Scale Integr. Syst. 14(10): 1140-1146 (2006) - [c10]Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou:
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. DATE 2006: 618-623 - [c9]Debjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou:
A timing dependent power estimation framework considering coupling. ICCAD 2006: 401-407 - [c8]Debjit Sinha, Hai Zhou, Narendra V. Shenoy:
Advances in Computation of the Maximum of a Set of Random Variables. ISQED 2006: 306-311 - [c7]Serkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou:
Yield-Aware Cache Architectures. MICRO 2006: 15-25 - 2005
- [c6]Debjit Sinha, Hai Zhou:
Yield driven gate sizing for coupling-noise reduction under uncertainty. ASP-DAC 2005: 192-197 - [c5]Debjit Sinha, Hai Zhou:
A unified framework for statistical timing analysis with coupling and multiple input switching. ICCAD 2005: 837-843 - [c4]Debjit Sinha, Narendra V. Shenoy, Hai Zhou:
Statistical gate sizing for timing yield optimization. ICCAD 2005: 1037-1041 - 2004
- [c3]Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee:
An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. FPGA 2004: 256 - [c2]Debjit Sinha, Hai Zhou:
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. ICCAD 2004: 14-19 - [c1]Debjit Sinha, Hai Zhou, Chris C. N. Chu:
Optimal gate sizing for coupling-noise reduction. ISPD 2004: 176-181
Coauthor Index
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