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ORCIDISPD 2013: Stateline, NV, USA
- Cheng-Kok Koh, Cliff C. N. Sze:
International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 2013. ACM 2013, ISBN 978-1-4503-1954-6
Welcome and keynote address
- Liam Madden:
Heterogeneous 3-d stacking, can we have the best of both (technology) worlds? 1-2
3D integration and physical planning
- Jordi Cortadella
, Javier de San Pedro, Nikita Nikitin, Jordi Petit:
Physical-aware system-level design for tiled hierarchical chip multiprocessors. 3-10 - Robert Fischbach, Johann Knechtel, Jens Lienig:
Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems. 11-16 - Pei-Wen Luo, Chun Zhang, Yung-Tai Chang, Liang-Chia Cheng, Hung-Hsie Lee, Bih-Lan Sheu, Yu-Shih Su, Ding-Ming Kwai, Yiyu Shi:
Benchmarking for research in power delivery networks of three-dimensional integrated circuits. 17-24 - David G. Chinnery:
High performance and low power design techniques for ASIC and custom in nanometer technologies. 25-32
Validation and design for yield
- Jens Lienig:
Electromigration and its impact on physical design in future technologies. 33-40 - Li-C. Wang:
Data mining in design and test processes: basic principles and promises. 41-42 - Yang Song, Hao Yu, Sai Manoj Pudukotai Dinakarrao, Guoyong Shi:
SRAM dynamic stability verification by reachability analysis with consideration of threshold voltage variation. 43-49 - Yu-Ming Yang, Iris Hui-Ru Jiang, Sung-Ting Ho:
PushPull: short path padding for timing error resilient circuits. 50-57
Commemoration for Professor Y. Kajitani
- Atsushi Takahashi:
Dawn of computer-aided design: from graph-theory to place and route. 58 - Shigetoshi Nakatake:
Practicality on placement given by optimality of packing. 59-60 - Hung-Ming Chen:
On the way to practical tools for beyond die codesign and integration. 61 - Yoji Kajitani:
Coding the objects in place and route CAD. 62-65
Advanced technologies and design for manufacturability
- James D. Warnock:
Circuit and PD challenges at the 14nm technology node. 66-67 - Shigeki Nojima:
Optical lithography extension with double patterning. 68 - Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada:
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection. 69-76 - Shao-Yun Fang, Chung-Wei Lin, Guang-Wan Liao, Yao-Wen Chang:
Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling. 77-84
Routability and routing
- Hamid Shojaei, Azadeh Davoodi, Jeffrey T. Linderoth:
Planning for local net congestion in global routing. 85-92 - Kan Wang, Huaxi Wang, Sheqin Dong:
Escape routing of mixed-pattern signals based on staggered-pin-array PCBs. 93-100 - Jianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto:
Delay-driven layer assignment in global routing under multi-tier interconnect structure. 101-107 - Xu He, Wing-Kai Chow, Evangeline F. Y. Young:
SRP: simultaneous routing and placement for congestion refinement. 108-113 - Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li:
Case study for placement solutions in ispd11 and dac12 routability-driven placement contests. 114-119
New frontiers for physical design
- Narayan Srinivasa:
A compiler for scalable placement and routing of brain-like architectures. 120-121 - John Giacobbe:
Physical design for debug: insurance policy for IC's. 122 - Kai-Han Tseng, Sheng-Chi You, Jhe-Yu Liou, Tsung-Yi Ho:
A top-down synthesis methodology for flow-based microfluidic biochips considering valve-switching minimization. 123-129 - Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly:
Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure. 130-136
Expert designer/user session (EDS)
- Cliff C. N. Sze, Laleh Behjat, Nikhil Jayakumar, Atul Walimbe, Gregory Ford, Mark Zwolinski, Harish Dangat, Giriraj Kakol:
ISPD 2013 expert designer/user session (eds). 137
Logic, clock driven PD and beyond
- Kenneth S. Stevens:
Relative timing driven multi-synchronous design: enabling order-of-magnitude energy reduction. 138 - Hua Xiang, Minsik Cho, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri:
Network flow based datapath bit slicing. 139-146 - Chang-Cheng Tsai, Yiyu Shi, Guojie Luo, Iris Hui-Ru Jiang:
FF-bond: multi-bit flip-flop bonding at placement. 147-153 - Logan M. Rakai, Amin Farshidi, Laleh Behjat, David T. Westwick:
Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes. 154-161 - Rickard Ewetz, Cheng-Kok Koh:
Local merges for effective redundancy in clock networks. 162-167
TAU/ISPD joint session on contests
- Muhammet Mustafa Ozdal, Chirayu Amin, Andrey Ayupov, Steven M. Burns, Gustavo R. Wilke, Cheng Zhuo:
An improved benchmark suite for the ISPD-2013 discrete cell sizing contest. 168-170 - Debjit Sinha, Luís Guerra e Silva, Jia Wang, Shesha Raghunathan, Dileep Netrabile, Ahmed Shebaita:
TAU 2013 variation aware timing analysis contest. 171-178
TAU/ISPD keynote
- Ruchir Puri:
Opportunities and challenges for high performance microprocessor designs and design automation. 179
TAU/ISPD invited session: what will it take to tame the hierarchical design trolls?
- Florentin Dartu, Qiuyang Wu:
To do or not to do hierarchical timing? 180 - Vidyamani Parkhe:
Variability aware hierarchical implementation of big chips. 181 - Shyam Ramji:
Challenges in managing timing and wiring contracts during hierarchical floorplanning and design closure. 182
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