default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDShigetoshi Nakatake
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2020
[j24]Chao Geng
, Qingji Sun, Shigetoshi Nakatake:
Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks. Sensors 20(15): 4222 (2020)- [c58]Chao Geng, Qingji Sun, Shigetoshi Nakatake:
An Analog CMOS Implementation for Multi-layer Perceptron With ReLU Activation. MOCAST 2020: 1-6 - [c57]Xuncheng Zou, Shigetoshi Nakatake:
A Fully Synthesizable, 0.3V, 10nW Rail-to-rail Dynamic Voltage Comparator. MWSCAS 2020: 199-202
2010 – 2019
- 2019
- [j23]Xuncheng Zou, Shigetoshi Nakatake:
A Low Voltage Stochastic Flash ADC without Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(7): 886-893 (2019) - [j22]Chao Geng, Bo Liu, Shigetoshi Nakatake:
Density Optimization for Analog Layout Based on Transistor-Array. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1720-1730 (2019) - [c56]Xinghuai Zhang, Shigetoshi Nakatake:
On-chip resistance configuration by subthreshold MOSFET-array for ultra weak current sensing. APCCAS 2019: 261-264 - [c55]Ryosuke Sakai, Shigetoshi Nakatake:
An Impedance Measurement of Intravesical Urine Volume Appropriate to Seated Posture. APCCAS 2019: 385-388 - 2018
- [j21]Kenya Kondo, Koichi Tanno, Hiroki Tamura, Shigetoshi Nakatake:
Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(5): 748-754 (2018) - [j20]Yoritaka Ishiguchi, Daishi Isogai, Takuma Osawa, Shigetoshi Nakatake:
Analog perceptron circuit with DAC-based multiplier. Integr. 63: 240-247 (2018) - [j19]Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake:
Routable and Matched Layout Styles for Analog Module Generation. ACM Trans. Design Autom. Electr. Syst. 23(4): 47:1-47:17 (2018) - [c54]Takaaki Shirakawa, Ryosuke Sakai, Shigetoshi Nakatake:
On-chip Impedance Evaluation with Auto-calibration based on Auto-balancing Bridge. MWSCAS 2018: 262-265 - [c53]Chao Geng, Shigetoshi Nakatake:
Hierarchical Floorplanning Based on Analog Structure Tree. NGCAS 2018: 138-141 - [c52]Xuncheng Zou, Shigetoshi Nakatake:
Analog Retargeting Constraint Extraction Based on Fundamental Circuits and Layout Regularity. NGCAS 2018: 142-145 - 2017
- [c51]Xuncheng Zou, Bo Liu, Shigetoshi Nakatake:
Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative Unit. ACM Great Lakes Symposium on VLSI 2017: 435-438 - [c50]Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake:
Overview of the 2017 CAD contest at ICCAD: Invited paper. ICCAD 2017: 855-856 - [c49]Chao Geng, Bo Liu, Shigetoshi Nakatake:
Explicit layout pattern density controlling based on transistor-array-style. MWSCAS 2017: 1557-1560 - [c48]Yoritaka Ishiguchi, Daishi Isogai, Takuma Osawa, Shigetoshi Nakatake:
A Perceptron Circuit with DAC-Based Multiplier for Sensor Analog Front-Ends. NGCAS 2017: 93-96 - [c47]Daishi Isogai, Bo Liu, Yoritaka Ishiguchi, Shigetoshi Nakatake:
Analog Characterization Module with Data Converter-Coupled Signal Reconfiguration. NGCAS 2017: 149-152 - 2016
- [j18]Chooi-Ling Goh, Shigetoshi Nakatake:
A Sensor-Based Data Visualization System for Training Blood Pressure Measurement by Auscultatory Method. IEICE Trans. Inf. Syst. 99-D(4): 936-943 (2016) - [j17]Takuya Hirata, Ryuta Nishino, Shigetoshi Nakatake, Masaya Shimoyama, Masashi Miyagawa, Ryoichi Miyauchi, Koichi Tanno, Akihiro Yamada:
Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent Manufacturability Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1381-1389 (2016) - [j16]Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang:
DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout. ACM Trans. Design Autom. Electr. Syst. 21(3): 45:1-45:21 (2016) - [c46]Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake:
Overview of the 2016 CAD contest at ICCAD. ICCAD 2016: 38 - [c45]Bo Liu, Shigetoshi Nakatake, Bo Yang, Gong Chen:
Twin-row-style for MOS analog layout. ICECS 2016: 141-144 - [c44]Gong Chen, Bo Liu, Shigetoshi Nakatake, Bo Yang:
Routability of twisted common-centroid capacitor array under signal coupling constraints. MWSCAS 2016: 1-4 - [c43]Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen:
A multi-functional memory unit with PLA-based reconfigurable decoder. ReConFig 2016: 1-7 - 2015
- [j15]Gong Chen, Yu Zhang, Qing Dong, Mingyu Li, Shigetoshi Nakatake:
Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1442-1454 (2015) - [c42]Takuya Hirata, Ryuta Nishino, Shigetoshi Nakatake, Masaya Shimoyama, Masashi Miyagawa, Koichi Tanno, Akihiro Yamada:
Subblock-level matching layout for analog block-pair and its manufacturability evaluation. ISCAS 2015: 3012-3015 - [c41]Daijiro Murooka, Yu Zhang, Qing Dong, Shigetoshi Nakatake:
Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning. ISVLSI 2015: 167-171 - 2013
- [j14]Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake:
Structured Analog Circuit and Layout Design with Transistor Array. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2475-2486 (2013) - [j13]Yu Zhang, Gong Chen, Bo Yang, Jing Li, Qing Dong, Mingyu Li, Shigetoshi Nakatake:
Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2487-2498 (2013) - [c40]Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake:
A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm. ACM Great Lakes Symposium on VLSI 2013: 315-316 - [c39]Shigetoshi Nakatake:
Practicality on placement given by optimality of packing. ISPD 2013: 59-60 - [c38]Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake:
A comparator energy model considering shallow trench isolation stress by geometric programming. ISQED 2013: 585-590 - [c37]Yu Zhang, Gong Chen, Qing Dong, Mingyu Li, Shigetoshi Nakatake:
Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects. VLSI-SoC 2013: 156-161 - 2012
- [j12]Bo Liu, Bo Yang, Shigetoshi Nakatake:
Layout-Aware Variability Characterization of CMOS Current Sources. IEICE Trans. Electron. 95-C(4): 696-705 (2012) - [c36]Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue:
A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model. ISCAS 2012: 938-941 - [c35]Yu Zhang, Bo Liu, Bo Yang, Jing Li, Shigetoshi Nakatake:
CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects. ISQED 2012: 464-469 - [c34]Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake:
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications. ISQED 2012: 656-662 - 2011
- [c33]Kota Shinohara, Mihoko Hidaka, Jing Li, Qing Dong, Bo Yang, Shigetoshi Nakatake:
Layout-aware variation evaluation of analog circuits and its validity on op-amp designs. ACM Great Lakes Symposium on VLSI 2011: 247-252 - [c32]Bo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake:
Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis. ISQED 2011: 525-532 - 2010
- [j11]Shigetoshi Nakatake, Masahiro Kawakita, Takao Ito, Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki:
Regularity-Oriented Analog Placement with Conditional Design Rules. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2389-2398 (2010) - [j10]Kokoro Kato, Masakazu Endo, Tadao Inoue, Shigetoshi Nakatake, Masaki Yamabe, Sunao Ishihara:
Photomask Data Prioritization Based on VLSI Design Intent and Its Utilization for Mask Manufacturing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2424-2432 (2010) - [c31]Shigetoshi Nakatake, Masahiro Kawakita, Takao Ito, Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki:
Regularity-oriented analog placement with diffusion sharing and well island generation. ASP-DAC 2010: 305-311 - [c30]Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake:
D-A converter based variation analysis for analog layout design. ASP-DAC 2010: 843-848 - [c29]Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake:
Structured analog circuit design and MOS transistor decomposition for high accuracy applications. ICCAD 2010: 721-728 - [c28]Jing Li, Bo Yang, Qing Dong, Shigetoshi Nakatake:
Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path. ISCAS 2010: 929-932
2000 – 2009
- 2009
- [j9]Bo Yang, Shigetoshi Nakatake:
Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3052-3060 (2009) - [j8]Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake:
Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3103-3110 (2009) - [j7]Qing Dong, Shigetoshi Nakatake:
Structured Placement with Topological Regularity Evaluation. IPSJ Trans. Syst. LSI Des. Methodol. 2: 222-238 (2009) - [c27]Jing Li, Bo Yang, Xiaochuan Hu, Qing Dong, Shigetoshi Nakatake:
STI stress aware placement optimization based on geometric programming. ACM Great Lakes Symposium on VLSI 2009: 209-214 - [c26]Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake:
Incremental buffer insertion and module resizing algorithm using geometric programming. ACM Great Lakes Symposium on VLSI 2009: 413-416 - 2008
- [j6]Bo Yang, Hiroshi Murata, Shigetoshi Nakatake:
A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 542-549 (2008) - [c25]Qing Dong, Shigetoshi Nakatake:
Constraint-free analog placement with topological symmetry structure. ASP-DAC 2008: 186-191 - [c24]Toru Fujimura, Shigetoshi Nakatake:
Transistor-level programmable MOS analog IC with body biasing. ISCAS 2008: 153-156 - [c23]Bo Yang, Shigetoshi Nakatake, Hiroshi Murata:
Fast Shape Optimization of Metallization Patterns for DMOS Based Driver. ISQED 2008: 617-620 - 2007
- [c22]Shigetoshi Nakatake:
Structured Placement with Topological Regularity Evaluation. ASP-DAC 2007: 215-220 - [c21]Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh:
Block placement to ensure channel routability. ACM Great Lakes Symposium on VLSI 2007: 465-468 - 2006
- [j5]Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani:
The Oct-Touched Tile: A New Architecture for Shape-Based Routing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2): 448-455 (2006) - [c20]Keiji Kida, Takehiko Matsuo, Tetsuya Tashiro, Shigetoshi Nakatake:
Sequence-Pair Based Compaction under Equi-Length Constraint. APCCAS 2006: 1015-1018 - [c19]Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani:
Adaptive Porting of Analog IPs with Reusable Conservative Properties. ISVLSI 2006: 18-23 - [c18]Ning Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake:
Multi-SP: A Representation with United Rectangles for Analog Placement and Routing. ISVLSI 2006: 38-43 - [c17]Tan Yan, Shigetoshi Nakatake, Takashi Nojima:
Formulating the Empirical Strategies in Module Generation of Analog MOS Layout. ISVLSI 2006: 44-49 - 2005
- [c16]Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani:
The oct-touched tile: a new architecture for shape-based routing. ACM Great Lakes Symposium on VLSI 2005: 126-129 - 2004
- [c15]Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani:
Abstraction and optimization of consistent floorplanning with pillar block constraints. ASP-DAC 2004: 19-24 - [c14]Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani:
Multi-level placement with circuit schema based clustering in analog IC layouts. ASP-DAC 2004: 406-411 - [c13]Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani:
A device-level placement with multi-directional convex clustering. ACM Great Lakes Symposium on VLSI 2004: 196-201 - [c12]Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, Shigetoshi Nakatake:
A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects. ISCAS (4) 2004: 489-492 - 2003
- [j4]Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita:
An Incremental Wiring Algorithm for VLSI Layout Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(5): 1203-1206 (2003) - 2002
- [j3]Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani:
Consistent floorplanning with hierarchical superconstraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 42-49 (2002) - [c11]Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita:
Chip size estimation based on wiring area. APCCAS (2) 2002: 113-118 - [c10]Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita:
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. ASP-DAC/VLSI Design 2002: 467-472 - 2001
- [c9]Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani:
Consistent floorplanning with super hierarchical constraints. ISPD 2001: 144-149 - 2000
- [c8]Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani:
Self-reforming routing for stochastic search in VLSI interconnection layout. ASP-DAC 2000: 87-92 - [c7]Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake:
Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. VLSI Design 2000: 11
1990 – 1999
- 1998
- [j2]Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani:
Module packing based on the BSG-structure and IC layout applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(6): 519-530 (1998) - [c6]Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani:
Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. ASP-DAC 1998: 571-576 - [c5]Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani:
The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. ICCAD 1998: 267-274 - [c4]Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita:
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. ICCAD 1998: 418-425 - 1996
- [j1]Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani:
VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1518-1524 (1996) - [c3]Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani:
Module placement on BSG-structure and IC layout applications. ICCAD 1996: 484-491 - 1995
- [c2]Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani:
Rectangle-packing-based module placement. ICCAD 1995: 472-479 - 1994
- [c1]Shigetoshi Nakatake, Yoji Kajitani:
Channel-driven global routing with consistent placement (extended abstract). ICCAD 1994: 350-355
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-24 22:53 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
