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ORCIDYoji Kajitani
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2010 – 2019
- 2016
[r2]Yoji Kajitani:
Floorplan and Placement. Encyclopedia of Algorithms 2016: 761-766- 2013
- [j23]Ching-Yu Chin, Chung-Yi Kuan, Tsung-Ying Tsai, Hung-Ming Chen, Yoji Kajitani:
Escaped Boundary Pins Routing for High-Speed Boards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 381-391 (2013) - [c42]Yoji Kajitani:
Coding the objects in place and route CAD. ISPD 2013: 62-65 - 2011
- [c41]Tsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi Kuan, Hung-Ming Chen, Yoji Kajitani:
On routing fixed escaped boundary pins for high speed boards. DATE 2011: 461-466
2000 – 2009
- 2008
- [r1]Yoji Kajitani:
Floorplan and Placement. Encyclopedia of Algorithms 2008 - 2007
- [j22]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani:
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(5): 924-931 (2007) - 2006
- [j21]Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani:
The Oct-Touched Tile: A New Architecture for Shape-Based Routing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2): 448-455 (2006) - [c40]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani:
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os. FPT 2006: 361-364 - [c39]Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani:
How does partitioning matter for 3D floorplanning? ACM Great Lakes Symposium on VLSI 2006: 73-78 - [c38]Yoji Kajitani:
Theory of placement by numDAG related with single-sequence, SP, BSG, and O-tree. ISCAS 2006 - [c37]Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani:
Adaptive Porting of Analog IPs with Reusable Conservative Properties. ISVLSI 2006: 18-23 - 2005
- [j20]Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi:
Equidistance routing in high-speed VLSI layout design. Integr. 38(3): 439-449 (2005) - [c36]Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani:
The oct-touched tile: a new architecture for shape-based routing. ACM Great Lakes Symposium on VLSI 2005: 126-129 - [c35]Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani:
A new approach based on LFF for optimization of dynamic hardware reconfigurations. ISCAS (2) 2005: 1210-1213 - [c34]Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani:
Fixed-outline floorplanning with constraints through instance augmentation. ISCAS (2) 2005: 1883-1886 - 2004
- [c33]Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani:
Abstraction and optimization of consistent floorplanning with pillar block constraints. ASP-DAC 2004: 19-24 - [c32]Xuliang Zhang, Yoji Kajitani:
Space-planning: placement of modules with controlled empty area by single-sequence. ASP-DAC 2004: 25-30 - [c31]Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani:
Multi-level placement with circuit schema based clustering in analog IC layouts. ASP-DAC 2004: 406-411 - [c30]Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani:
A device-level placement with multi-directional convex clustering. ACM Great Lakes Symposium on VLSI 2004: 196-201 - [c29]Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi:
Equidistance routing in high-speed VLSI layout design. ACM Great Lakes Symposium on VLSI 2004: 220-223 - [c28]Xuliang Zhang, Yoji Kajitani:
Theory of T-junction floorplans in terms of single-sequence. ISCAS (5) 2004: 341-344 - 2003
- [j19]Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita:
An Incremental Wiring Algorithm for VLSI Layout Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(5): 1203-1206 (2003) - [c27]Changwen Zhuang, Keishi Sakanushi, Liyan Jin, Yoji Kajitani:
An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost. ASP-DAC 2003: 338-341 - 2002
- [j18]Kengo R. Azegami, Masato Inagi, Atsushi Takahashi, Yoji Kajitani:
An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(3): 655-663 (2002) - [j17]Keishi Sakanushi, Zhonglin Wu, Yoji Kajitani:
Recognition of Floorplan by Parametric BSG for Reuse of Layout Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(4): 872-879 (2002) - [j16]Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani:
Consistent floorplanning with hierarchical superconstraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 42-49 (2002) - [c26]Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita:
Chip size estimation based on wiring area. APCCAS (2) 2002: 113-118 - [c25]Hiroshi Miyashita, Yoji Kajitani:
On the equivalence of the sequence pair for rectangle packing to the dimension of partial orders [floorplanning]. APCCAS (2) 2002: 367-370 - [c24]Changwen Zhuang, Yoji Kajitani, Keishi Sakanushi, Liyan Jin:
An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. DATE 2002: 61-68 - [c23]Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita:
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. ASP-DAC/VLSI Design 2002: 467-472 - 2001
- [c22]Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani:
Consistent floorplanning with super hierarchical constraints. ISPD 2001: 144-149 - 2000
- [c21]Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani:
Self-reforming routing for stochastic search in VLSI interconnection layout. ASP-DAC 2000: 87-92 - [c20]Yoji Kajitani, Atsushi Takahashi
, Kengo R. Azegami, Shigetoshi Nakatake:
Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. VLSI Design 2000: 11
1990 – 1999
- 1999
- [c19]Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani:
Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. ASP-DAC 1999: 125- - 1998
- [j15]Magnús M. Halldórsson, Shuichi Ueno, Hiroshi Nakao, Yoji Kajitani:
Approximating Steiner trees in graphs with restricted weights. Networks 31(4): 283-292 (1998) - [j14]Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani:
Module packing based on the BSG-structure and IC layout applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(6): 519-530 (1998) - [c18]Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani:
Air-Pressure-Model-Based Fast Algorithms for General Floorplan. ASP-DAC 1998: 563-570 - [c17]Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani:
Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. ASP-DAC 1998: 571-576 - [c16]Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani:
The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. ICCAD 1998: 267-274 - [c15]Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita:
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. ICCAD 1998: 418-425 - 1997
- [j13]Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu:
Design of minimum and uniform bipartites for optimum connection blocks of FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1377-1383 (1997) - [c14]Atsushi Takahashi, Yoji Kajitani:
Performance and reliability driven clock scheduling of sequential logic circuits. ASP-DAC 1997: 37-42 - [c13]Hiroshi Murata, Kunihiro Fujiyoshi, Tomomi Watanabe, Yoji Kajitani:
A mapping from sequence-pair to rectangular dissection. ASP-DAC 1997: 625-633 - [c12]Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani:
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. ICCAD 1997: 260-265 - 1996
- [j12]Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani:
VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1518-1524 (1996) - [c11]Yasuhiro Takashima, Atsushi Takahashi, Yoji Kajitani:
Detailed-Routability of FPGAs with Extremal Switch-Block Structures. ED&TC 1996: 160-164 - [c10]Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani:
Module placement on BSG-structure and IC layout applications. ICCAD 1996: 484-491 - 1995
- [j11]Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani:
Mixed Searching and Proper-Path-Width. Theor. Comput. Sci. 137(2): 253-268 (1995) - [c9]Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani:
Rectangle-packing-based module placement. ICCAD 1995: 472-479 - 1994
- [j10]Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani:
Minimal acyclic forbidden minors for the family of graphs with bounded path-width. Discret. Math. 127(1-3): 293-304 (1994) - [c8]Shigetoshi Nakatake, Yoji Kajitani:
Channel-driven global routing with consistent placement (extended abstract). ICCAD 1994: 350-355 - [c7]Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu:
The Totally-Perfect Bipartite Graph and Its Construction. ISAAC 1994: 541-549 - [c6]Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu:
Design of Optimum Totally Perfect Connection-Blocks of FPGA. ISCAS 1994: 221-224 - [c5]Yoji Kajitani, Jun Dong Cho, Majid Sarrafzadeh:
New Approximation Results on Graph Matching and related Problems. WG 1994: 343-358 - 1993
- [j9]Tadashi Arai, Shuichi Ueno, Yoji Kajitani:
Generalization of aTheorem on the Parametric Maximum Flow Problem. Discret. Appl. Math. 41(1): 69-74 (1993) - [c4]Wayne Wei-Ming Dai, Yoji Kajitani, Yorihiko Hirata:
Optimal single hop multiple bus networks. ISCAS 1993: 2541-2544 - [p1]Toshihiko Takahashi, Yoji Kajitani:
The Virtual Dimensions of a Straight Line Embedding of a plane Graph. Algorithmic Aspects of VLSI Layout 1993: 357-363 - 1992
- [j8]Atsushi Takahashi, Yoji Kajitani:
Peel-the-box: a concept of switch-box routing and tractable problems. Integr. 14(1): 33-47 (1992) - 1991
- [c3]Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani:
Mixed-Searching and Proper-Path-Width. ISA 1991: 61-71
1980 – 1989
- 1988
- [j7]Yoji Kajitani, Shuichi Ueno, Hiroshi Miyano:
Ordering of the elements of a matroid such that its consecutive w elements are independent. Discret. Math. 72(1-3): 187-194 (1988) - [j6]Shuichi Ueno, Yoji Kajitani, Shin'ya Gotoh:
On the nonseparating independent set problem and feedback set problem for graphs with no vertex degree exceeding three. Discret. Math. 72(1-3): 355-360 (1988) - [j5]Shuichi Ueno, Yoji Kajitani, Hajime Wada:
Minimum augmentation of a tree to a K-edge-connected graph. Networks 18(1): 19-25 (1988) - 1986
- [j4]Yoji Kajitani, Akio Ishizuka, Shuichi Ueno:
Characterization of partial 3-trees in terms of three structures. Graphs Comb. 2(1): 233-246 (1986) - [j3]Yoji Kajitani, Shuichi Ueno:
The minimum augmentation of a directed tree to a k-edge-connected directed graph. Networks 16(2): 181-197 (1986) - 1984
- [j2]Yoji Kajitani, Shuichi Ueno:
A matroid generalization of theorems of Lewin and Gallai. Discret. Appl. Math. 9(2): 213-216 (1984) - [c2]Rachel R. Chen, Yoji Kajitani:
The channel expansion problem in layout design. DAC 1984: 388-391 - 1983
- [j1]Yoji Kajitani:
Order of Channels for Safe Routing and Optimal Compaction of Routing Area. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(4): 293-300 (1983)
1970 – 1979
- 1979
- [c1]Tatsuya Kawamoto, Yoji Kajitani:
The minimum width routing of A 2-row 2-layer polycell-layout. DAC 1979: 290-296
Coauthor Index
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