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2020 – today
- 2024
[j56]Cheng-Kai Yao
, Chun-Hsiang Peng, Hung-Ming Chen, Wen-Yang Hsu, Tzu-Chiao Lin, Yibeltal Chanie Manie, Peng-Chun Peng:
One Raman DTS Interrogator Channel Supports a Dual Separate Path to Realize Spatial Duplexing. Sensors 24(16): 5277 (2024)- [c115]Cheng-Chen Lin, Wei Lu, Po-Tsang Huang, Hung-Ming Chen:
A 28nm 343.5fps/W Vision Transformer Accelerator with Integer-Only Quantized Attention Block. AICAS 2024: 80-84 - [c114]Wei Lu, Han-Hsiang Pei, Jheng-Rong Yu, Hung-Ming Chen, Po-Tsang Huang:
A 28nm Energy-Area-Efficient Row-based pipelined Training Accelerator with Mixed FXP4/FP16 for On-Device Transfer Learning. ISCAS 2024: 1-5 - [c113]Hung-Ming Chen:
Enabling System Design in 3D Integration: Technologies and Methodologies. ISPD 2024: 217 - [c112]Bo-Han Li, Kuan-Chih Lin, Hao Zuo, Po-Cheng Pan, Hung-Ming Chen, Shyh-Jye Jou, Chien-Nan Jimmy Liu, Bo-Cheng Lai:
Efficient Analog Layout Generation for In-RRAM Computing Circuits via Area and Wire Optimization. MWSCAS 2024: 1085-1090 - [c111]Bo-Kai Kang, Hao-Ju Chang, Hung-Ming Chen, Chien-Nan Jimmy Liu:
ML/DL-Based Signal Integrity Optimization for InFO Routing. NewCAS 2024: 343-347 - [c110]Shih-Han Chang, Shih-Yu Chen, Chun-Wen Yang, Hau-Wei Huang, Yu-Cheng Yang, Wei-Liang Chen, Chien-Nan Liu, Hung-Ming Chen:
Mitigating Power and Process Variation for Analog CIM Design Migration. SMACD 2024: 1-4 - [c109]Wei Lu, Jie Zhang, Yi-Hui Wei, Hsu-Ming Hsiao, Sih-Han Li, Chao-Kai Hsu, Chih-Cheng Hsiao, Feng-Hsiang Lo, Shyh-Shyuan Sheu, Chin-Hung Wang, Wei-Chung Lo, Shih-Chieh Chang, Hung-Ming Chen, Kuan-Neng Chen, Po-Tsang Huang:
Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology. VLSI Technology and Circuits 2024: 1-2 - [c108]Bo-Jheng Shih, Yu-Ming Pan, Hao-Tung Chung, Chieh-Ling Lee, I-Chun Hsieh, Nein-Chih Lin, Chih-Chao Yang, Po-Tsang Huang, Hung-Ming Chen, Chiao-Yen Wang, Huan-Yu Chiu, Huang-Chung Cheng, Chang-Hong Shen, Wen-Fa Wu, Tuo-Hung Hou, Kuan-Neng Chen, Chenming Hu:
3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j55]Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin, Guan-Qi Fang, Simon Yi-Hung Chen:
Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(1): 266-279 (2023) - [j54]A. K. Thasreefa, Abhishek Patyal, Hao-Yu Chi, Mark Po-Hung Lin, Hung-Ming Chen:
On Reducing LDE Variations in Modern Analog Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1268-1279 (2023) - [c107]Yeu-Haw Yeh, Simon Yi-Hung Chen, Hung-Ming Chen, Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, Po-Yang Chen:
DPRoute: Deep Learning Framework for Package Routing. ASP-DAC 2023: 277-282 - [c106]Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen:
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC. ASP-DAC 2023: 352-357 - [c105]Hung-Ming Chen, Chu-Wen Ho, Shih-Hsien Wu, Wei Lu, Po-Tsang Huang, Hao-Ju Chang, Chien-Nan Jimmy Liu:
Reshaping System Design in 3D Integration: Perspectives and Challenges. ISPD 2023: 71-77 - [c104]Po-Yang Chen, Chang-Yun Liu, Hung-Ming Chen, Po-Tsang Huang:
On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC. ISQED 2023: 1-6 - [c103]Po-Chun Wang, Mark Po-Hung Lin, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Layout Synthesis of Analog Primitive Cells with Variational Autoencoder. SMACD 2023: 1-4 - 2022
- [j53]Hung-Ming Chen, Hung-Yi Wu, Pih-Shuw Chen:
Innovative service model of information services based on the sustainability balanced scorecard: Applied integration of the fuzzy Delphi method, Kano model, and TRIZ. Expert Syst. Appl. 205: 117601 (2022) - [j52]Tsui-Ping Chang, Hung-Ming Chen, Shih-Ying Chen, Wei-Cheng Lin:
Deep Learning Model for Dynamic Hand Gesture Recognition for Natural Human-Machine Interface on End Devices. Int. J. Inf. Syst. Model. Des. 13(10): 1-23 (2022) - [c102]Bo-Cheng Lai, Tzu-Chieh Chiang, Po-Shen Kuo, Wan-Ching Wang, Yan-Lin Hung, Hung-Ming Chen, Chien-Nan Liu, Shyh-Jye Jou:
DASC: A DRAM Data Mapping Methodology for Sparse Convolutional Neural Networks. DATE 2022: 208-213 - [c101]Hao-Yu Chi, Simon Yi-Hung Chen, Hung-Ming Chen, Chien-Nan Liu, Yun-Chih Kuo, Ya-Hsin Chang, Kuan-Hsien Ho:
Practical Substrate Design Considering Symmetrical and Shielding Routes. DATE 2022: 951-956 - [c100]Wei Lu, Pei-Yu Ge, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang:
Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM. ISOCC 2022: 169-170 - [c99]Jui-I Kao, Wei Lu, Po-Tsang Huang, Hung-Ming Chen:
Precision-Aware Workload Distribution and Dataflow for a Hybrid Digital-CIM Deep CNN Accelerator. ISOCC 2022: 171-172 - [c98]Yun-Ru Yang, Wei Lu, Po-Tsang Huang, Hung-Ming Chen:
Digital Computation-in-Memory Design with Adaptive Floating Point for Deep Neural Networks. MCSoC 2022: 216-223 - [c97]Hung-Ming Chen, Yung-Feng Lu, Jia-Hong Jhang, Hong-Sheng Sun:
An OpenDDS cross-platform data exchange module for cloud-edge-based industrial internet of things. RACS 2022: 153-158 - [c96]Yung-Feng Lu, Hung-Ming Chen, Chang-Wei Chen, Hsueh-Wen Tseng, Chin-Fu Kuo:
Red-black tree I/O management of solid state disk with elastic striping design. RACS 2022: 159-164 - [c95]Cheng-Yu Chiang, Chia-Lin Hu, Kang-Yu Chang, Mark Po-Hung Lin, Shyh-Jye Jou, Hung-Yu Chen, Chien-Nan Jimmy Liu, Hung-Ming Chen:
On Optimizing Capacitor Array Design for Advanced Node SAR ADC. SMACD 2022: 1-4 - [c94]Yeu-Haw Yeh, Simon Yi-Hung Chen, Hung-Ming Chen, Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, Po-Yang Chen:
Substrate Signal Routing Solution Exploration for High-Density Packages with Machine Learning. VLSI-DAT 2022: 1-4 - [c93]Jie Zhang, Wei Lu, Po-Tsang Huang, Sih-Han Li, Tsung-Yi Hung, Shih-Hsien Wu, Ming-Ji Dai, I-Shan Chung, Wen-Chao Chen, Chin-Hung Wang, Shyh-Shyuan Sheu, Hung-Ming Chen, Kuan-Neng Chen, Wei-Chung Lo, Chih-I Wu:
An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology. VLSI Technology and Circuits 2022: 262-263 - 2021
- [j51]Wei Lu, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang:
An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(4): 776-788 (2021) - [j50]K. A. Asha, Li En Hsu, Abhishek Patyal, Hung-Ming Chen:
Improving the Quality of FPGA RO-PUF by Principal Component Analysis (PCA). ACM J. Emerg. Technol. Comput. Syst. 17(3): 34:1-34:25 (2021) - [j49]Hao-Yu Chi, Zi-Jun Lin, Chia-Hao Hung, Chien-Nan Jimmy Liu, Hung-Ming Chen:
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(12): 2556-2567 (2021) - [c92]Hung-Ming Chen, Cheng-En Ni, Kang-Yu Chang, Tzu-Chieh Chiang, Shih-Han Chang, Cheng-Yu Chiang, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou:
On Reconfiguring Memory-Centric AI Edge Devices for CIM. ISOCC 2021: 262-263 - [c91]Ying-Yao Huang, Chang-Tzu Lin, Wei-Lun Liang, Hung-Ming Chen:
Learning Based Placement Refinement to Reduce DRC Short Violations. VLSI-DAT 2021: 1-4 - 2020
- [j48]Jiunn-Woei Lian, Chih-Teng Chen, Li-Fang Shen, Hung-Ming Chen:
Understanding user acceptance of blockchain-based smart locker. Electron. Libr. 38(2): 353-366 (2020) - [j47]Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Wei-Zen Chen:
Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5056-5068 (2020) - [j46]Hao-Yu Chi, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Wire Load Oriented Analog Routing with Matching Constraints. ACM Trans. Design Autom. Electr. Syst. 25(6): 55:1-55:26 (2020) - [c90]Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin:
Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization. DAC 2020: 1-2 - [c89]Jyun-Ru Jiang, Yun-Chih Kuo, Simon Yi-Hung Chen, Hung-Ming Chen:
On Pre-Assignment Route Prototyping for Irregular Bumps on BGA Packages. DATE 2020: 1311-1314 - [c88]Mark Po-Hung Lin, Hao-Yu Chi, Abhishek Patyal, Zheng-Yao Liu, Jun-Jie Zhao, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Achieving Analog Layout Integrity through Learning and Migration Invited Talk. ICCAD 2020: 55:1-55:8 - [c87]Hung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Küster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou:
On EDA Solutions for Reconfigurable Memory-Centric AI Edge Applications. ICCAD 2020: 127:1-127:8 - [c86]Sin-Hong Liou, Sean S.-Y. Liu, Richard Sun, Hung-Ming Chen:
Timing Driven Partition for Multi-FPGA Systems with TDM Awareness. ISPD 2020: 111-118 - [c85]Yung-Feng Lu, Chin-Fu Kuo, Hung-Ming Chen, Hsueh-Wen Tseng, Shih-Chun Chou, Yu-Ming Liao:
A Three-Factor Mutual Authentication Scheme for Cyber-Physical Systems. RACS 2020: 113-118 - [c84]Yung-Feng Lu, Hung-Ming Chen, Chin-Fu Kuo, Bo-Ting Chen, Zong-Yan Dai:
Enhanced Privacy with Blockchain-based Storage for Data Sharing. RACS 2020: 124-129 - [c83]Po-Tsang Huang, Tzung-Han Tsai, Po-Jen Yang, Wei Hwang, Hung-Ming Chen:
Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs. SoCC 2020: 242-247
2010 – 2019
- 2019
- [j45]Jian-De Li, Chun-Hao Kuo, Guan-Ruei Lu, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho, Hung-Ming Chen, Shiyan Hu:
Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips. Microelectron. J. 83: 185-196 (2019) - [c82]Po-Cheng Pan, Chien-Chia Huang, Hung-Ming Chen:
An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis. DAC 2019: 232 - [c81]Hao-Yu Chi, Zi-Jun Lin, Chia-Hao Hung, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines. ICCAD 2019: 1-6 - [c80]Yu-Hsiang Chuang, Chang-Tzu Lin, Hung-Ming Chen, Chi-Han Lee, Ting-Sheng Chen:
More Effective Power Network Prototyping by Analytical and Centroid Learning. ISCAS 2019: 1-5 - [c79]Yung-Feng Lu, Hung-Ming Chen, Chin-Fu Kuo, Bo-Kai Tseng, Shih-Chun Chou:
Container-based load balancing for WebRTC applications. RACS 2019: 20-26 - [c78]Yu-Hsien Chen, Hao-Yu Chi, Ling-Yen Song, Chien-Nan Jimmy Liu, Hung-Ming Chen:
A Structure-Based Methodology for Analog Layout Generation. SMACD 2019: 33-36 - 2018
- [j44]James T. Lin, Chun-Chih Chiu, Edward Huang, Hung-Ming Chen:
A Multi-Fidelity Model Approach for Simultaneous Scheduling of Machines and Vehicles in Flexible Manufacturing Systems. Asia Pac. J. Oper. Res. 35(1): 1850005:1-1850005:20 (2018) - [j43]Guan-Ruei Lu, Ansuman Banerjee, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen:
Reliability Hardening Mechanisms in Cyber-Physical Digital-Microfluidic Biochips. ACM J. Emerg. Technol. Comput. Syst. 14(3): 34:1-34:22 (2018) - [j42]Guan-Ruei Lu, Chun-Hao Kuo, Kuen-Cheng Chiang, Ansuman Banerjee, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen:
Flexible Droplet Routing in Active Matrix-Based Digital Microfluidic Biochips. ACM Trans. Design Autom. Electr. Syst. 23(3): 37:1-37:25 (2018) - [c77]K. A. Asha, Abhishek Patyal, Hung-Ming Chen:
Generation of PUF-Keys on FPGAs by K-means Frequency Clustering. AsianHOST 2018: 44-49 - [c76]Guan-Ruei Lu, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen:
Multi-level droplet routing in active-matrix based digital-microfluidic biochips. ASP-DAC 2018: 46-51 - [c75]Hao-Yu Chi, Hwa-Yi Tseng, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Performance-preserved analog routing methodology via wire load reduction. ASP-DAC 2018: 482-487 - [c74]Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu:
Analog placement with current flow and symmetry constraints using PCP-SP. DAC 2018: 10:1-10:6 - [c73]Bing-Hui Jiang, Hung-Ming Chen:
Extending ML-OARSMT to net open locator with efficient and effective boolean operations. ICCAD 2018: 83 - [c72]Yung-Feng Lu, Chin-Fu Kuo, Hung-Ming Chen, Guan-Bo Wang, Shih-Chun Chou:
A mutual authentication scheme with user anonymity for cyber-physical and internet of things. RACS 2018: 88-93 - [c71]Po-Cheng Pan, Hung-Wen Huang, Chien-Chia Huang, Abhishek Patyal, Hung-Ming Chen, Tsun-Yu Yang:
On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts. SMACD 2018: 181-184 - [c70]Li-Chin Chen, Chien-Chia Huang, Yao-Lin Chang, Hung-Ming Chen:
A learning-based methodology for routability prediction in placement. VLSI-DAT 2018: 1-4 - 2017
- [j41]Hua-Chiang Wen, Wu-Ching Chou, Po-Chen Lin, Yeau-Ren Jeng, Chien-Chang Chen, Hung-Ming Chen, Don Son Jiang, Chun-Hu Cheng:
Using nanoindentation to investigate the temperature cycling of Sn-37Pb solders. Microelectron. Reliab. 78: 111-117 (2017) - [c69]Guan-Ruei Lu, Guan-Ming Huang, Ansuman Banerjee, Bhargab B. Bhattacharya, Tsung-Yi Ho, Hung-Ming Chen:
On reliability hardening in cyber-physical digital-microfluidic biochips. ASP-DAC 2017: 518-523 - [c68]Wei-Hsun Liao, Chang-Tzu Lin, Sheng-Hsin Fang, Chien-Chia Huang, Hung-Ming Chen, Ding-Ming Kwai, Yung-Fa Chou:
Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization. ASP-DAC 2017: 549-553 - [c67]Hung-Ming Chen, Ci-Jie Li, Bi-Shun Ke:
Designing A Simple Storage Services (S3) Compatible System Based on Ceph Software-Defined Storage System. ICMSSP 2017: 6-10 - [c66]Sheng-Hsin Fang, Chang-Tzu Lin, Wei-Hsun Liao, Chien-Chia Huang, Li-Chin Chen, Hung-Ming Chen, I-Hsuan Lee, Ding-Ming Kwai, Yung-Fa Chou:
On Tolerating Faults of TSV/Microbumps for Power Delivery Networks in 3D IC. ISVLSI 2017: 459-464 - [c65]Wan-Ning Wu, Chen Chen, Ching-Yu Chin, Chun-Kai Wang, Hung-Ming Chen:
An analytical placer for heterogeneous FPGAs via rough-placed packing. VLSI-DAT 2017: 1-4 - 2016
- [j40]Shu-Lin Wang, Young-Long Chen, Alex Mu-Hsing Kuo, Hung-Ming Chen, Yi-Shiang Shiu:
Design and evaluation of a cloud-based Mobile Health Information Recommendation system on wireless sensor networks. Comput. Electr. Eng. 49: 221-235 (2016) - [j39]Chin-Chia Wu, Yunqiang Yin, Wen-Hsiang Wu, Hung-Ming Chen, Shuenn-Ren Cheng:
Using a branch-and-bound and a genetic algorithm for a single-machine total late work scheduling problem. Soft Comput. 20(4): 1329-1339 (2016) - [c64]Chun-Hao Kuo, Guan-Ruei Lu, Tsung-Yi Ho, Hung-Ming Chen, Shiyan Hu:
Placement optimization of cyber-physical digital microfluidic biochips. BioCAS 2016: 448-451 - [c63]Yu-Hsiang Hung, Sheng-Hsin Fang, Hung-Ming Chen, Shen-Min Chen, Chang-Tzu Lin, Chia-Hsin Lee:
A New Methodology for Noise Sensor Placement Based on Association Rule Mining. ACM Great Lakes Symposium on VLSI 2016: 81-86 - 2015
- [j38]Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen, Tung-Chieh Chen, Chin-Chieh Lee, Jou-Chun Lin:
A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(9): 1373-1386 (2015) - [c62]Shih-Ying Liu, Tung-Chieh Chen, Hung-Ming Chen:
An approach to anchoring and placing high performance custom digital designs. ASP-DAC 2015: 384-389 - [c61]Chun-Kai Wang, Chuan-Chia Huang, Shih-Ying Sean Liu, Ching-Yu Chin, Sheng-Te Hu, Wei-Chen Wu, Hung-Ming Chen:
Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability. ISPD 2015: 149-156 - 2014
- [j37]Hung-Ming Chen, Yong-Zan Liou:
Performance Evaluation of Continuity of Care Records (CCRs): Parsing Models in a Mobile Health Management System. J. Medical Syst. 38(10): 117 (2014) - [j36]Hung-Ming Chen, Ya-Ting Tsao, Shin-Ni Tsai:
Automatic image segmentation and classification based on direction texton technique for hemolytic anemia in thin blood smears. Mach. Vis. Appl. 25(2): 501-510 (2014) - [j35]Shih-Ying Sean Liu, Chung-Hung Chang, Hung-Ming Chen, Tsung-Yi Ho:
ACER: An Agglomerative Clustering Based Electrode Addressing and Routing Algorithm for Pin-Constrained EWOD Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(9): 1316-1327 (2014) - [j34]Chun-Kai Wang, Yeh-Chi Chang, Hung-Ming Chen, Ching-Yu Chin:
Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation. ACM Trans. Design Autom. Electr. Syst. 20(1): 3:1-3:23 (2014) - [j33]Shih-Ying Sean Liu, Ren-Guo Luo, Suradeth Aroonsantidecha, Ching-Yu Chin, Hung-Ming Chen:
Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1404-1415 (2014) - [c60]Meng-Ling Chen, Tu-Hsiung Tsai, Hung-Ming Chen, Shi-Hao Chen:
Routability-driven bump assignment for chip-package co-design. ASP-DAC 2014: 519-524 - [c59]Yi-En Chen, Tu-Hsiung Tsai, Shi-Hao Chen, Hung-Ming Chen:
Cost-effective decap selection for beyond die power integrity. DATE 2014: 1-4 - [c58]Yiyu Shi, Hung-Ming Chen:
Memcomputing: The cape of good hope: [Extended special session description]. DATE 2014: 1-3 - [c57]Hsin-Chun Lin, Shih-Ying Sean Liu, Hung-Ming Chen:
Planning and placing power clamps for effective CDM protection. ICCAD 2014: 663-669 - [c56]Chia-Chi Huang, Chang-Tzu Lin, Wei-Syun Liao, Chieh-Jui Lee, Hung-Ming Chen, Chia-Hsin Lee, Ding-Ming Kwai:
Improving power delivery network design by practical methodologies. ICCD 2014: 237-242 - [c55]Shu-Lin Wang, Mu-Hsing Kuo, Hung-Ming Chen, André Kushniruk, Elizabeth M. Borycki, Yi-Hsiang Hsu:
Usability Evaluation of a Cloud Computing Based Context-aware Healthcare System. MIE 2014: 1194 - [c54]Shih-Hsin Hsu, Wei-Zen Chen, Jui-Pin Zheng, Sean S.-Y. Liu, Po-Cheng Pan, Hung-Ming Chen:
An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming. VLSI-DAT 2014: 1-4 - 2013
- [j32]Hung-Ming Chen, Po-Hung Chen, Cheng-Tso Lin, Jian-Hong Ciou:
An adaptive macroblock-mean difference based sorting scheme for fast normalized partial distortion search motion estimation. Comput. Electr. Eng. 39(5): 1409-1421 (2013) - [j31]Hung-Ming Chen, Chuan-Chien Hou, Yu-Hsiang Wang:
A 3D visualized expert system for maintenance and management of existing building facilities using reliability-based method. Expert Syst. Appl. 40(1): 287-299 (2013) - [j30]Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih:
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs. Integr. 46(3): 280-289 (2013) - [j29]Ching-Yu Chin, Chung-Yi Kuan, Tsung-Ying Tsai, Hung-Ming Chen, Yoji Kajitani:
Escaped Boundary Pins Routing for High-Speed Boards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 381-391 (2013) - [j28]Ren-Jie Lee, Hung-Ming Chen:
A study of row-based area-array I/O design planning in concurrent chip-package design flow. ACM Trans. Design Autom. Electr. Syst. 18(2): 30:1-30:19 (2013) - [j27]Shih-Ying Sean Liu, Wan-Ting Lo, Chieh-Jui Lee, Hung-Ming Chen:
Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization. ACM Trans. Design Autom. Electr. Syst. 18(3): 40:1-40:20 (2013) - [j26]Ren-Jie Lee, Hsin-Wu Hsu, Hung-Ming Chen:
Board- and Chip-Aware Package Wire Planning. IEEE Trans. Very Large Scale Integr. Syst. 21(8): 1377-1387 (2013) - [c53]Shih-Ying Sean Liu, Chieh-Jui Lee, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee:
Effective power network prototyping via statistical-based clustering and sequential linear programming. DATE 2013: 1701-1706 - [c52]Shih-Ying Sean Liu, Ren-Guo Luo, Hung-Ming Chen:
A network-flow based algorithm for power density mitigation at post-placement stage. DATE 2013: 1707-1710 - [c51]Po-Cheng Pan, Hung-Ming Chen, Chien-Chih Lin:
PAGE: parallel agile genetic exploration towards utmost performance for analog circuit design. DATE 2013: 1849-1854 - [c50]Ching-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin:
Efficient analog layout prototyping by layout reuse with routing preservation. ICCAD 2013: 40-47 - [c49]Hung-Ming Chen, Jhong-Kai Lin, Po-Hung Chen, Ting-Jhao Jheng:
A fuzzy thresholding early termination scheme of fast motion estimation for video coding. ISCE 2013: 243-244 - [c48]Hung-Ming Chen, Yong-Zan Liou, Shih-Ying Chen, Jhuo-Syun Li:
Design of mobile healthcare service with health records format evaluation. ISCE 2013: 257-258 - [c47]Hung-Ming Chen:
On the way to practical tools for beyond die codesign and integration. ISPD 2013: 61 - [c46]Shih-Ying Chen, Jia-Hong Li, Ke-Chung Lin, Hung-Ming Chen, Tung-Shou Chen:
Using MapReduce Framework for Mining Association Rules. ITCS 2013: 723-731 - 2012
- [j25]Min-Yuan Cheng, Kuo-Yu Huang, Hung-Ming Chen:
K-means particle swarm optimization with embedded chaotic search for solving multidimensional problems. Appl. Math. Comput. 219(6): 3091-3099 (2012) - [j24]Hung-Ming Chen, Wei-Ko Kao, Hsing-Chih Tsai:
Genetic programming for predicting aseismic abilities of school buildings. Eng. Appl. Artif. Intell. 25(6): 1103-1113 (2012) - [j23]Hung-Ming Chen, Jung-Wen Lo, Chang-Kuo Yeh:
An Efficient and Secure Dynamic ID-based Authentication Scheme for Telecare Medical Information Systems. J. Medical Syst. 36(6): 3907-3915 (2012) - [j22]Min-Yuan Cheng, Kuo-Yu Huang, Hung-Ming Chen:
Dynamic guiding particle swarm optimization with embedded chaotic search for solving multidimensional problems. Optim. Lett. 6(4): 719-729 (2012) - [c45]Suradeth Aroonsantidecha, Shih-Ying Liu, Ching-Yu Chin, Hung-Ming Chen:
A fast thermal aware placement with accurate thermal analysis based on Green function. ASP-DAC 2012: 425-430 - [c44]Shih-Ying Liu, Chieh-Jui Lee, Hung-Ming Chen:
Agglomerative-based flip-flop merging with signal wirelength optimization. DATE 2012: 1391-1396 - [c43]Hsin-Wu Hsu, Meng-Ling Chen, Hung-Ming Chen, Hung-Chun Li, Shi-Hao Chen:
On effective flip-chip routing via pseudo single redistribution layer. DATE 2012: 1597-1602 - [c42]Po-Cheng Pan, Hung-Ming Chen, Yi-Kan Cheng, Jill Liu, Wei-Yi Hu:
Configurable analog routing methodology via technology and design constraint unification. ICCAD 2012: 620-626 - [c41]Yeh-Chi Chang, Chun-Kai Wang, Hung-Ming Chen:
On construction low power and robust clock tree via slew budgeting. ISPD 2012: 129-136 - [c40]Chieh-Jui Lee, Shih-Ying Liu, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee:
Hierarchical power network synthesis for multiple power domain designs. ISQED 2012: 477-482 - 2011
- [j21]Wei-Ko Kao, Hung-Ming Chen, Jui-Sheng Chou:
Aseismic ability estimation of school building using predictive data mining models. Expert Syst. Appl. 38(8): 10252-10263 (2011) - [j20]Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu:
Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits. J. Inf. Sci. Eng. 27(1): 287-302 (2011) - [j19]Chia-Yi Lin, Hung-Ming Chen:
A Generic Multi-Dimensional Scan-Control Scheme for Test-Cost Reduction. J. Inf. Sci. Eng. 27(6): 1943-1957 (2011) - [j18]Ren-Jie Lee, Hung-Ming Chen:
Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign. IEEE Trans. Very Large Scale Integr. Syst. 19(5): 904-909 (2011) - [c39]Ren-Jie Lee, Hung-Ming Chen:
Row-based area-array I/O design planning in concurrent chip-package design flow. ASP-DAC 2011: 837-842 - [c38]Tsung-Ying Tsai, Ren-Jie Lee, Ching-Yu Chin, Chung-Yi Kuan, Hung-Ming Chen, Yoji Kajitani:
On routing fixed escaped boundary pins for high speed boards. DATE 2011: 461-466 - [c37]Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, Wei-Zen Chen:
Fast analog layout prototyping for nanometer design migration. ICCAD 2011: 517-522 - [c36]Chuan-Pin Lu, Jui-Pin Li, Wei-Yi Liou, Hung-Ming Chen:
The Development of Smart Assistive Technology Devices for Urinary Catheterization Monitoring. ICGEC 2011: 41-44 - [c35]Meng-Chen Wu, Hung-Ming Chen, Jing-Yang Jou:
Mixed non-rectangular block packing for non-Manhattan layout architectures. ISQED 2011: 257-262 - [c34]Chang-Cheng Tsai, Tzu-Hen Lin, Shin-Han Tsai, Hung-Ming Chen:
Clock planning for multi-voltage and multi-mode designs. ISQED 2011: 654-658 - [c33]Kuo-Hsuan Meng, Po-Cheng Pan, Hung-Ming Chen:
Integrated hierarchical synthesis of analog/RF circuits with accurate performance mapping. ISQED 2011: 777-784 - [c32]Hung-Ming Chen, Po-Hung Chen, Jian-Hong Ciou:
New Sorting Technique on Partial Distortion Search Using Two Bit-Transform for Fast Optimal Motion Estimation. RVSP 2011: 276-279 - [c31]Yi-Rong Chen, Hung-Ming Chen, Shih-Ying Liu:
TSV-based 3D-IC placement for timing optimization. SoCC 2011: 290-295 - 2010
- [j17]Sheng-Fu Liang, Hung-Ming Chen, Yi-Che Liu:
Image Enlargement by Applying Coordinate Rotation and Kernel Stretching to Interpolation Kernels. EURASIP J. Adv. Signal Process. 2010 (2010) - [j16]Chia-Yi Lin, Li-Chung Hsu, Hung-Ming Chen:
On Reducing Test Power, Volume and Routing Cost by Chain Reordering and Test Compression Techniques. IEICE Trans. Electron. 93-C(3): 369-378 (2010) - [j15]Chia-Yi Lin, Hsiu-Chuan Lin, Hung-Ming Chen:
On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1220-1224 (2010) - [c30]Fang-Yu Fan, Hung-Ming Chen, I-Min Liu:
Technology mapping with crosstalk noise avoidance. ASP-DAC 2010: 319-324 - [c29]Chia-Yi Lin, Hung-Ming Chen:
A novel two-dimensional scan-control scheme for test-cost reduction. ISQED 2010: 237-243 - [c28]Houng-Yi Li, Iris Hui-Ru Jiang, Hung-Ming Chen:
Simultaneous voltage island generation and floorplanning. SoCC 2010: 219-223
2000 – 2009
- 2009
- [j14]Meng-Chen Wu, Ming-Ching Lu, Hung-Ming Chen, Jing-Yang Jou:
Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning. ACM Trans. Design Autom. Electr. Syst. 15(1): 3:1-3:17 (2009) - [j13]Ren-Jie Lee, Hung-Ming Chen:
Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1087-1098 (2009) - [c27]Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih:
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design. DATE 2009: 845-850 - [c26]Bo-Zhou Chen, Hung-Ming Chen, Li-Da Huang, Po-Cheng Pan:
A stochastic-based efficient critical area extractor on OpenAccess platform. ACM Great Lakes Symposium on VLSI 2009: 197-202 - [c25]Hsin-Hua Pan, Hung-Ming Chen, Chia-Yi Chang:
Buffer/flip-flop block planning for power-integrity-driven floorplanning. ISQED 2009: 488-493 - 2008
- [j12]Hung-Ming Chen, Yu-Chin Lin:
Web-FEM: An internet-based finite-element analysis framework with 3D graphics and parallel computing environment. Adv. Eng. Softw. 39(1): 55-68 (2008) - [j11]Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu:
An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning. J. Inf. Sci. Eng. 24(1): 115-127 (2008) - [j10]Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu:
Effective decap insertion in area-array SoC floorplan design. ACM Trans. Design Autom. Electr. Syst. 13(4): 66:1-66:20 (2008) - [j9]Chia-Yi Chang, Hung-Ming Chen:
Design Migration From Peripheral ASIC Design to Area-I/O Flip-Chip Design by Chip I/O Planning and Legalization. IEEE Trans. Very Large Scale Integr. Syst. 16(1): 108-112 (2008) - [c24]Lun-Chun Wei, Hung-Ming Chen, Li-Da Huang, Sarah Songjie Xu:
Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow. ACM Great Lakes Symposium on VLSI 2008: 359-362 - [c23]Bruce Tseng, Hung-Ming Chen:
Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations. ISPD 2008: 23-30 - [c22]Ming-Fang Lai, Hung-Ming Chen:
An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign. ISQED 2008: 604-607 - 2007
- [j8]Wen-Lin Huang, Hung-Ming Chen, Shiow-Fen Hwang, Shinn-Ying Ho:
Accurate prediction of enzyme subfamily class using an adaptive fuzzy k-nearest neighbor method. Biosyst. 90(2): 405-413 (2007) - [j7]Hung-Ming Chen, Po-Hung Chen, Kuo-Liang Yeh, Wen-Hsien Fang, Mon-Chau Shie, Feipei Lai:
Center of Mass-Based Adaptive Fast Block Motion Estimation. EURASIP J. Image Video Process. 2007 (2007) - [j6]Hung-Ming Chen, Bo-Fu Liu, Hui-Ling Huang, Shiow-Fen Hwang, Shinn-Ying Ho:
SODOCK: Swarm optimization for highly flexible protein-ligand docking. J. Comput. Chem. 28(2): 612-623 (2007) - [c21]Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu:
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design. ASP-DAC 2007: 792-797 - [c20]Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen:
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign. ASP-DAC 2007: 804-809 - [c19]Chia-Yi Lin, Hung-Ming Chen:
A selective pattern-compression scheme for power and test-data reduction. ICCAD 2007: 520-525 - [c18]Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu:
Using power gating techniques in area-array SoC floorplan design. SoCC 2007: 233-236 - 2006
- [j5]Po-Hung Chen, Hung-Ming Chen, Kuo-Jui Hung, Wen-Hsien Fang, Mon-Chau Shie, Feipei Lai:
Markov model fuzzy-reasoning based algorithm for fast block motion estimation. J. Vis. Commun. Image Represent. 17(1): 131-142 (2006) - [j4]Hung-Ming Chen, I-Min Liu, Martin D. F. Wong:
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2552-2556 (2006) - [c17]Li-Chung Hsu, Hung-Ming Chen:
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design. ISQED 2006: 451-456 - [c16]Shinn-Ying Ho, Chih-Hung Hsieh, Kuan-Wei Chen, Hui-Ling Huang, Hung-Ming Chen, Shinn-Jang Ho:
Scoring Method for Tumor Prediction from Microarray Data Using an Evolutionary Fuzzy Classifier. PAKDD 2006: 520-529 - [c15]Huang-Liang Chen, Hung-Ming Chen:
On Achieving Low-Power SoC Clock Tree Synthesis by Transition Time Planning via Buffer Library Study. SoCC 2006: 203-206 - [c14]Ming-Ching Lu, Meng-Chen Wu, Hung-Ming Chen, Iris Hui-Ru Jiang:
Performance Constraints Aware Voltage Islands Generation in SoC Floorplan Design. SoCC 2006: 211-214 - 2005
- [j3]Jian-Hung Chen, Hung-Ming Chen, Shinn-Ying Ho:
Design of nearest neighbor classifiers: multi-objective approach. Int. J. Approx. Reason. 40(1-2): 3-22 (2005) - [j2]Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong:
Simultaneous power supply planning and noise avoidance in floorplan design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 578-587 (2005) - [c13]Bo-Fu Liu, Hung-Ming Chen, Hui-Ling Huang, Shiow-Fen Hwang, Shinn-Ying Ho:
Flexible protein-ligand docking using particle swarm optimization. Congress on Evolutionary Computation 2005: 251-258 - [c12]Shinn-Ying Ho, Chong-Cheng Lee, Hung-Ming Chen, Hui-Ling Huang:
Efficient gene selection for classification of microarray data. Congress on Evolutionary Computation 2005: 1753-1760 - [c11]Bo-Fu Liu, Hung-Ming Chen, Jian-Hung Chen, Shiow-Fen Hwang, Shinn-Ying Ho:
MeSwarm: memetic particle swarm optimization. GECCO 2005: 267-268 - [c10]Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong:
Current Calculation on VLSI Signal Interconnects. ISQED 2005: 580-585 - 2004
- [j1]Shinn-Ying Ho, Hung-Ming Chen, Shinn-Jang Ho, Tai-Kang Chen:
Design of accurate classifiers with a compact fuzzy-rule base using an evolutionary scatter partition of feature space. IEEE Trans. Syst. Man Cybern. Part B 34(2): 1031-1044 (2004) - [c9]Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang:
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. ICCD 2004: 562-567 - [c8]Jian-Hung Chen, Hung-Ming Chen, Shinn-Ying Ho:
Design of Nearest Neighbor Classifiers Using an Intelligent Multi-objective Evolutionary Algorithm. PRICAI 2004: 262-271 - 2003
- [c7]Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong:
Floorplanning with power supply noise avoidance. ASP-DAC 2003: 427-430 - [c6]Li-Da Huang, Hung-Ming Chen, D. F. Wong:
Global Wire Bus Configuration with Minimum Delay Uncertainty. DATE 2003: 10050-10055 - [c5]Hung-Ming Chen, Po-Hung Chen, Tai-Jee Pan, Feipei Lai:
Designing platform-based system power management on a smart tablet appliance. ICECS 2003: 316-319 - 2001
- [c4]I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong:
Integrated power supply planning and floorplanning. ASP-DAC 2001: 589-594 - [c3]Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang:
Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI 2001: 62-67
1990 – 1999
- 1999
- [c2]Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani:
Integrated floorplanning and interconnect planning. ICCAD 1999: 354-357 - 1996
- [c1]Lee-Feng Chien, Ming-Jer Lee, Ming-Chuan Chen, Hung-Ming Chen, Ting-Chi Chen, Wei-Feng Tung, Hung-Chung Lee, Duen-Yi Huang, Yuan-Cheng Chang:
尋易（Csmart-Ⅱ）：智慧型網路中文資訊檢索系統 (An Intelligent Chinese Information Retrieval System for the Internet) [In Chinese]. ROCLING 1996: 121-136
Coauthor Index
Chien-Nan Jimmy Liu
aka: Chien-Nan Liu
aka: Chien-Nan Liu
Shih-Ying Liu
aka: Shih-Ying Sean Liu
aka: Shih-Ying Sean Liu
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