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2020 – today
- 2024
[j5]Shih-Nung Chen
, Shi-Hao Chen:
Application of Generative Adversarial Networks for Virtual Silicon Data Generation and Design-Technology Co-Optimization: A Study on WAT and CP. IEEE Access 12: 6532-6545 (2024)- [j4]Yu-Hsuan Tsai, Yi-Cheng Lin, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Shi-Hao Chen, Chi-Shi Chen, Chia-Hsiang Yang:
A 28-nm 1.3-mW Speech-to-Text Accelerator for Edge AI Devices. IEEE J. Solid State Circuits 59(11): 3816-3826 (2024)
2010 – 2019
- 2019
- [c12]Yu-Zhe Wang, Jingjie Wu, Shi-Hao Chen, Mango Chia-Tso Chao, Chia-Hsiang Yang:
Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs. VLSI-DAT 2019: 1-4 - 2018
- [c11]Jheng-Yi Chen, Ming-Yu Chang, Shi-Hao Chen, Jia-Wei Lee, Meng-Hsueh Chiang:
Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM. ISQED 2018: 151-155 - [c10]Keng-Wei Chang, Chun-Yang Huang, Szu-Pang Mu, Jian-Min Huang, Shi-Hao Chen, Mango C.-T. Chao:
DVFS Binning Using Machine-Learning Techniques. ITC-Asia 2018: 31-36 - 2016
- [j3]Szu-Pang Mu, Mango C.-T. Chao, Shi-Hao Chen, Yi-Ming Wang:
Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1675-1687 (2016) - 2014
- [j2]Wen-Hsiang Chang, Mango Chia-Tso Chao, Shi-Hao Chen:
Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1069-1081 (2014) - [c9]Meng-Ling Chen, Tu-Hsiung Tsai, Hung-Ming Chen, Shi-Hao Chen:
Routability-driven bump assignment for chip-package co-design. ASP-DAC 2014: 519-524 - [c8]Yi-En Chen, Tu-Hsiung Tsai, Shi-Hao Chen, Hung-Ming Chen:
Cost-effective decap selection for beyond die power integrity. DATE 2014: 1-4 - [c7]Yi-Ming Wang, Mango Chia-Tso Chao, Shi-Hao Chen, Hung-Chun Li:
Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designs. VLSI-DAT 2014: 1-4 - 2013
- [j1]Shi-Hao Chen, Youn-Long Lin, Mango Chia-Tso Chao:
Power-Up Sequence Control for MTCMOS Designs. IEEE Trans. Very Large Scale Integr. Syst. 21(3): 413-423 (2013) - [c6]Hao-Wen Hsu, Shih-Hua Kuo, Wen-Hsiang Chang, Shi-Hao Chen, Ming-Tung Chang, Mango Chia-Tso Chao:
Testing retention flip-flops in power-gated designs. VTS 2013: 1-6 - 2012
- [c5]Yi-Ming Wang, Shi-Hao Chen, Mango Chia-Tso Chao:
An Efficient Hamiltonian-cycle power-switch routing for MTCMOS designs. ASP-DAC 2012: 59-65 - [c4]Hsin-Wu Hsu, Meng-Ling Chen, Hung-Ming Chen, Hung-Chun Li, Shi-Hao Chen:
On effective flip-chip routing via pseudo single redistribution layer. DATE 2012: 1597-1602 - 2010
- [c3]Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia-Tso Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai:
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs. ICCAD 2010: 155-161
2000 – 2009
- 2008
- [c2]Shi-Hao Chen, Jiing-Yuan Lin:
Experiences of low power design implementation and verification. ASP-DAC 2008: 742-747 - 2007
- [c1]Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai:
DFM/DFY practices during physical designs for timing, signal integrity, and power. ASP-DAC 2007: 232-237
Coauthor Index
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