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Chih-Mou Tseng

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2010 – 2019

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2011
[c4]
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  - conf/itc/WenHTLLCTTL11
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  - https://dblp.org/rec/conf/itc/WenHTLLCTTL11
Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James Chien-Mo Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li:
Test clock domain optimization for peak power supply noise reduction during scan. ITC 2011: 1-8
2010
[c3]
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Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li:
TSV redundancy: Architecture and design issues in 3D IC. DATE 2010: 166-171
[c2]
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  - conf/iccad/MuWYCCTT10
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Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia-Tso Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai:
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs. ICCAD 2010: 155-161

2000 – 2009

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2009
[c1]
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Tzuo-Fan Chien, Wen-Chi Chao, James Chien-Mo Li, Yao-Wen Chang, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng:
BIST design optimization for large-scale embedded memory cores. ICCAD 2009: 197-200

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