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2000 – 2009
- 2005
[c12]Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong
:
Current Calculation on VLSI Signal Interconnects. ISQED 2005: 580-585- [c11]Muzhou Shao, Youxin Gao, Li-Pen Yuan, Martin D. F. Wong:
IR Drop and Ground Bounce Awareness Timing Model. ISVLSI 2005: 226-231 - 2003
- [j4]Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao:
Maze routing with buffer insertion under transition time constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 91-95 (2003) - [c10]Muzhou Shao, D. F. Wong, Youxin Gao, Huijing Cao, Li-Pen Yuan:
A fast and accurate method for interconnect current calculation. ASP-DAC 2003: 37-42 - [c9]Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee:
Explicit gate delay model for timing evaluation. ISPD 2003: 32-38 - 2002
- [c8]Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao:
Maze Routing with Buffer Insertion under Transition Time Constraints. DATE 2002: 702-707 - [c7]Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao:
Shaping interconnect for uniform current density. ICCAD 2002: 254-259 - 2001
- [c6]Youxin Gao, D. F. Wong:
A fast and accurate delay estimation method for buffered interconnects. ASP-DAC 2001: 533-538 - [c5]Youxin Gao, D. F. Wong:
A graph based algorithm for optimal buffer insertion under accurate delay models. DATE 2001: 535-539 - 2000
- [c4]Youxin Gao, D. F. Wong:
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. DATE 2000: 512-516
1990 – 1999
- 1999
- [j3]Youxin Gao, D. F. Wong:
Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance. Integr. 27(2): 165-178 (1999) - [j2]Youxin Gao, Martin D. F. Wong:
Optimal shape function for a bidirectional wire under Elmore delay model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7): 994-999 (1999) - [j1]Youxin Gao, Martin D. F. Wong:
Wire-sizing optimization with inductance consideration using transmission-line model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12): 1759-1767 (1999) - [c3]Youxin Gao, D. F. Wong:
Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. ASP-DAC 1999: 217-220 - 1998
- [c2]Youxin Gao, D. F. Wong:
Shaping a VLSI wire to minimize delay using transmission line model. ICCAD 1998: 611-616 - 1997
- [c1]Youxin Gao, D. F. Wong:
Optimal shape function for a bi-directional wire under Elmore delay model. ICCAD 1997: 622-627
Coauthor Index
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