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Tzu-Hen Lin
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2010 – 2019
- 2014
- [j1]Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Sheng Chou, Tzu-Hen Lin, Tung-Chieh Chen, Yao-Wen Chang:
NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1914-1927 (2014) - [c4]Meng-Kai Hsu, Nitesh Katta, Homer Yen-Hung Lin, Keny Tzu-Hen Lin, King Ho Tam, Ken Chung-Hsing Wang:
Design and manufacturing process co-optimization in nano-technology. ICCAD 2014: 574-581 - 2013
- [c3]Tzu-Hen Lin, Pritha Banerjee, Yao-Wen Chang:
An efficient and effective analytical placer for FPGAs. DAC 2013: 10:1-10:6 - 2011
- [c2]Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, Yao-Wen Chang:
Routability-driven analytical placement for mixed-size circuit designs. ICCAD 2011: 80-84 - [c1]Chang-Cheng Tsai, Tzu-Hen Lin, Shin-Han Tsai, Hung-Ming Chen:
Clock planning for multi-voltage and multi-mode designs. ISQED 2011: 654-658
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