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ORCID57th DAC 2020: San Francisco, CA, USA
- 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020. IEEE 2020, ISBN 978-1-7281-1085-1
- Antonino Tumeo, Marco Minutoli
, Vito Giovanni Castellana, Joseph B. Manzano, Vinay Amatya, David Brooks, Gu-Yeon Wei:
Invited: Software Defined Accelerators From Learning Tools Environment. 1-6 - Ghada Dessouky, Patrick Jauernig, Nele Mentens, Ahmad-Reza Sadeghi, Emmanuel Stapf:
INVITED: AI Utopia or Dystopia - On Securing AI Platforms. 1-6 - Shaza Zeitouni, Emmanuel Stapf, Hossein Fereidooni, Ahmad-Reza Sadeghi:
On the Security of Strong Memristor-based Physically Unclonable Functions. 1-6 - Anna Bernasconi, Stelvio Cimato, Valentina Ciriani, Maria Chiara Molteni:
Multiplicative Complexity of Autosymmetric Functions: Theory and Applications to Security. 1-6 - Behnam Khaleghi, Mohsen Imani, Tajana Rosing:
Prive-HD: Privacy-Preserved Hyperdimensional Computing. 1-6 - Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. 1-6 - Brett Shook, Prateek Bhansali, Chandramouli V. Kashyap, Chirayu Amin, Siddhartha Joshi:
MLParest: Machine Learning based Parasitic Estimation for Custom Circuit Design. 1-6 - Renzo Andri, Tomas Henriksson, Luca Benini:
Extending the RISC-V ISA for Efficient RNN-based 5G Radio Resource Management. 1-6 - Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski:
R2D3: A Reliability Engine for 3D Parallel Systems. 1-6 - Zhanhong Tan, Jiebo Song, Xiaolong Ma, Sia Huat Tan, Hongyang Chen, Yuanqing Miao, Yifu Wu, Shaokai Ye, Yanzhi Wang, Dehui Li, Kaisheng Ma:
PCNN: Pattern-based Fine-Grained Regular Pruning Towards Optimizing CNN Accelerators. 1-6 - Peiyan Dong, Siyue Wang, Wei Niu, Chengming Zhang, Sheng Lin, Zhengang Li, Yifan Gong, Bin Ren, Xue Lin, Dingwen Tao:
RTMobile: Beyond Real-Time Mobile Acceleration of RNNs for Speech Recognition. 1-6 - He-Teng Zhang, Jie-Hong R. Jiang:
SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies. 1-6 - Alexander Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Laura Hauenschild, Naveen Shankar Nagaraja, Christian Unger, Walter Stechele:
ALF: Autoencoder-based Low-rank Filter-sharing for Efficient Convolutional Neural Networks. 1-6 - Minah Lee, Burhan Ahmad Mudassar, Taesik Na, Saibal Mukhopadhyay:
WarningNet: A Deep Learning Platform for Early Warning of Task Failures under Input Perturbation for Reliable Autonomous Platforms. 1-6 - Minjin Tang, Mei Wen, Junzhong Shen, Xiaolei Zhao, Chunyuan Zhang:
Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA. 1-6 - Jianli Chen, Zhipeng Huang, Ye Huang, Wenxing Zhu, Jun Yu, Yao-Wen Chang:
An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells *. 1-6 - Kaushik Roy, Indranil Chakraborty, Mustafa Fayez Ali, Aayush Ankit, Amogh Agrawal:
In-Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview. 1-6 - Yung-Chih Chen, Hao-Ju Chang, Li-Cheng Zheng:
Don't-Care-Based Node Minimization for Threshold Logic Networks. 1-6 - Jaekang Shin, Seungkyu Choi, Yeongjae Choi, Lee-Sup Kim:
A Pragmatic Approach to On-device Incremental Learning System with Selective Weight Updates. 1-6 - Huili Chen, Rosario Cammarota, Felipe Valencia, Francesco Regazzoni, Farinaz Koushanfar:
AHEC: End-to-end Compiler Framework for Privacy-preserving Machine Learning Acceleration. 1-6 - Sundar Dev, David Lo, Liqun Cheng, Parthasarathy Ranganathan:
Autonomous Warehouse-Scale Computers. 1-6 - Pei-Wei Chen, Yu-Ching Huang, Cheng-Lin Lee, Jie-Hong Roland Jiang:
Circuit Learning for Logic Regression on High Dimensional Boolean Space. 1-6 - Dimitrios Serpanos, Shengqi Yang, Marilyn Wolf:
Neural Network-Based Side Channel Attacks and Countermeasures. 1-2 - Tao Lu, Lu Peng:
BPU: A Blockchain Processing Unit for Accelerated Smart Contract Execution. 1-6 - Jianli Chen, Ziran Zhu, Qinghai Liu, Yimin Zhang, Wenxing Zhu, Yao-Wen Chang:
Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation. 1-6 - Jiaji He, Xiaolong Guo, Haocheng Ma, Yanjiang Liu, Yiqiang Zhao, Yier Jin:
Runtime Trust Evaluation and Hardware Trojan Detection Using On-Chip EM Sensors. 1-6 - Haoxing Ren, George F. Kokai, Walker J. Turner, Ting-Sheng Ku:
ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks. 1-6 - Thierry Tambe, En-Yu Yang, Zishen Wan, Yuntian Deng, Vijay Janapa Reddi, Alexander M. Rush, David Brooks, Gu-Yeon Wei:
Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference. 1-6 - Xianfeng Li, Gengchao Li, Xiaole Cui:
ReTriple: Reduction of Redundant Rendering on Android Devices for Performance and Energy Optimizations. 1-6 - Hyungjun Oh, Yongseung Yu, Giha Ryu, Gunjoo Ahn, Yuri Jeong, Yongjun Park, Jiwon Seo:
Convergence-Aware Neural Network Training. 1-6 - Jianqi Chen, Monir Zaman, Yiorgos Makris, R. D. Shawn Blanton, Subhasish Mitra, Benjamin Carrión Schäfer:
DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY. 1-6 - Daan van der Valk, Marina Krcek, Stjepan Picek, Shivam Bhasin:
Learning From A Big Brother - Mimicking Neural Networks in Profiled Side-channel Analysis. 1-6 - Prawar Poudel, Biswajit Ray, Aleksandar Milenkovic:
Flashmark: Watermarking of NOR Flash Memories for Counterfeit Detection. 1-6 - Feng Xiong, Fengbin Tu, Man Shi, Yang Wang, Leibo Liu, Shaojun Wei, Shouyi Yin:
STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction. 1-6 - Chaoqun Chu, Yanzhi Wang, Yilong Zhao, Xiaolong Ma, Shaokai Ye, Yunyan Hong, Xiaoyao Liang, Yinhe Han, Li Jiang:
PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory Architecture. 1-6 - Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu:
A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. 1-6 - Nitthilan Kanappan Jayakodi, Janardhan Rao Doppa, Partha Pratim Pande:
PETNet: Polycount and Energy Trade-off Deep Networks for Producing 3D Objects from Images. 1-6 - Yawen Wu, Zhepeng Wang, Zhenge Jia, Yiyu Shi, Jingtong Hu:
Intermittent Inference with Nonuniformly Compressed Multi-Exit Neural Network for Energy Harvesting Powered Devices. 1-6 - Soheil Nazar Shahsavani, Massoud Pedram:
TDP-ADMM: A Timing Driven Placement Approach for Superconductive Electronic Circuits Using Alternating Direction Method of Multipliers. 1-6 - Dongup Kwon, Suyeon Hur, Hamin Jang, Eriko Nurvitadhi, Jangwoo Kim:
Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels. 1-6 - Wenhan Xia, Hongxu Yin, Niraj K. Jha:
INVITED: Efficient Synthesis of Compact Deep Neural Networks. 1-6 - Wei Zhong, Shuxiang Hu, Yuzhe Ma, Haoyu Yang, Xiuyuan Ma, Bei Yu:
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization. 1-6 - Bo Qiao, M. Akif Özkan, Jürgen Teich, Frank Hannig:
The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. 1-6 - Andrew B. Kahng, Lutong Wang, Bangqi Xu:
The Tao of PAO: Anatomy of a Pin Access Oracle for Detailed Routing. 1-6 - Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. 1-6 - Xiandong Zhao, Ying Wang, Cheng Liu, Cong Shi, Kaijie Tu, Lei Zhang:
BitPruner: Network Pruning for Bit-serial Accelerators. 1-6 - Rémi Denis-Courmont, Hans Liljestrand, Carlos Chinea Perez, Jan-Erik Ekberg:
Camouflage: Hardware-assisted CFI for the ARM Linux kernel. 1-6 - Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Jürgen Teich:
Probabilistic Error Propagation through Approximated Boolean Networks. 1-6 - Jan Spieck, Stefan Wildermann, Jürgen Teich:
Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs. 1-6 - Jinho Lee, Inseok Hwang, Soham Shah, Minsik Cho:
FlexReduce: Flexible All-reduce for Distributed Deep Learning on Asymmetric Network Topology. 1-6 - Srikant Bharadwaj, Jieming Yin, Bradford M. Beckmann, Tushar Krishna:
Kite: A Family of Heterogeneous Interposer Topologies Enabled via Accurate Interconnect Modeling. 1-6 - Yina Lv, Liang Shi, Qiao Li, Chun Jason Xue, Edwin H.-M. Sha:
Access Characteristic Guided Partition for Read Performance Improvement on Solid State Drives. 1-6 - Alexander Hoffman, Anuj Pathania, Philipp H. Kindt, Samarjit Chakraborty, Tulika Mitra:
BrezeFlow: Unified Debugger for Android CPU Power Governors and Schedulers on Edge Devices. 1-6 - Rafael Billig Tonetto, Hiago Mayk G. de A. Rocha, Gabriel L. Nazar, Antonio Carlos Schneider Beck:
A Machine Learning Approach for Reliability-Aware Application Mapping for Heterogeneous Multicores. 1-6 - Arman Kazemi, Cristobal Alessandri, Alan C. Seabaugh, Xiaobo Sharon Hu, Michael T. Niemier, Siddharth Joshi:
A Device Non-Ideality Resilient Approach for Mapping Neural Networks to Crossbar Arrays. 1-6 - Kyungchul Park, Chanyoung Oh, Youngmin Yi:
BPNet: Branch-pruned Conditional Neural Network for Systematic Time-accuracy Tradeoff. 1-6 - Seyed Hamidreza Moghadas, Michael Pehl:
ROPAD: A Fully Digital Highly Predictive Ring Oscillator Probing Attempt Detector. 1-6 - Ahmad M. Radaideh, Paul V. Gratz:
Exploiting Zero Data to Reduce Register File and Execution Unit Dynamic Power Consumption in GPGPUs. 1-6 - Guido Baccelli, Dimitrios Stathis, Ahmed Hemani, Maurizio Martina:
NACU: A Non-Linear Arithmetic Unit for Neural Networks. 1-6 - Bahar Asgari, Ramyad Hadidi, Nima Shoghi Ghaleshahi, Hyesoon Kim:
PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse Algebra. 1-6 - Ji Zhang, Yuanzhang Wang, Yangtao Wang, Ke Zhou, Sebastian Schelter, Ping Huang, Bin Cheng, Yongguang Ji:
Tier-Scrubbing: An Adaptive and Tiered Disk Scrubbing Scheme with Improved MTTD and Reduced Cost. 1-6 - Po-Chun Chien, Jie-Hong R. Jiang:
Time Multiplexing via Circuit Folding. 1-6 - Rick Bahr, Clark W. Barrett, Nikhil Bhagdikar, Alex Carsello, Ross Daly, Caleb Donovick, David Durst, Kayvon Fatahalian, Kathleen Feng, Pat Hanrahan, Teguh Hofstee, Mark Horowitz, Dillon Huff, Fredrik Kjolstad, Taeyoung Kong, Qiaoyi Liu, Makai Mann, Jackson Melchert, Ankita Nayak, Aina Niemetz, Gedeon Nyengele, Priyanka Raina, Stephen Richardson, Rajsekhar Setaluri, Jeff Setter, Kavya Sreedhar, Maxwell Strange, James Thomas, Christopher Torng, Leonard Truong, Nestan Tsiskaridze, Keyi Zhang:
Creating an Agile Hardware Design Flow. 1-6 - Qing Wang, Youyou Lu, Zhongjie Wu, Fan Yang, Jiwu Shu:
Improving the Concurrency Performance of Persistent Memory Transactions on Multicores. 1-6 - Stefan Hillmich, Igor L. Markov, Robert Wille:
Just Like the Real Thing: Fast Weak Simulation of Quantum Computation. 1-6 - Quan Chen:
A Robust Exponential Integrator Method for Generic Nonlinear Circuit Simulation. 1-6 - Tianjia He, Lin Zhang, Fanxin Kong, Asif Salekin:
Exploring Inherent Sensor Redundancy for Automotive Anomaly Detection. 1-6 - Mahabubul Alam, Abdullah Ash-Saki, Swaroop Ghosh:
An Efficient Circuit Compilation Flow for Quantum Approximate Optimization Algorithm. 1-6 - Sunwoo Ahn, Hayoon Yi, Younghan Lee, Whoi Ree Ha, Giyeol Kim, Yunheung Paek:
Hawkware: Network Intrusion Detection based on Behavior Analysis with ANNs on an IoT Device. 1-6 - Dharanidhar Dang, Sahar Taheri, Bill Lin, Debashis Sahoo:
MEMTONIC: A Neuromorphic Accelerator for Energy Efficient Deep Learning. 1-2 - Haowei Deng, Yu Zhang, Quanxi Li:
Codar: A Contextual Duration-Aware Qubit Mapping for Various NISQ Devices. 1-6 - Lukas Burgholzer, Robert Wille:
The Power of Simulation for Equivalence Checking in Quantum Computing. 1-6 - Arne Hamann, Selma Saidi, David Ginthoer, Christian Wietfeld, Dirk Ziegenbein:
Building End-to-End IoT Applications with QoS Guarantees. 1-6 - Zhuoran Song, Jianfei Wang, Tianjian Li, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing:
GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor Cores. 1-6 - Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park:
Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. 1-6 - Marina Neseem, Jon Nelson, Sherief Reda:
AdaSense: Adaptive Low-Power Sensing and Activity Recognition for Wearable Devices. 1-6 - Peng Zou, Zhifeng Lin, Xiao Shi, Yingjie Wu, Jianli Chen, Jun Yu, Yao-Wen Chang:
Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification. 1-6 - Leilai Shao, Ting Lei, Tsung-Ching Huang, Zhenan Bao, Kwang-Ting Cheng:
Robust Design of Large Area Flexible Electronics via Compressed Sensing. 1-6 - Mengshu Sun, Pu Zhao, Mehmet Güngör, Massoud Pedram, Miriam Leeser, Xue Lin:
3D CNN Acceleration on FPGA using Hardware-Aware Pruning. 1-6 - Mohammad Rahmani Fadiheh, Johannes Müller, Raik Brinkmann, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz:
A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors. 1-6 - Cheng-Yun Hsieh, Chen-Hung Wu, Chia-Hsien Huang, His-Sheng Goan, James Chien-Mo Li:
Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits. 1-6 - Rui Li, Heng Yu, Weixiong Jiang, Yajun Ha:
DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs. 1-6 - Mojan Javaheripi, Huili Chen, Farinaz Koushanfar:
Unified Architectural Support for Secure and Robust Deep Learning. 1-6 - Md Fahim Faysal Khan, Mohammad Mahdi Kamani, Mehrdad Mahdavi, Vijaykrishnan Narayanan:
Learning to Quantize Deep Neural Networks: A Competitive-Collaborative Approach. 1-6 - Wenye Liu, Chip-Hong Chang, Fan Zhang, Xiaoxuan Lou:
Imperceptible Misclassification Attack on Deep Learning Accelerator by Glitch Injection. 1-6 - Ziru Li, Bonan Yan, Hai Helen Li:
ReSiPE: ReRAM-based Single-Spiking Processing-In-Memory Engine. 1-6 - Charles Gouert, Nektarios Georgios Tsoutsos:
Romeo: Conversion and Evaluation of HDL Designs in the Encrypted Domain. 1-6 - Mohamed Baker Alawieh, Duane S. Boning, David Z. Pan:
Wafer Map Defect Patterns Classification using Deep Selective Learning. 1-6 - Runbin Shi, Yuhao Ding, Xuechao Wei, He Li, Hang Liu, Hayden Kwok-Hay So, Caiwen Ding:
FTDL: A Tailored FPGA-Overlay for Deep Learning with High Scalability. 1-6 - Yi-Chen Lu, Sai Surya Kiran Pentapati, Lingjun Zhu, Kambiz Samadi, Sung Kyu Lim:
TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs. 1-6 - Yijie Wei, Kofi Otseidu, Jie Gu:
Exploration of Design Space and Runtime Optimization for Affective Computing in Machine Learning Empowered Ultra-Low Power SoC. 1-6 - Maolin Yang, Ze-Wei Chen, Xu Jiang, Nan Guan, Hang Lei:
DPCP-p: A Distributed Locking Protocol for Parallel Real-Time Tasks. 1-6 - Inayat Ullah, Kashif Inayat, Joon-Sung Yang, Jaeyong Chung:
Factored Radix-8 Systolic Array for Tensor Processing. 1-6 - Marcelo Brandalero, Bernardo Neuhaus Lignati, Antonio Carlos Schneider Beck, Muhammad Shafique, Michael Hübner:
Proactive Aging Mitigation in CGRAs through Utilization-Aware Allocation. 1-6 - Jinrong Guo, Songlin Hu, Wang Wang, Chunrong Yao, Jizhong Han, Ruixuan Li, Yijun Lu:
Tail: An Automated and Lightweight Gradient Compression Framework for Distributed Deep Learning. 1-6 - Xun Jiao, Dongning Ma, Wanli Chang, Yu Jiang:
TEVoT: Timing Error Modeling of Functional Units under Dynamic Voltage and Temperature Variations. 1-6 - Xi Wang, Brody Williams, John D. Leidel, Alan Ehret, Michel A. Kinsy, Yong Chen:
Remote Atomic Extension (RAE) for Scalable High Performance Computing. 1-6 - Qilin Zheng, Zongwei Wang, Zishun Feng, Bonan Yan, Yimao Cai, Ru Huang, Yiran Chen, Chia-Lin Yang, Hai Helen Li:
Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks. 1-6 - Igor L. Markov, Aneeqa Fatima, Sergei V. Isakov, Sergio Boixo:
Massively Parallel Approximate Simulation of Hard Quantum Circuits. 1-6 - Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng:
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis. 1-6 - Jiaqi Gu, Zheng Zhao, Chenghao Feng, Wuxi Li, Ray T. Chen, David Z. Pan:
FLOPS: EFficient On-Chip Learning for OPtical Neural Networks Through Stochastic Zeroth-Order Optimization. 1-6 - Nguyen-Dong Ho, Minh-Son Le, Ik-Joon Chang:
O-2A: Low Overhead DNN Compression with Outlier-Aware Approximation. 1-6 - Daniele Jahier Pagliari, Roberta Chiaro, Yukai Chen, Sara Vinco, Enrico Macii, Massimo Poncino:
Input-Dependent Edge-Cloud Mapping of Recurrent Neural Networks Inference. 1-6 - Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane:
Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator. 1-6 - Nils Heitmann, Philipp H. Kindt, Samarjit Chakraborty:
Late Breaking Results: Can You Hear Me? Towards an Ultra Low-Cost Hearing Screening Device. 1-2 - Dmitry Utyamishev, Inna Partin-Vaisband:
Late Breaking Results: A Neural Network that Routes ICs. 1-2 - Minghua Wang, Zhi Zhang, Yueqiang Cheng, Surya Nepal:
DRAMDig: A Knowledge-assisted Tool to Uncover DRAM Address Mapping. 1-6 - Akashdeep Saha, Sayandeep Saha, Siddhartha Chowdhury, Debdeep Mukhopadhyay, Bhargab B. Bhattacharya:
LoPher: SAT-Hardened Logic Embedding on Block Ciphers. 1-6 - Debjit Sinha, Vasant Rao, Chaitanya Peddawad, Michael H. Wood, Jeffrey G. Hemmett, Suriya Skariah, Patrick Williams:
Statistical Timing Analysis considering Multiple-Input Switching. 1-6 - Wenfei Hu, Zuochang Ye, Yan Wang:
Adjoint Transient Sensitivity Analysis for Objective Functions Associated to Many Time Points. 1-6 - Zhengxiong Luo, Feilong Zuo, Yuheng Shen, Xun Jiao, Wanli Chang, Yu Jiang:
ICS Protocol Fuzzing: Coverage Guided Packet Crack and Generation. 1-6 - Sumit K. Mandal, Ümit Y. Ogras, Janardhan Rao Doppa, Raid Zuhair Ayoub, Michael Kishinevsky, Partha Pratim Pande:
Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCs. 1-6 - Gouranga Charan, Jubin Hazra, Karsten Beckmann, Xiaocong Du, Gokul Krishnan, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao:
Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation. 1-6 - Yuyang Wang, Jared Hulme, Peng Sun, Mudit Jain, M. Ashkan Seyedi, Marco Fiorentino, Raymond G. Beausoleil, Kwang-Ting Cheng:
Characterization and Applications of Spatial Variation Models for Silicon Microring-Based Optical Transceivers. 1-6 - Tzu-Wei Wang, Po-Chang Wu, Mark Po-Hung Lin:
Late Breaking Results: Automatic Adaptive MOM Capacitor Cell Generation for Analog and Mixed-Signal Layout Design. 1-2 - Wei-Lin Wang, Tseng-Yi Chen, Yuan-Hao Chang, Hsin-Wen Wei, Wei-Kuan Shih:
How to Cut Out Expired Data with Nearly Zero Overhead for Solid-State Drives. 1-6 - Xiaodong Wang, Tianchen Gu, Changhao Yan, Xiulong Wu, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits. 1-6 - Mohammad A. Alshboul, James Tuck, Yan Solihin:
WET: Write Efficient Loop Tiling for Non-Volatile Main Memory. 1-6 - Natasha Yogananda Jeppu, Thomas F. Melham, Daniel Kroening, John O'Leary:
Learning Concise Models from Long Execution Traces. 1-6 - Jeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericàs, Antonio Carlos Schneider Beck:
Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction Offloading. 1-6 - Aein Rezaei Shahmirzadi, Shahram Rasoolzadeh, Amir Moradi:
Impeccable Circuits II. 1-6 - James Geist, Travis Meade, Shaojie Zhang, Yier Jin:
RELIC-FUN: Logic Identification through Functional Signal Comparisons. 1-6 - Chau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang:
Latch Clustering for Timing-Power Co-Optimization. 1-6 - Sabur Baidya, Yu-Jen Ku, Hengyu Zhao, Jishen Zhao, Sujit Dey:
Vehicular and Edge Computing for Emerging Connected and Autonomous Vehicle Applications. 1-6 - Hsiang-Ting Wen, Yu-Jie Cai, Yang Hsu, Yao-Wen Chang:
Via-based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures. 1-6 - Khushboo Rani, Hemangee K. Kapoor:
ZENCO: Zero-bytes based ENCOding for Non-Volatile Buffers in On-Chip Interconnects. 1-6 - Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan:
Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. 1-6 - Han Xu, Maimaiti Nazhamaiti, Yidong Liu, Fei Qiao, Qi Wei, Xinjun Liu, Huazhong Yang:
Utilizing Direct Photocurrent Computation and 2D Kernel Scheduling to Improve In-Sensor-Processing Efficiency. 1-6 - Shan Shen, Liang Pang, Tianxiang Shao, Ming Ling, Xiao Shi, Longxing Shi:
TYMER: A Yield-based Performance Model for Timing-speculation SRAM. 1-6 - Abraham Addisie, Valeria Bertacco:
Centaur: Hybrid Processing in On/Off-chip Memory Architecture for Graph Analytics. 1-6 - Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang:
Topological Structure and Physical Layout Codesign for Wavelength-Routed Optical Networks-on-Chip. 1-6 - Chaoshu Yang, Duo Liu, Runyu Zhang, Xianzhang Chen, Shun Nie, Fengshun Wang, Qingfeng Zhuge, Edwin H.-M. Sha:
Efficient Multi-Grained Wear Leveling for Inodes of Persistent Memory File Systems. 1-6 - Chang Meng, Weikang Qian, Alan Mishchenko:
ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set. 1-6 - Kartikeya Bhardwaj, Wei Chen, Radu Marculescu:
INVITED: New Directions in Distributed Deep Learning: Bringing the Network at Forefront of IoT Design. 1-6 - Vladimir Herdt, Daniel Große, Rolf Drechsler:
Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side*. 1-6 - Jingyu Wang, Songming Yu, Jinshan Yue, Zhe Yuan, Zhuqing Yuan, Huazhong Yang, Xueqing Li, Yongpan Liu:
High PE Utilization CNN Accelerator with Channel Fusion Supporting Pattern-Compressed Sparse Neural Networks. 1-6 - Shiqiang Nie, Youtao Zhang, Weiguo Wu, Jun Yang:
Layer RBER Variation Aware Read Performance Optimization for 3D Flash Memories. 1-6 - Scott Beamer, David Donofrio:
Efficiently Exploiting Low Activity Factors to Accelerate RTL Simulation. 1-6 - Nuo Xu, Qi Liu, Tao Liu, Zihao Liu, Xiaochen Guo, Wujie Wen:
Stealing Your Data from Compressed Machine Learning Models. 1-6 - Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin:
Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization. 1-2 - Runyu Zhang, Duo Liu, Xianzhang Chen, Xiongxiong She, Chaoshu Yang, Yujuan Tan, Zhaoyan Shen, Zili Shao:
LOFFS: A Low-Overhead File System for Large Flash Memory on Embedded Devices. 1-6 - Chenlin Ma, Yi Wang, Zhaoyan Shen, Zili Shao:
KFR: Optimal Cache Management with K-Framed Reclamation for Drive-Managed SMR Disks. 1-6 - Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang:
A Provably Good Wavelength-Division-Multiplexing-Aware Clustering Algorithm for On-Chip Optical Routing. 1-6 - Yuhao Zhang, Zhiping Jia, Yungang Pan, Hongchao Du, Zhaoyan Shen, Mengying Zhao, Zili Shao:
PattPIM: A Practical ReRAM-Based DNN Accelerator by Reusing Weight Pattern Repetitions. 1-6 - Dimitris Mouris, Nektarios Georgios Tsoutsos:
Pythia: Intellectual Property Verification in Zero-Knowledge. 1-6 - Daniel Casini, Paolo Pazzaglia, Alessandro Biondi, Marco Di Natale, Giorgio C. Buttazzo:
Predictable Memory-CPU Co-Scheduling with Support for Latency-Sensitive Tasks. 1-6 - Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler:
Verification for Field-coupled Nanocomputing Circuits. 1-6 - Tsun-Yu Yang, Ming-Chang Yang, Jiawei Li, Wang Kang:
Permutation-Write: Optimizing Write Performance and Energy for Skyrmion Racetrack Memory. 1-6 - Yanqing Zhang, Haoxing Ren, Brucek Khailany:
GRANNITE: Graph Neural Network Inference for Transferable Power Estimation. 1-6 - Maohua Zhu, Yuan Xie:
Taming Unstructured Sparsity on GPUs via Latency-Aware Optimization. 1-6 - Fei Sun, Minghai Qin, Tianyun Zhang, Liu Liu, Yen-Kuang Chen, Yuan Xie:
INVITED: Computation on Sparse Neural Networks and its Implications for Future Hardware. 1-6 - Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young:
CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model. 1-6 - Liang Wang, Leibo Liu, Xiaohang Wang, Jie Han, Chenchen Deng, Shaojun Wei:
CDRing: Reconfigurable Ring Architecture by Exploiting Cycle Decomposition of Torus Topology. 1-6 - Hengli Huang, Xiaohang Wang, Yingtao Jiang, Amit Kumar Singh, Mei Yang, Letian Huang:
On Countermeasures Against the Thermal Covert Channel Attacks Targeting Many-core Systems. 1-6 - Dennis Leander Wolf, Christoph Spang, Christian Hochberger:
Towards Purposeful Design Space Exploration of Heterogeneous CGRAs: Clock Frequency Estimation. 1-6 - Dongyeob Shin, Geonho Kim, Joongho Jo, Jongsun Park:
Prediction Confidence based Low Complexity Gradient Computation for Accelerating DNN Training. 1-6 - Abhishek Chakraborty, Ankit Mondal, Ankur Srivastava:
Hardware-Assisted Intellectual Property Protection of Deep Learning Models. 1-6 - Francesco Restuccia, Alessandro Biondi, Mauro Marinoni, Giorgiomaria Cicero, Giorgio C. Buttazzo:
AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC. 1-6 - Shaahin Angizi, Naima Ahmed Fahmi, Wei Zhang, Deliang Fan:
PIM-Assembler: A Processing-in-Memory Platform for Genome Assembly. 1-6 - Hao Zheng, Ke Wang, Ahmed Louri:
A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures. 1-6 - Bing Liu, Sara Safa:
A Model Checking-based Analysis Framework for Systems Biology Models. 1-6 - Soroush Ghodrati, Hardik Sharma, Cliff Young, Nam Sung Kim, Hadi Esmaeilzadeh:
Bit-Parallel Vector Composability for Neural Acceleration. 1-6 - Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim:
Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead. 1-6 - Payman Behnam, Mahdi Nazm Bojnordi:
RedCache: Reduced DRAM Caching. 1-6 - Stefano Aldegheri, Nicola Bombieri, Franco Fummi, Simone Girardi, Riccardo Muradore, Nicola Piccinelli:
Late Breaking Results: Enabling Containerized Computing and Orchestration of ROS-based Robotic SW Applications on Cloud-Server-Edge Architectures. 1-2 - Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao:
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. 1-6 - Andreas Kurth, Samuel Riedel, Florian Zaruba, Torsten Hoefler, Luca Benini:
ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor. 1-6 - Huili Chen, Siam Umar Hussain, Fabian Boemer, Emmanuel Stapf, Ahmad-Reza Sadeghi, Farinaz Koushanfar, Rosario Cammarota:
Developing Privacy-preserving AI Systems: The Lessons learned. 1-4 - Panagiota Kiourti, Kacper Wardega, Susmit Jha, Wenchao Li:
TrojDRL: Evaluation of Backdoor Attacks on Deep Reinforcement Learning. 1-6 - Ardhi Wiratama Baskara Yudha, Reza Pulungan, Henry Hoffmann, Yan Solihin:
A Simple Cache Coherence Scheme for Integrated CPU-GPU Systems. 1-6 - Jingtao Li, Adnan Siraj Rakin, Yan Xiong, Liangliang Chang, Zhezhi He, Deliang Fan, Chaitali Chakrabarti:
Defending Bit-Flip Attack through DNN Weight Reconstruction. 1-6 - Gushu Li, Yufei Ding, Yuan Xie:
Eliminating Redundant Computation in Noisy Quantum Computing Simulation. 1-6 - Tung-Wei Lin, Wei-Chen Tai, Yu-Cheng Lin, Iris Hui-Ru Jiang:
Routing Topology and Time-Division Multiplexing Co-Optimization for Multi-FPGA Systems. 1-6 - Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin:
TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. 1-6 - Vidushi Goyal, Valeria Bertacco, Reetuparna Das:
Seesaw: End-to-end Dynamic Sensing for IoT using Machine Learning. 1-19 - Chungseop Lee, Keonhyuk Lee, Mingoo Kang, Hyukjun Lee:
EANeM: Energy-Aware Network Stack Management for Mobile Devices. 1-6 - Louis K. Scheffer:
INVITED: Computational Methods of Biological Exploration. 1-4 - Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique:
DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural Networks. 1-6 - M. Hüsrev Cilasun, Salonik Resch, Zamshed Iqbal Chowdhury, Erin Olson, Masoud Zabihi, Zhengyang Zhao, Thomas Peterson, Jianping Wang, Sachin S. Sapatnekar, Ulya R. Karpuzcu:
CRAFFT: High Resolution FFT Accelerator In Spintronic Computational RAM. 1-6 - Zi Wang, Benjamin Carrión Schäfer:
Machine Leaming to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration. 1-6 - Qi Liu, Tao Liu, Zihao Liu, Wujie Wen, Chengmo Yang:
Monitoring the Health of Emerging Neural Network Accelerators with Cost-effective Concurrent Test. 1-6 - Lei Yang, Zheyu Yan, Meng Li, Hyoukjun Kwon, Liangzhen Lai, Tushar Krishna, Vikas Chandra, Weiwen Jiang, Yiyu Shi:
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks. 1-6 - Zhe Zhou, Xintong Li, Xiaoyang Wang, Zheng Liang, Guangyu Sun, Guojie Luo:
Hardware-assisted Service Live Migration in Resource-limited Edge Computing Systems. 1-6 - Muhammad Abdullah Hanif, Rehan Hafiz, Osman Hasan, Muhammad Shafique:
PEMACx: A Probabilistic Error Analysis Methodology for Adders with Cascaded Approximate Units. 1-6 - Zhe Yang, Youyou Lu, Erci Xu, Jiwu Shu:
CoinPurse: A Device-Assisted File System with Dual Interfaces. 1-6 - Yuze Chi, Jason Cong:
Exploiting Computation Reuse for Stencil Accelerators. 1-6 - Wenjie Fu, Leilei Jin, Ming Ling, Yu Zheng, Longxing Shi:
A Cross-Layer Power and Timing Evaluation Method for Wide Voltage Scaling. 1-6 - Zhangyu Chen, Yu Hua, Pengfei Zuo, Yuanyuan Sun, Yuncheng Guo:
Reducing Bit Writes in Non-volatile Main Memory by Similarity-aware Compression. 1-6 - Hanchen Ye, Xiaofan Zhang, Zhize Huang, Gengsheng Chen, Deming Chen:
HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation. 1-6 - Raviv Gal, Haim Kermany, Alexander Ivrii, Ziv Nevo, Avi Ziv:
Late Breaking Results: FRIENDS - Finding Related Interesting Events via Neighbor Detection. 1-2 - Shuai Zhao, Zhe Jiang, Xiaotian Dai, Iain Bate, Ibrahim Habli, Wanli Chang:
Timing-Accurate General-Purpose I/O for Multi- and Many-Core Systems: Scheduling and Hardware Support. 1-6 - Ali Heydari Gorji, Mahdi Torabzadehkashi, Siavash Rezaei, Hossein Bobarshad, Vladimir Castro Alves, Pai H. Chou:
Stannis: Low-Power Acceleration of DNN Training Using Computational Storage Devices. 1-6 - Indranil Chakraborty, Mustafa Fayez Ali, Dong Eun Kim, Aayush Ankit, Kaushik Roy:
GENIEx: A Generalized Approach to Emulating Non-Ideality in Memristive Xbars using Neural Networks. 1-6 - Seongsik Park, Sei Joon Kim, Byunggook Na, Sungroh Yoon:
T2FSNN: Deep Spiking Neural Networks with Time-to-first-spike Coding. 1-6 - Majid Sabbagh, Yunsi Fei, David R. Kaeli:
A Novel GPU Overdrive Fault Attack. 1-6 - Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli:
SAT-Sweeping Enhanced for Logic Synthesis. 1-6 - Danielle Tchuinkou Kwadjo, Christophe Bobda:
Late Breaking Results: Automated Hardware Generation of CNN Models on FPGAs. 1-2 - Fan Zhang, Bin Shao, Guorui Xu, Bolin Yang, Ziqi Yang, Zhan Qin, Kui Ren:
From Homogeneous to Heterogeneous: Leveraging Deep Learning based Power Analysis across Devices. 1-6 - Zhenkun Yang, Yuriy Viktorov, Jin Yang, Jiewen Yao, Vincent Zimmer:
UEFI Firmware Fuzzing with Simics Virtual Platform. 1-6 - Akira Dan, Riu Shimizu, Takeshi Nishikawa, Song Bian, Takashi Sato:
Clustering Approach for Solving Traveling Salesman Problems via Ising Model Based Solver. 1-6 - Yan Li, Xiaoyoung Zeng, Zhengqi Gao, Liyu Lin, Jun Tao, Jun Han, Xu Cheng, Mehdi B. Tahoori, Xiaoyang Zeng:
Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit. 1-6 - Navid Khoshavi, Arman Roohi, Connor Broyles, Saman Sargolzaei, Yu Bi, David Z. Pan:
SHIELDeNN: Online Accelerated Framework for Fault-Tolerant Deep Neural Network Architectures. 1-6 - Babak Zamirai, Salar Latifi, Pedram Zamirai, Scott A. Mahlke:
SIEVE: Speculative Inference on the Edge with Versatile Exportation. 1-6 - Zhifeng Lin, Yanyue Xie, Gang Qian, Sifei Wang, Jun Yu, Jianli Chen:
Late Breaking Results: An Analytical Timing-Driven Placer for Heterogeneous FPGAs*. 1-2 - Jiandong Mu, Mengdi Wang, Lanbo Li, Jun Yang, Wei Lin, Wei Zhang:
A History-Based Auto-Tuning Framework for Fast and High-Performance DNN Design on GPU. 1-6 - Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui:
Tight Compression: Compressing CNN Model Tightly Through Unstructured Pruning and Simulated Annealing Based Permutation. 1-6 - Hua Wang, Yang Yang, Ping Huang, Yu Zhang, Ke Zhou, Mengling Tao, Bin Cheng:
S-CDA: A Smart Cloud Disk Allocation Approach in Cloud Block Storage System. 1-6 - Ankit Mondal, Michael Zuzak, Ankur Srivastava:
StatSAT: A Boolean Satisfiability based Attack on Logic-Locked Probabilistic Circuits. 1-6 - Aibin Yan, Xiangfeng Feng, Xiaohu Zhao, Hang Zhou, Jie Cui, Zuobin Ying, Patrick Girard, Xiaoqing Wen:
HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications. 1-6 - Benjamin Hettwer, Daniel Fennes, Sebastien Leger, Jan Richter-Brockmann, Stefan Gehrer, Tim Güneysu:
Deep Learning Multi-Channel Fusion Attack Against Side-Channel Protected Hardware. 1-6 - Wei Li, Jialu Xia, Yuzhe Ma, Jialu Li, Yibo Lin, Bei Yu:
Adaptive Layout Decomposition with Graph Embedding Neural Networks. 1-6 - Cheng Gongye, Yunsi Fei, Thomas Wahl:
Reverse-Engineering Deep Neural Networks Using Floating-Point Timing Side-Channels. 1-6 - Yu-Pei Liang, Tseng-Yi Chen, Ching-Ho Chi, Hsin-Wen Wei, Wei-Kuan Shih:
Enabling a B+-tree-based Data Management Scheme for Key-value Store over SMR-based SSHD. 1-6 - Yuxin Yang, Xiaoming Chen, Yinhe Han:
Dadu-CD: Fast and Efficient Processing-in-Memory Accelerator for Collision Detection. 1-6 - Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen, Weisheng Zhao:
SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training. 1-6 - Jiho Kim, John Kim, Yongjun Park:
Navigator: Dynamic Multi-kernel Scheduling to Improve GPU Performance. 1-6 - Hsien-Han Cheng, Iris Hui-Ru Jiang, Oscar Ou:
Fast and Accurate Wire Timing Estimation on Tree and Non-Tree Net Structures. 1-6 - Bharath Srinivas Prabakaran, Alberto García Jiménez, Germán Moltó Martínez, Muhammad Shafique:
EMAP: A Cloud-Edge Hybrid Framework for EEG Monitoring and Cross-Correlation Based Real-time Anomaly Prediction. 1-6 - Po-Yao Chuang, Pai-Yu Tan, Cheng-Wen Wu, Juin-Ming Lu:
A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification. 1-6 - Eshan Singh, Florian Lonsing, Saranyu Chattopadhyay, Maxwell Strange, Peng Wei, Xiaofan Zhang, Yuan Zhou, Deming Chen, Jason Cong, Priyanka Raina, Zhiru Zhang, Clark W. Barrett, Subhasish Mitra:
A-QED Verification of Hardware Accelerators. 1-6 - Eunji Kwon, Sodam Han, Yoonho Park, Young Hwan Kim, Seokhyeong Kang:
Late Breaking Results: Reinforcement Learning-based Power Management Policy for Mobile Device Systems. 1-2 - Jincheng Yu, Zhilin Xu, Shulin Zeng, Chao Yu, Jiantao Qiu, Chaoyang Shen, Yuanfan Xu, Guohao Dai, Yu Wang, Huazhong Yang:
INCA: INterruptible CNN Accelerator for Multi-tasking in Embedded Robots. 1-6 - Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong:
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. 1-6 - Xin Xin, Youtao Zhang, Jun Yang:
Reducing DRAM Access Latency via Helper Rows. 1-6 - Vikram B. Suresh, Raghavan Kumar, Sanu Mathew:
INVITED: A 0.26% BER, Machine-Learning Resistant 1028 Challenge-Response PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection. 1-3 - Christoph Scholl, Alexander Konrad:
Symbolic Computer Algebra and SAT Based Information Forwarding for Fully Automatic Divider Verification. 1-6 - Weiqing Ji, Tsung-Yi Ho, Hailong Yao:
Transfer Learning-Based Microfluidic Design System for Concentration Generation∗. 1-6 - Seungho Han, Sungyu Jeong, Chanho Kim, Hong-June Park, Byungsub Kim:
GUI-Enhanced Layout Generation of FFE SST TXs for Fast High-Speed Serial Link Design. 1-6 - Songyun Qu, Bing Li, Ying Wang, Dawen Xu, Xiandong Zhao, Lei Zhang:
RaQu: An automatic high-utilization CNN quantization and mapping framework for general-purpose RRAM Accelerator. 1-6 - Hongyu Fang, Milos Doroslovacki, Guru Venkataramani:
Reuse-trap: Re-purposing Cache Reuse Distance to Defend against Side Channel Leakage. 1-6 - Donghyun Kang, Soonhoi Ha:
Tensor Virtualization Technique to Support Efficient Data Reorganization for CNN Accelerators. 1-6 - Jose Maria Bermudo Mera, Furkan Turan, Angshuman Karmakar, Sujoy Sinha Roy, Ingrid Verbauwhede:
Compact domain-specific co-processor for accelerating module lattice-based KEM. 1-6 - Isak Edo Vivancos, Sayeh Sharify, Milos Nikolic, Ciaran Bannon, Mostafa Mahmoud, Alberto Delmas Lascorz, Andreas Moshovos:
Late Breaking Results: Building an On-Chip Deep Learning Memory Hierarchy Brick by Brick. 1-2 - Yintao He, Ying Wang, Xiandong Zhao, Huawei Li, Xiaowei Li:
Towards State-Aware Computation in ReRAM Neural Networks. 1-6 - Hamid Nejatollahi, Saransh Gupta, Mohsen Imani, Tajana Simunic Rosing, Rosario Cammarota, Nikil D. Dutt:
CryptoPIM: In-memory Acceleration for Lattice-based Cryptographic Hardware. 1-6 - Cong Guo, Yangjie Zhou, Jingwen Leng, Yuhao Zhu, Zidong Du, Quan Chen, Chao Li, Bin Yao, Minyi Guo:
Balancing Efficiency and Flexibility for DNN Acceleration via Temporal GPU-Systolic Array Integration. 1-6 - Sina Asadi, M. Hassan Najafi:
Late Breaking Results: LDFSM: A Low-Cost Bit-Stream Generator for Low-Discrepancy Stochastic Computing. 1-2 - Sotirios Xydis, Eleftherios-Iordanis Christoforidis, Dimitrios Soudris:
DDOT: Data Driven Online Tuning for energy efficient acceleration. 1-6 - Sugil Lee, Giju Jung, Mohammed E. Fouda, Jongeun Lee, Ahmed M. Eltawil, Fadi J. Kurdahi:
Learning to Predict IR Drop with Effective Training for ReRAM-based Neural Network Hardware. 1-6 - Li Yang, Zhezhi He, Yu Cao, Deliang Fan:
Non-uniform DNN Structured Subnets Sampling for Dynamic Inference. 1-6 - Yun Long, Edward Lee, Daehyun Kim, Saibal Mukhopadhyay:
Q-PIM: A Genetic Algorithm based Flexible DNN Quantization Method and Application to Processing-In-Memory Platform. 1-6 - Yu Liu, Hong Jiang, Yangtao Wang, Ke Zhou, Yifei Liu, Li Liu:
Content Sifting Storage: Achieving Fast Read for Large-scale Image Dataset Analysis. 1-6 - Chien-Pang Lu, Iris Hui-Ru Jiang, Chih-Wen Yang:
Late Breaking Results: Design Dependent Mega Cell Methodology for Area and Power Optimization. 1-2 - Chubo Liu, Kenli Li, Mingcong Song, Jiechen Zhao, Keqin Li, Tao Li, Zihao Zeng:
CoExe: An Efficient Co-execution Architecture for Real-Time Neural Network Services. 1-6 - Maedeh Hemmat, Joshua San Miguel, Azadeh Davoodi:
CAP'NN: Class-Aware Personalized Neural Network Inference. 1-6 - Chao Huang, Shichao Xu, Zhilu Wang, Shuyue Lan, Wenchao Li, Qi Zhu:
Opportunistic Intermittent Control with Safety Guarantees for Autonomous Systems. 1-6 - Yongchen Wang, Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li:
An Efficient Deep Learning Accelerator for Compressed Video Analysis. 1-6 - Jinghao Sun, Feng Li, Nan Guan, Wentao Zhu, Minjie Xiang, Zhishan Guo, Wang Yi:
On Computing Exact WCRT for DAG Tasks†. 1-6 - Sangmok Jeong, SeungYup Kang, Joon-Sung Yang:
PAIR: Pin-aligned In-DRAM ECC architecture using expandability of Reed-Solomon code. 1-6 - Alberto Marchisio, Beatrice Bussolino, Alessio Colucci, Maurizio Martina, Guido Masera, Muhammad Shafique:
Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks. 1-6 - Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar:
CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems. 1-6 - Qingcheng Xiao, Liqiang Lu, Jiaming Xie, Yun Liang:
FCNNLib: An Efficient and Flexible Convolution Algorithm Library on FPGAs. 1-6 - Yuhong Li, Cong Hao, Xiaofan Zhang, Xinheng Liu, Yao Chen, Jinjun Xiong, Wen-mei W. Hwu, Deming Chen:
EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions. 1-6 - Guannan Guo, Tsung-Wei Huang, Chun-Xun Lin, Martin D. F. Wong:
An Efficient Critical Path Generation Algorithm Considering Extensive Path Constraints. 1-6 - Adam Auten, Matthew Tomei, Rakesh Kumar:
Hardware Acceleration of Graph Neural Networks. 1-6 - Lei Zhao, Youtao Zhang, Jun Yang:
SCA: A Secure CNN Accelerator for Both Training and Inference. 1-6 - Jinli Yan, Wei Quan, Xiangrui Yang, Wenwen Fu, Yue Jiang, Hui Yang, Zhigang Sun:
TSN-Builder: Enabling Rapid Customization of Resource-Efficient Switches for Time-Sensitive Networking. 1-6 - Hameedah Sultan, Smruti R. Sarangi:
VarSim: A Fast and Accurate Variability and Leakage Aware Thermal Simulator. 1-6 - Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert J. Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Charles Wright, Jerry Zhao, Jonathan Bachrach, Yakun Sophia Shao, Borivoje Nikolic, Krste Asanovic:
Invited: Chipyard - An Integrated SoC Research and Implementation Environment. 1-6 - Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han:
GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. 1-6
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