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2020 – today
- 2024
[j5]Yoshinori Nishi
, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. IEEE J. Solid State Circuits 59(4): 1146-1157 (2024)- [c15]Walker J. Turner, John W. Poulton, Yoshinori Nishi, Xi Chen, Brian Zimmer, Sanquan Song, John M. Wilson, William J. Dally, C. Thomas Gray:
Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications. CICC 2024: 1-7 - 2023
- [j4]Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. IEEE J. Solid State Circuits 58(4): 1062-1073 (2023) - [c14]Hao Chen, Kai-Chieh Hsu, Walker J. Turner, Po-Hsuan Wei, Keren Zhu, David Z. Pan, Haoxing Ren:
Reinforcement Learning Guided Detailed Routing for Custom Circuits. ISPD 2023: 26-34 - [c13]Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j3]Nandish Mehta, Stephen G. Tell, Walker J. Turner, Lamar Tatro, Jih Ren Goh, C. Thomas Gray:
An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop. IEEE J. Solid State Circuits 57(10): 2898-2908 (2022) - [c12]Hao Chen, Walker J. Turner, David Z. Pan, Haoxing Ren:
Routability-Aware Placement for Advanced FinFET Mixed-Signal Circuits using Satisfiability Modulo Theories. DATE 2022: 160-165 - [c11]Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren:
TAG: Learning Circuit Spatial Embedding from Layouts. ICCAD 2022: 66:1-66:9 - [c10]Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, Haoxing Ren:
AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies. ISPD 2022: 175-183 - [c9]Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray:
A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. VLSI Technology and Circuits 2022: 154-155 - [i1]Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren:
TAG: Learning Circuit Spatial Embedding From Layouts. CoRR abs/2209.03465 (2022) - 2021
- [c8]Nandish Mehta, Stephen G. Tell, Walker J. Turner, Lamar Tatro, Giant Goh, C. Thomas Gray:
A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop. A-SSCC 2021: 1-3 - [c7]Mingjie Liu, Walker J. Turner, George F. Kokai, Brucek Khailany, David Z. Pan, Haoxing Ren:
Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization. DATE 2021: 1372-1377 - 2020
- [c6]Haoxing Ren, George F. Kokai, Walker J. Turner, Ting-Sheng Ku:
ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks. DAC 2020: 1-6 - [c5]Xi Chen, Nikola Nedovic, Stephen G. Tell, Sudhir S. Kudva, Brian Zimmer, Thomas H. Greer, John W. Poulton, Sanquan Song, Walker J. Turner, John M. Wilson, C. Thomas Gray:
6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links. ISSCC 2020: 126-128
2010 – 2019
- 2019
- [j2]John W. Poulton, John M. Wilson, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally:
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. IEEE J. Solid State Circuits 54(1): 43-54 (2019) - [c4]Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally:
A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. CICC 2019: 1-4 - 2018
- [c3]Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray:
Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. CICC 2018: 1-8 - [c2]John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally:
A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. ISSCC 2018: 276-278 - 2016
- [j1]Walker J. Turner, Rizwan Bashirullah:
A 4.7 T/11.1 T NMR Compliant 50 nW Wirelessly Programmable Implant for Bioartificial Pancreas In Vivo Monitoring. IEEE J. Solid State Circuits 51(2): 473-483 (2016) - 2014
- [c1]Walker J. Turner, Rizwan Bashirullah:
A 4.7T/11.1T NMR compliant wirelessly programmable implant for bio-artificial pancreas in vivo monitoring. VLSIC 2014: 1-2
Coauthor Index
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