Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDICCAD 2022: San Diego, CA, USA
- Tulika Mitra, Evangeline F. Y. Young, Jinjun Xiong:
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2022, San Diego, California, USA, 30 October 2022 - 3 November 2022. ACM 2022, ISBN 978-1-4503-9217-4
The Role of Graph Neural Networks in Electronic Design Automation
- Haoxing Ren, Siddhartha Nath, Yanqing Zhang, Hao Chen, Mingjie Liu:
Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper). 1:1-1:8 - Yi-Chen Lu, Sung Kyu Lim:
On Advancing Physical Design Using Graph Neural Networks. 2:1-2:7 - Daniela Sanchez Lopera
, Wolfgang Ecker:
Applying GNNs to Timing Estimation at RTL. 3:1-3:8 - Lilas Alrahis, Satwik Patnaik, Muhammad Shafique, Ozgur Sinanoglu:
Embracing Graph Neural Networks for Hardware Security. 4:1-4:9
Compiler and System-Level Techniques for Efficient Machine Learning
- Mahmut T. Kandemir, Xulong Tang, Jagadish Kotra, Mustafa Karaköy:
Fine-Granular Computation and Data Layout Reorganization for Improving Locality. 5:1-5:9 - Nicolas Bohm Agostini, Serena Curzel, Vinay Amatya, Cheng Tan, Marco Minutoli, Vito Giovanni Castellana, Joseph B. Manzano, David R. Kaeli, Antonino Tumeo:
An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration. 6:1-6:9 - Yingjie Li, Ruiyang Chen, Weilu Gao, Cunxi Yu:
Physics-Aware Differentiable Discrete Codesign for Diffractive Optical Neural Networks. 7:1-7:9 - Gokul Krishnan, A. Alper Goksoy, Sumit K. Mandal, Zhenyu Wang, Chaitali Chakrabarti, Jae-sun Seo, Ümit Y. Ogras, Yu Cao:
Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture. 8:1-8:9
Addressing Sensor Security through Hardware/Software Co-Design
- Marilyn Wolf, Kruttidipta Samal:
Attacks on Image Sensors. 9:1-9:6 - Dimitrios Serpanos:
False Data Injection Attacks on Sensor Systems. 10:1-10:5 - Ningyuan Cao, Jianbo Liu, Boyang Cheng, Muya Chang:
Stochastic Mixed-Signal Circuit Design for In-Sensor Privacy. 11:1-11:9 - Anomadarshi Barua, Mohammad Abdullah Al Faruque:
Sensor Security: Current Progress, Research Challenges, and Future Roadmap (Invited Paper). 12:1-12:7
Advances in Partitioning and Physical Optimization
- Ismail Bustany, Andrew B. Kahng, Ioannis Koutis, Bodhisatta Pramanik, Zhiang Wang:
SpecPart: A Supervised Spectral Framework for Hypergraph Partitioning Solution Improvement. 13:1-13:9 - Ali Aghdaei, Zhuo Feng:
HyperEF: Spectral Hypergraph Coarsening by Effective-Resistance Clustering. 14:1-14:9 - Soomin Kim, Taewhan Kim:
Design and Technology Co-Optimization Utilizing Multi-Bit Flip-Flop Cells. 15:1-15:7 - Yang Hsu, Min-Hsuan Chung, Yao-Wen Chang, Ci-Hong Lin:
Transitive Closure Graph-Based Warpage-Aware Floorplanning for Package Designs. 16:1-16:7
Democratizing Design Automation with Open-Source Tools: Perspectives, Opportunities, and Challenges
- Andrew B. Kahng:
A Mixed Open-Source and Proprietary EDA Commons for Education and Prototyping. 17:1-17:6 - Nicolas Bohm Agostini, Ankur Limaye, Marco Minutoli, Vito Giovanni Castellana, Joseph B. Manzano, Antonino Tumeo, Serena Curzel, Fabrizio Ferrandi:
SODA Synthesizer: An Open-Source, Multi-Level, Modular, Extensible Compiler from High-Level Frameworks to Silicon. 18:1-18:7 - Maico Cassel dos Santos, Tianyu Jia, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Luca P. Carloni, Pradip Bose:
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components. 20:1-20:9
Accelerators on A New Horizon
- Wei Cheng, Chun-Feng Wu, Yuan-Hao Chang, Ing-Chao Lin:
GraphRC: Accelerating Graph Processing on Dual-Addressing Memory with Vertex Merging. 21:1-21:9 - Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini:
Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. 22:1-22:9 - Edward Richter, Deming Chen:
Qilin: Enabling Performance Analysis and Optimization of Shared-Virtual Memory Systems with FPGA Accelerators. 23:1-23:9 - Ebadollah Taheri, Sudeep Pasricha, Mahdi Nikdast:
ReSiPI: A Reconfigurable Silicon-Photonic 2.5D Chiplet Network with PCMs for Energy-Efficient Interposer Communication. 24:1-24:9
CAD for Confidentiality of Hardware IPS
- Swarup Bhunia, Amitabh Das, Saverio Fazzari, Vivian Kammler, David Kehlet, Jeyavijayan Rajendran, Ankur Srivastava:
Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool. 25:1-25:8
Analyzing Reliability, Defects and Patterning
- Kyeonghyeon Baek, Hyunbum Park, Suwan Kim, Kyumyung Choi, Taewhan Kim:
Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net. 26:1-26:9 - Olympia Axelou, Nestor E. Evmorfopoulos, George Floros, George I. Stamoulis, Sachin S. Sapatnekar:
A Novel Semi-Analytical Approach for Fast Electromigration Stress Analysis in Multi-Segment Interconnects. 27:1-27:7 - Wentian Jin, Liang Chen, Subed Lamichhane, Mohammadamir Kavousi, Sheldon X.-D. Tan:
HierPINN-EM: Fast Learning-Based Electromigration Analysis for Multi-Segment Interconnects Using Hierarchical Physics-Informed Neural Network. 28:1-28:9 - Guan-Ting Liu, Wei-Chen Tai, Yi-Ting Lin, Iris Hui-Ru Jiang, James P. Shiely, Pu-Jen Cheng:
Sub-Resolution Assist Feature Generation with Reinforcement Learning and Transfer Learning. 29:1-29:9
New Frontier in Verification Technology
- I-Wei Chiu, Xin-Ping Chen, Jennifer Shueh-Inn Hu, James Chien-Mo Li:
Automatic Test Configuration and Pattern Generation (ATCPG) for Neuromorphic Chips. 30:1-30:7 - Sizhe Zhang, Mohsen Imani, Xun Jiao:
ScaleHD: Robust Brain-Inspired Hyperdimensional Computing via Adapative Scaling. 31:1-31:9 - Chanwook Oh, Michele Lora, Pierluigi Nuzzo:
Quantitative Verification and Design Space Exploration under Uncertainty with Parametric Stochastic Contracts. 32:1-32:9
Low Power Edge Intelligence
- Dina Hussein, Taha Belkhouja, Ganapati Bhat, Janardhan Rao Doppa:
Reliable Machine Learning for Wearable Activity Monitoring: Novel Algorithms and Theoretical Guarantees. 33:1-33:9 - Yang Ni, Nicholas A. Lesica, Fan-Gang Zeng, Mohsen Imani:
Neurally-Inspired Hyperdimensional Classification for Efficient and Robust Biosignal Processing. 34:1-34:9 - Sahidul Islam, Shanglin Zhou, Ran Ran, Yufang Jin, Wujie Wen, Caiwen Ding, Mimi Xie:
EVE: Environmental Adaptive Neural Network Models for Low-Power Energy Harvesting System. 35:1-35:9
Crossbars, Analog Accelerators for Neural Networks, and Neuromorphic Computing Based on Printed Electronics
- Pranav Sinha, Sunny Raj:
Designing Energy-Efficient Decision Tree Memristor Crossbar Circuits Using Binary Classification Graphs. 36:1-36:9 - Hanqing Zhu, Keren Zhu, Jiaqi Gu, Harrison Jin, Ray T. Chen, Jean Anne Incorvia, David Z. Pan:
Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration. 37:1-37:9 - Haibin Zhao, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori:
Aging-Aware Training for Printed Neuromorphic Circuits. 38:1-38:9
Designing DNN Accelerators
- Naebeom Park, Daehyun Ahn, Jae-Joon Kim:
Workload-Balanced Graph Attention Network Accelerator with Top-K Aggregation Candidates. 39:1-39:9 - Hyein Shin, Myeonggu Kang, Lee-Sup Kim:
Re2fresh: A Framework for Mitigating Read Disturbance in ReRAM-Based DNN Accelerators. 40:1-40:9 - Shehzeen Hussain, Nojan Sheybani, Paarth Neekhara, Xinqiao Zhang, Javier Mauricio Duarte, Farinaz Koushanfar:
FastStamp: Accelerating Neural Steganography and Digital Watermarking of Images on FPGAs. 41:1-41:9
Novel Chiplet Approaches from Interconnect to System (Virtual)
- Fuping Li, Ying Wang, Yuanqing Cheng, Yujie Wang, Yinhe Han, Huawei Li, Xiaowei Li:
GIA: A Reusable General Interposer Architecture for Agile Chiplet Integration. 42:1-42:9 - Chengeng Li, Fan Jiang, Shixi Chen, Jiaxu Zhang, Yinyi Liu, Yuxiang Fu, Jiang Xu:
Accelerating Cache Coherence in Manycore Processor through Silicon Photonic Chiplet. 43:1-43:9 - Qian Wei, Zhaoyan Shen, Yiheng Tong, Zhiping Jia, Lei Ju, Jiezhi Chen, Bingzhe Li:
Re-LSM: A ReRAM-Based Processing-in-Memory Framework for LSM-Based Key-Value Store. 44:1-44:9
Architecture for DNN Acceleration (Virtual)
- Yiming Chen, Guodong Yin, Mingyen Lee, Wenjun Tang, Zekun Yang, Yongpan Liu, Huazhong Yang, Xueqing Li:
Hidden-ROM: A Compute-in-ROM Architecture to Deploy Large-Scale Neural Networks on Chip with Flexible and Scalable Post-Fabrication Task Transfer Capability. 45:1-45:9 - Yikan Qiu, Yufei Ma, Wentao Zhao, Meng Wu, Le Ye, Ru Huang:
DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks. 46:1-46:9 - Jun Li, Wei Wang, Wu-Jun Li:
Hardware Computation Graph for DNN Accelerator Design Automation without Inter-PU Templates. 47:1-47:9
Multi-Purpose Fundamental Digital Design Improvements (Virtual)
- Nikolaos Zompakis, Sotirios Xydis:
Dynamic Frequency Boosting Beyond Critical Path Delay. 48:1-48:8 - Weihua Xiao, Weikang Qian:
ASPPLN: Accelerated Symbolic Probability Propagation in Logic Network. 49:1-49:9 - Longlong Yang, Cuiyang Ding, Changhao Yan, Dian Zhou, Xuan Zeng:
A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions. 50:1-50:9
GPU Acceleration for Routing Algorithms (Virtual)
- Shiju Lin, Martin D. F. Wong:
Superfast Full-Scale CPU-Accelerated Global Routing. 51:1-51:8 - Zhuolun He, Yuzhe Ma, Bei Yu:
X-Check: CPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms. 52:1-52:9 - Zizheng Guo, Feng Gu, Yibo Lin:
GPU-Accelerated Rectilinear Steiner Tree Generation. 53:1-53:9
Breakthroughs in Synthesis - Infrastructure and ML Assist I (Virtual)
- Ruifan Xu, Youwei Xiao, Jin Luo, Yun Liang:
HECTOR: A Multi-Level Intermediate Representation for Hardware Synthesis Methodologies. 54:1-54:9 - Mingyu Chen, Yu Zhang, Yongshang Li, Zhen Wang, Jun Li, Xiangyang Li:
QCIR: Pattern Matching Based Universal Quantum Circuit Rewriting Framework. 55:1-55:8 - Chang Feng, Wenlong Lyu, Zhitang Chen, Junjie Ye, Mingxuan Yuan, Jianye Hao:
Batch Sequential Black-Box Optimization with Embedding Alignment Cells for Logic Synthesis. 56:1-56:9 - Xinyi Zhou, Junjie Ye, Chak-Wa Pui, Kun Shao, Guangliang Zhang, Bin Wang, Jianye Hao, Guangyong Chen, Pheng-Ann Heng:
Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration. 57:1-57:9
Smart Search (Virtual)
- Huihong Shi, Haoran You, Yang Zhao, Zhongfeng Wang, Yingyan Lin:
NASA: Neural Architecture Search and Acceleration for Hardware Inspired Hybrid Networks. 58:1-58:9 - Zhao Yang, Qingshuang Sun:
Personalized Heterogeneity-Aware Federated Search Towards Better Accuracy and Energy Efficiency. 59:1-59:9
Reconfigurable Computing: Accelerators and Methodologies I (Virtual)
- Keqi Fu, Zhi Qi, Jiaxuan Cai, Xulong Shi:
Towards High Performance and Accurate BNN Inference on FPGA with Structured Fine-Grained Pruning. 60:1-60:9 - Yan Zhuang, Zhihao Zhang, Dajiang Liu:
Towards High-Quality CGRA Mapping with Graph Neural Networks and Reinforcement Learning. 61:1-61:9
Hardware Security: Attacks and Countermeasures (Virtual)
- Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang:
Attack Directories on ARM big.LITTLE Processors. 62:1-62:9 - Rajat Sadhukhan, Sayandeep Saha, Debdeep Mukhopadhyay:
AntiSIFA-CAD: A Framework to Thwart SIFA at the Layout Level. 63:1-63:9
Advanced VLSI Routing and Layout Learning
- Rongjian Liang, Hua Xiang, Jinwook Jung, Jiang Hu, Gi-Joon Nam:
A Stochastic Approach to Handle Non-Determinism in Deep Learning-Based Design Rule Violation Predictions. 64:1-64:8 - Yen-Ting Chen, Yao-Wen Chang:
Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular Structures. 65:1-65:6 - Keren Zhu, Hao Chen, Walker J. Turner, George F. Kokai, Po-Hsuan Wei, David Z. Pan, Haoxing Ren:
TAG: Learning Circuit Spatial Embedding from Layouts. 66:1-66:9
Physical Attacks and Countermeasures
- Huifeng Zhu, Zhiyuan Yu, Weidong Cao, Ning Zhang, Xuan Zhang:
PowerTouch: A Security Objective-Guided Automation Framework for Generating Wired Ghost Touch Attacks on Touchscreens. 67:1-67:9 - Michael Zuzak, Yuntao Liu, Isaac McDaniel, Ankur Srivastava:
A Combined Logical and Physical Attack on Logic Obfuscation. 68:1-68:9 - Alexander Hepp, Tiago D. Perez, Samuel Pagliarini, Georg Sigl:
A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. 69:1-69:9
Tutorial: Polynomial Formal Verification: Ensuring Correctness under Resource Constraints
- Rolf Drechsler, Alireza Mahzoon:
Polynomial Formal Verification: Ensuring Correctness under Resource Constraints. 70:1-70:9
Scalable Verification Technologies
- Mate Soos, Kuldeep S. Meel:
Arjun: An Efficient Independent Support Computation Technique and its Applications to Counting and Sampling. 71:1-71:9 - Yue Xing, Huaixi Lu, Aarti Gupta, Sharad Malik:
Compositional Verification Using a Formal Component and Interface Specification. 72:1-72:9 - Qinhan Tan, Aarti Gupta, Sharad Malik:
Usage-Based RTL Subsetting for Hardware Accelerators. 73:1-73:9
Optimizing Digital Design Aspects: From Gate Sizing to Multi-Bit Flip-Flops
- Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren:
TransSizer: A Novel Transformer-Based Fast Gate Sizer. 74:1-74:9 - Meng-Yun Liu, Yu-Cheng Lai, Wai-Kei Mak, Ting-Chi Wang:
Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization. 75:1-75:9 - Zhiyao Xie, Shiyu Li, Mingyuan Ma, Chen-Chia Chang, Jingyu Pan, Yiran Chen, Jiang Hu:
DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters. 76:1-76:9
Energy Efficient Hardware Acceleration and Stochastic Computing
- Ranyang Zhou, Arman Roohi, Durga Misra, Shaahin Angizi:
ReD-LUT: Reconfigurable In-DRAM LUTs Enabling Massive Parallel Computation. 77:1-77:8 - Pranathi Vasireddy, Krishna Kavi, Gayatri Mehta:
Sparse-T: Hardware Accelerator Thread for Unstructured Sparse Data Processing. 78:1-78:8 - Peter Schober, Seyedeh Newsha Estiri, Sercan Aygun, Nima TaheriNejad, M. Hassan Najafi:
Sound Source Localization Using Stochastic Computing. 79:1-79:9
Special Session: Approximate Computing and the Efficient Machine Learning Expedition
- Jörg Henkel, Hai Li, Anand Raghunathan, Mehdi B. Tahoori, Swagath Venkataramani, Xiaoxuan Yang, Georgios Zervakis:
Approximate Computing and the Efficient Machine Learning Expedition. 80:1-80:9
Co-Search Methods and Tools
- Tong Zhou, Shaolei Ren, Xiaolin Xu:
ObfuNAS: A Neural Architecture Search-Based DNN Obfuscation Approach. 81:1-81:9 - Rongjian Liang, Jianfeng Song, Bo Yuan, Jiang Hu:
Deep Learning Toolkit-Accelerated Analytical Co-Optimization of CNN Hardware and Dataflow. 82:1-82:9 - William Andrew Simon, Una Pale, Tomás Teijeiro, David Atienza:
HDTorch: Accelerating Hyperdimensional Computing with GP-GPUs for Design Space Exploration. 83:1-83:8
Reconfigurable Computing: Accelerators and Methodologies II
- Hanning Chen, Mariam Issa, Yang Ni, Mohsen Imani:
DARL: Distributed Reconfigurable Accelerator for Hyperdimensional Reinforcement Learning. 84:1-84:9 - Carl-Johannes Johnsen, Tiziano De Matteis, Tal Ben-Nun, Johannes de Fine Licht, Torsten Hoefler:
Temporal Vectorization: A Compiler Approach to Automatic Multi-Pumping. 85:1-85:9
Compute-in-Memory for Neural Networks
- Yun-Chen Lo, Chih-Chen Yeh, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Wen-Chien Ting, Ren-Shuo Liu:
ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators. 86:1-86:9 - Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi:
Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous? 87:1-87:9
Breakthroughs in Synthesis - Infrastructure and ML Assist II
- Wan-Hsuan Lin, Chia-Hsuan Su, Jie-Hong R. Jiang:
Language Equation Solving via Boolean Automata Manipulation. 88:1-88:9 - Prianka Sengupta, Aakash Tyagi, Yiran Chen, Jiang Hu:
How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning. 89:1-89:9
In-Memory Computing Revisited
- Muhammad Rashedul Haq Rashed, Sumit Kumar Jha, Rickard Ewetz:
Logic Synthesis for Digital In-Memory Computing. 90:1-90:9 - Kang He, Indranil Chakraborty, Cheng Wang, Kaushik Roy:
Design Space and Memory Technology Co-Exploration for In-Memory Computing Based Machine Learning Accelerators. 91:1-91:9
Special Session: 2022 CAD Contest at ICCAD
- Yu-Guang Chen, Chun-Yao Wang, Tsung-Wei Huang, Takashi Sato:
Overview of 2022 CAD Contest at ICCAD. 92:1-92:3 - Chung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu:
2022 CAD Contest Problem A: Learning Arithmetic Operations from Gate-Level Circuit. 93:1-93:4 - Kai-Shun Hu, I-Jye Lin, Yu-Hui Huang, Hao-Yu Chi, Yi-Hsuan Wu, Cindy Chin-Fang Shen:
2022 ICCAD CAD Contest Problem B: 3D Placement with D2D Vertical Connections. 94:1-94:5 - Sicheng Li, Chen Bai, Xuechao Wei, Bizhao Shi, Yen-Kuang Chen, Yuan Xie:
2022 ICCAD CAD Contest Problem C: Microarchitecture Design Space Exploration. 95:1-95:7 - Jinwook Jung, Andrew B. Kahng, Ravi Varadarajan, Zhiang Wang:
IEEE CEDA DATC: Expanding Research Foundations for IC Physical Design and ML-Enabled EDA. 96:1-96:8
Architectures and Methodologies for Advanced Hardware Security
- Jingyao Zhang, Elaheh Sadredini:
Inhale: Enabling High-Performance and Energy-Efficient In-SRAM Cryptographic Hash for IoT. 97:1-97:9 - Kevin Nam, Hyunyoung Oh, Hyungon Moon, Yunheung Paek:
Accelerating N-Bit Operations over TFHE on Commodity CPU-FPGA. 98:1-98:9 - Oleg Mazonka, Eduardo Chielle, Deepraj Soni, Michail Maniatakos:
Fast and Compact Interleaved Modular Multiplication Based on Carry Save Addition. 99:1-99:9 - Eduardo Chielle, Oleg Mazonka, Homer Gamil, Michail Maniatakos:
Accelerating Fully Homomorphic Encryption by Bridging Modular and Bit-Level Arithmetic. 100:1-100:9
Special Session: The Dawn of Domain-Specific Hardware Accelerators for Robotic Computing
- Yanqi Liu, Anthony Opipari, Odest Chadwicke Jenkins, R. Iris Bahar:
A Reconfigurable Hardware Library for Robot Scene Perception. 101:1-101:9 - Zishen Wan, Karthik Swaminathan, Pin-Yu Chen, Nandhini Chandramoorthy, Arijit Raychowdhury:
Analyzing and Improving Resilience and Robustness of Autonomous Systems. 102:1-102:9 - Yuhui Hao, Bo Yu, Qiang Liu, Shaoshan Liu, Yuhao Zhu:
Factor Graph Accelerator for LiDAR-Inertial Odometry (Invited Paper). 103:1-103:7 - Lingyi Huang, Xiao Zang, Yu Gong, Bo Yuan:
Hardware Architecture of Graph Neural Network-Enabled Motion Planner (Invited Paper). 104:1-104:7
From Logical to Physical Qubits: New Models and Techniques for Mapping
- Tsou-An Wu, Yun-Jhe Jiang, Shao-Yun Fang:
A Robust Quantum Layout Synthesis Algorithm with a Qubit Mapping Checker. 105:1-105:9 - Ching-Yao Huang, Chi-Hsiang Lien, Wai-Kei Mak:
Reinforcement Learning and DEAR Framework for Solving the Qubit Mapping Problem. 106:1-106:9 - Bochen Tan, Dolev Bluvstein, Mikhail D. Lukin, Jason Cong:
Qubit Mapping for Reconfigurable Atom Arrays. 107:1-107:9 - Sunghye Park, Dohun Kim, Jae-Yoon Sim, Seokhyeong Kang:
MCQA: Multi-Constraint Qubit Allocation for Near-FTQC Device. 108:1-108:9
Smart Embedded Systems (Virtual)
- Hao Kong, Di Liu, Shuo Huai, Xiangzhong Luo, Weichen Liu, Ravi Subramaniam, Christian Makaya, Qian Lin:
Smart Scissor: Coupling Spatial Redundancy Reduction and CNN Compression for Embedded Hardware. 109:1-109:9 - Yuankai Xu, Tiancheng He, Ruiqi Sun, Yehan Ma, Yier Jin, An Zou:
SHAPE: Scheduling of Fixed-Priority Tasks on Heterogeneous Architectures with Multiple CPUs and Many PEs. 110:1-110:9 - Yu-Cheng Lin, Yu-Pei Liang, Tseng-Yi Chen, Yuan-Hao Chang, Shuo-Han Chen, Wei-Kuan Shih:
On Minimizing the Read Latency of Flash Memory to Preserve Inter-Tree Locality in Random Forest. 111:1-111:9
Analog/Mixed-Signal Simulation, Layout, and Packaging (Virtual)
- Xiaoming Chen:
Numerically-Stable and Highly-Scalable Parallel LU Factorization for Circuit Simulation. 112:1-112:9 - Cong Wang, Dongen Yang, Quan Chen:
EI-MOR: A Hybrid Exponential Integrator and Model Order Reduction Approach for Transient Power/Ground Network Analysis. 113:1-113:8 - Zhen Zhuang, Bei Yu, Kai-Yuan Chao, Tsung-Yi Ho:
Multi-Package Co-Design for Chiplet Integration. 114:1-114:9
Advanced PIM and Biochip Technology and Stochastic Computing (Virtual)
- Xing Li, Rachata Ausavarungnirun, Xiao Liu, Xueyuan Liu, Xuan Zhang, Heng Lu, Zhuoran Song, Naifeng Jing, Xiaoyao Liang:
Gzippo: Highly-Compact Processing-in-Memory Graph Accelerator Alleviating Sparsity and Redundancy. 115:1-115:9 - Siyuan Liang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho:
CoMUX: Combinatorial-Coding-Based High-Performance Microfluidic Control Multiplexer Design. 116:1-116:9 - Kuncai Zhong, Zexi Li, Haoran Jin, Weikang Qian:
Exploiting Uniform Spatial Distribution to Design Efficient Random Number Source for Stochastic Computing. 117:1-117:9
On Automating Heterogeneous Designs (Virtual)
- Jai-Ming Lin, Po-Chen Lu, Heng-Yu Lin, Jia-Ting Tsai:
A Novel Blockage-Avoiding Macro Placement Approach for 3D ICs Based on POCS. 118:1-118:7 - Jai-Ming Lin, Hao-Yuan Hsieh, Hsuan Kung, Hao-Jia Lin:
Routability-Driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs. 119:1-119:8
Special Session: Quantum Computing to Solve Chemistry, Physics and Security Problems (Virtual)
- Collin Beaudoin, Satwik Kundu, Rasit Onur Topaloglu, Swaroop Ghosh:
Quantum Machine Learning for Material Synthesis and Hardware Security (Invited Paper). 120:1-120:7 - Andrea Delgado, Kathleen E. Hamilton:
Quantum Machine Learning Applications in High-Energy Physics. 120:1-120:5
Making Patterning Work (Virtual)
- Qipan Wang, Xiaohan Gao, Yibo Lin, Runsheng Wang, Ru Huang:
DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography. 122:1-122:9 - Wenqian Zhao, Xufeng Yao, Ziyang Yu, Guojin Chen, Yuzhe Ma, Bei Yu, Martin D. F. Wong:
AdaOPC: A Self-Adaptive Mask Optimization Framework for Real Design Patterns. 123:1-123:9 - Liangjian Wen, Yi Zhu, Lei Ye, Guojin Chen, Bei Yu, Jianzhuang Liu, Chunjing Xu:
LayouTransformer: Generating Layout Patterns with Transformer via Sequential Pattern Modeling. 124:1-124:9 - Qijing Wang, Martin D. F. Wong:
WaferHSL: Wafer Failure Pattern Classification with Efficient Human-Like Staged Learning. 125:1-125:8
Advanced Verification Technologies (Virtual)
- Xiaoyu Zhang, Shengping Xiao, Jianwen Li, Geguang Pu, Ofer Strichman:
Combining BMC and Complementary Approximate Reachability to Accelerate Bug-Finding. 126:1-126:9 - Xin Hong, Yuan Feng, Sanjiang Li, Mingsheng Ying:
Equivalence Checking of Dynamic Quantum Circuits. 127:1-127:8
Routing with Cell Movement (Virtual)
- Xinshi Zang, Fangzhou Wang, Jinwei Liu, Martin D. F. Wong:
ATLAS: A Two-Level Layer-Aware Scheme for Routing with Cell Movement. 128:1-128:7 - Ziran Zhu, Fuheng Shen, Yangjie Mei, Zhipeng Huang, Jianli Chen, Jun Yang:
A Robust Global Routing Engine with High-Accuracy Cell Movement under Advanced Constraints. 129:1-129:9
Special Session: Hardware Security through Reconfigurability: Attacks, Defenses, and Challenges
- Nima Kavand, Armin Darjani, Shubham Rai, Akash Kumar:
Securing Hardware through Reconfigurable Nano-Structures. 130:1-130:7 - Luca Collini, Benjamin Tan, Christian Pilato, Ramesh Karri:
Reconfigurable Logic for Hardware IP Protection: Opportunities and Challenges. 131:1-131:7
Performance, Power and Temperature Aspects in Deep Learning
- Chaojian Li, Sixu Li, Yang Zhao, Wenbo Zhu, Yingyan Lin:
RT-NeRF: Real-Time On-Device Neural Radiance Fields Towards Immersive AR/VR Rendering. 132:1-132:9 - Yifan Gong, Zheng Zhan, Pu Zhao, Yushu Wu, Chao Wu, Caiwen Ding, Weiwen Jiang, Minghai Qin, Yanzhi Wang:
All-in-One: A Highly Representative DNN Pruning Framework for Edge Devices with Dynamic Power Management. 133:1-133:9 - Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Jiang Hu, Yiran Chen:
Robustify ML-Based Lithography Hotspot Detectors. 134:1-134:7 - Mengyuan Li, Arman Kazemi, Ann Franchesca Laguna, X. Sharon Hu:
Associative Memory Based Experience Replay for Deep Reinforcement Learning. 135:1-135:9
Tutorial: TorchQuantum Case Study for Robust Quantum Circuits
- Hanrui Wang, Zhiding Liang, Jiaqi Gu, Zirui Li, Yongshan Ding, Weiwen Jiang, Yiyu Shi, David Z. Pan, Frederic T. Chong, Song Han:
TorchQuantum Case Study for Robust Quantum Circuits. 136:1-136:9
Emerging Machine Learning Primitives: From Technology to Application
- Che-Kai Liu, Haobang Chen, Mohsen Imani, Kai Ni, Arman Kazemi, Ann Franchesca Laguna, Michael T. Niemier, Xiaobo Sharon Hu, Liang Zhao, Cheng Zhuo, Xunzhao Yin:
COSIME: FeFET Based Associative Memory for In-Memory Cosine Similarity Search. 137:1-137:9 - Thai-Hoang Nguyen, Muhammad Imran, Joon-Sung Yang:
DynaPAT: A Dynamic Pattern-Aware Encoding Technique for Robust MLC PCM-Based Deep Neural Networks. 138:1-138:9 - Vedika Servanan, Samah Mohamed Saeed:
Graph Neural Networks for Idling Error Mitigation. 139:1-139:9 - Zhirui Hu, Peiyan Dong, Zhepeng Wang, Youzuo Lin, Yanzhi Wang, Weiwen Jiang:
Quantum Neural Network Compression. 140:1-140:9
Design for Low Energy, Low Resource, but High Quality
- Azat Azamat, Jaewoo Park, Jongeun Lee:
Squeezing Accumulators in Binary Neural Networks for Extremely Resource-Constrained Applications. 141:1-141:7 - Yunxiang Zhang, Biao Sun, Weixiong Jiang, Yajun Ha, Miao Hu, Wenfeng Zhao:
WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization. 142:1-142:9 - Kyeongho Lee, Joonhyung Kim, Jongsun Park:
Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital Conversion. 143:1-143:8
Microarchitectural Attacks and Countermeasures
- Hasini Witharana, Prabhat Mishra:
Speculative Load Forwarding Attack on Modern Processors. 144:1-144:9 - Arash Pashrashid, Ali Hajiabadi, Trevor E. Carlson:
Fast, Robust and Accurate Detection of Cache-Based Spectre Attack Phases. 145:1-145:9 - Ivan De Oliveira Nunes, Sashidhar Jakkamsetti, Youngil Kim, Gene Tsudik:
CASU: Compromise Avoidance via Secure Update for Low-End Embedded Systems. 146:1-146:9
Genetic Circuits Meet Ising Machines
- Tobias Schwarz, Christian Hochberger:
Technology Mapping of Genetic Circuits: From Optimal to Fast Solutions. 147:1-147:8 - Naomi Sagan, Jaijeet Roychowdhury:
DaS: Implementing Dense Ising Machines Using Sparse Resistive Networks. 148:1-148:9 - Yiqiao Zhang, Uday Kumar Reddy Vengalam, Anshujit Sharma, Michael C. Huang, Zeljko Ignjatovic:
QuBRIM: A CMOS Compatible Resistively-Coupled Ising Machine with Quantized Nodal Interactions. 149:1-149:8
Energy Efficient Neural Networks via Approximate Computations
- Elias Trommer, Bernd Waschneck, Akash Kumar:
Combining Gradients and Probabilities for Heterogeneous Approximation of Neural Networks. 150:1-150:8 - Ayushi Dube, Ankit Wagle, Gian Singh, Sarma B. K. Vrudhula:
Tunable Precision Control for Approximate Image Filtering in an In-Memory Architecture with Embedded Neurons. 151:1-151:9 - Tim Bücher, Lilas Alrahis, Guilherme Paim, Sergio Bampi, Ozgur Sinanoglu, Hussam Amrouch:
AppGNN: Approximation-Aware Functional Reverse Engineering Using Graph Neural Networks. 152:1-152:9 - Aradhana Mohan Parvathy, Sarada Krithivasan, Sanchari Sen, Anand Raghunathan:
Seprox: Sequence-Based Approximations for Compressing Ultra-Low Precision Deep Neural Networks. 153:1-153:9
Algorithms and Tools for Security Analysis and Secure Hardware Design
- Amin Rezaei, Raheel Afsharmazayejani, Jordan Maynard:
Evaluating the Security of eFPGA-Based Redaction Algorithms. 154:1-154:7 - Pei-Pei Chen, Xiang-Min Yang, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
An Approach to Unlocking Cyclic Logic Locking: LOOPLock 2.0. 155:1-155:7 - Mohammad Hashemi, Steffi Roy, Fatemeh Ganji, Domenic Forte:
Garbled EDA: Privacy Preserving Electronic Design Automation. 156:1-156:9 - Baleegh Ahmad, Wei-Kai Liu, Luca Collini, Hammond Pearce, Jason M. Fung, Jonathan Valamehr, Mohammad Bidmeshki, Piotr Sapiecha, Steve Brown, Krishnendu Chakrabarty, Ramesh Karri, Benjamin Tan:
Don't CWEAT It: Toward CWE Analysis Techniques in Early Stages of Hardware Design. 157:1-157:9
Special Session: Making ML Reliable: From Devices to Systems to Software
- Meng-Fan Chang, Je-Ming Hung, Ping-Cheng Chen, Tai-Hao Wen:
Reliable Computing of ReRAM Based Compute-in-Memory Circuits for AI Edge Devices. 158:1-158:6 - Biresh Kumar Joardar, Aqeeb Iqbal Arka, Janardhan Rao Doppa, Partha Pratim Pande:
Fault-Tolerant Deep Learning Using Regularization. 159:1-159:6 - Arjun Chaudhuri, Jonti Talukdar, Krishnendu Chakrabarty:
Machine Learning for Testing Machine-Learning Hardware: A Virtuous Cycle. 160:1-160:6 - Bonita Bhaskaran, Sanmitra Banerjee, Kaushik Narayanun, Shao-Chun Hung, Seyed Nima Mozaffari Mojaveri, Mengyun Liu, Gang Chen, Tung-Che Liang:
Observation Point Insertion Using Deep Learning. 161:1-161:8
Autonomous Systems and Machine Learning on Embedded Systems
- Luke Chen, Mohanad Odema, Mohammad Abdullah Al Faruque:
Romanus: Robust Task Offloading in Modular Multi-Sensor Autonomous Driving Systems. 162:1-162:8 - Soham Sinha, Anam Farrukh, Richard West:
ModelMap: A Model-Based Multi-Domain Application Framework for Centralized Automotive Systems. 163:1-163:9 - Anish Krishnakumar, Radu Marculescu, Ümit Y. Ogras:
INDENT: Incremental Online Decision Tree Training for Domain-Specific Systems-on-Chip. 164:1-164:9 - Cheng-Yuan Wang, Yao-Wen Chang, Yuan-Hao Chang:
SGIRR: Sparse Graph Index Remapping for ReRAM Crossbar Operation Unit and Power Optimization. 165:1-165:7
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-06-10 21:39 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
