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Sharad Sinha
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2020 – today
- 2024
- [j25]Akanksha Mishra, Sharad Sinha, Clint Pazhayidam George:
Shielding against online harm: A survey on text analysis to prevent cyberbullying. Eng. Appl. Artif. Intell. 133: 108241 (2024) - [j24]Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang:
AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2769-2782 (2024) - [j23]Pavitra Prakash Bhade, Joseph Paturel, Olivier Sentieys, Sharad Sinha:
Lightweight Hardware-Based Cache Side-Channel Attack Detection for Edge Devices (Edge-CaSCADe). ACM Trans. Embed. Comput. Syst. 23(4): 56:1-56:27 (2024) - [j22]Prachi Kashikar, Olivier Sentieys, Sharad Sinha:
Combining Weight Approximation, Sharing and Retraining for Neural Network Model Compression. ACM Trans. Embed. Comput. Syst. 23(6): 99:1-99:23 (2024) - [j21]Linfeng Du, Tingyuan Liang, Xiaofeng Zhou, Jinming Ge, Shangkun Li, Sharad Sinha, Jieru Zhao, Zhiyao Xie, Wei Zhang:
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs. ACM Trans. Reconfigurable Technol. Syst. 17(3): 47:1-47:33 (2024) - [j20]Enlai Li, Sharad Sinha, Wei Zhang:
Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1549-1553 (2024) - [c43]Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang:
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. FPGA 2024: 143-153 - [c42]Shubhayu Das, Nanditha P. Rao, Sharad Sinha:
ConvMap: Boosting Convolution Throughput on FPGAs with Efficient Resource Mapping. IPDPS (Workshops) 2024: 189 - 2023
- [j19]Sathi Sarveswara Reddy, Sharad Sinha, Wei Zhang:
Design and Analysis of RSA and Paillier Homomorphic Cryptosystems Using PSO-Based Evolutionary Computation. IEEE Trans. Computers 72(7): 1886-1900 (2023) - [j18]Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang:
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3925-3938 (2023) - [j17]Prachi Kashikar, Olivier Sentieys, Sharad Sinha:
Lossless Neural Network Model Compression Through Exponent Sharing. IEEE Trans. Very Large Scale Integr. Syst. 31(11): 1816-1825 (2023) - [c41]Vipin Gautam, Shitala Prasad, Sharad Sinha:
YOLORe-IDNet: An Efficient Multi-camera System for Person-Tracking. CVIP (1) 2023: 185-197 - [c40]Vipin Gautam, Shitala Prasad, Sharad Sinha:
Joint-YODNet: A Light-Weight Object Detector for UAVs to Achieve Above 100fps. CVIP (2) 2023: 567-578 - [c39]Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang:
Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs. DATE 2023: 1-6 - [c38]Yuying Zhang, Sathi Sarveswara Reddy, Zili Kou, Sharad Sinha, Wei Zhang:
Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform. FCCM 2023: 174-183 - [c37]Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang:
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. FPGA 2023: 15-25 - [c36]Liangji Chen, Tingyuan Liang, Wei Zhang, Sharad Sinha:
DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis. ICFPT 2023: 300-301 - [c35]Sheikh K. Ghafoor, Sushil K. Prasad, Ashish Kuvelkar, Sharad Sinha, Satish Puri:
Message from Workshop Chairs. HiPCW 2023: 1-3 - [i13]Vipin Gautam, Shitala Prasad, Sharad Sinha:
YOLORe-IDNet: An Efficient Multi-Camera System for Person-Tracking. CoRR abs/2309.13387 (2023) - [i12]Vipin Gautam, Shitala Prasad, Sharad Sinha:
AaP-ReID: Improved Attention-Aware Person Re-identification. CoRR abs/2309.15780 (2023) - [i11]Vipin Gautam, Shitala Prasad, Sharad Sinha:
Joint-YODNet: A Light-weight Object Detector for UAVs to Achieve Above 100fps. CoRR abs/2309.15782 (2023) - 2022
- [j16]Sharad Sinha:
Workings of science: Is engineering applied science? Ubiquity 2022(May): 1-6 (2022) - [c34]Aditi Saxena, Sharad Sinha:
Machine Learning Based Webcasting Analytics for Indian Elections - Reflections on Deployment. CVIP (2) 2022: 47-57 - [c33]Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang:
Attack Directories on ARM big.LITTLE Processors. ICCAD 2022: 62:1-62:9 - [i10]Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang:
AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA. CoRR abs/2210.08682 (2022) - [i9]Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang:
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. CoRR abs/2212.11582 (2022) - 2021
- [j15]Arish Sateesan, Sharad Sinha, Smitha K. G., A. P. Vinod:
A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs. Neural Process. Lett. 53(3): 2331-2377 (2021) - [j14]Zhe Lin, Sharad Sinha, Wei Zhang:
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2279-2292 (2021) - [c32]Prachi Kashikar, Sharad Sinha, Ajeet Kumar Verma:
Exploiting Weight Statistics for Compressed Neural Network Implementation on Hardware. AICAS 2021: 1-4 - [c31]Zili Kou, Wenjian He, Sharad Sinha, Wei Zhang:
Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict. DAC 2021: 979-984 - [c30]Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang:
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. ICCAD 2021: 1-9 - [c29]Prachi Kashikar, Sharad Sinha:
Compressing CNNs by Exponent Sharing in Weights using IEEE Single Precision Format. ISQED 2021: 317 - [c28]Risikesh RK, Sharad Sinha, Nanditha P. Rao:
Variable Bit-Precision Vector Extension for RISC-V Based Processors. MCSoC 2021: 114-121 - [c27]Pavitra Prakash Bhade, Sharad Sinha:
Detection of Cache Side Channel Attacks Using Thread Level Monitoring of Hardware Performance Counters. MCSoC 2021: 210-217 - 2020
- [j13]Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He:
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1428-1441 (2020) - [j12]Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha:
Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling. ACM Trans. Reconfigurable Technol. Syst. 13(3): 13:1-13:28 (2020) - [c26]Wenjian He, Wei Zhang, Sharad Sinha, Sanjeev Das:
iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU. ASP-DAC 2020: 56-61 - [c25]Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang:
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. ASP-DAC 2020: 574-580 - [c24]Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen:
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. FPL 2020: 269-276 - [c23]Arish Sateesan, Sharad Sinha, Smitha K. G.:
DASH: Design Automation for Synthesis and Hardware Generation for CNN. FPT 2020: 72-75 - [i8]Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen:
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. CoRR abs/2006.03250 (2020) - [i7]Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang:
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. CoRR abs/2009.00871 (2020) - [i6]Zhe Lin, Sharad Sinha, Wei Zhang:
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA. CoRR abs/2009.01431 (2020) - [i5]Zhe Lin, Sharad Sinha, Wei Zhang:
An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power. CoRR abs/2009.01432 (2020) - [i4]Zhe Lin, Wei Zhang, Sharad Sinha:
Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA. CoRR abs/2009.01434 (2020) - [i3]Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang:
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. CoRR abs/2009.01441 (2020) - [i2]Zhe Lin, Sharad Sinha, Wei Zhang:
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System. CoRR abs/2012.06272 (2020)
2010 – 2019
- 2019
- [j11]Sharad Sinha, Clint P. George:
Artificial intelligence for all using R programming language. AI Matters 5(4): 10-13 (2019) - [j10]Zhe Lin, Sharad Sinha, Wei Zhang:
An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1661-1674 (2019) - [c22]Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang:
LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms. DAC 2019: 1 - [c21]Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang:
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. DATE 2019: 1130-1135 - [c20]Zhe Lin, Sharad Sinha, Wei Zhang:
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA. FCCM 2019: 172-180 - [c19]Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang:
A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms. FPGA 2019: 188 - [c18]Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang:
Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis. ICCAD 2019: 1-6 - [c17]Lim Boon Leng, Smitha K. G., Sharad Sinha:
Smart Nation: Indoor Navigation for the Visually Impaired. ICITE 2019: 147-151 - [c16]Ang Poh Keong, K. G. Smitha, Sharad Sinha:
Smart Nation: Offline Public Transport Made Easy. ICITE 2019: 175-179 - [c15]Arish S, Sharad Sinha, Smitha K. G.:
Optimization of Convolutional Neural Networks on Resource Constrained Devices. ISVLSI 2019: 19-24 - [i1]Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang:
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. CoRR abs/1905.03852 (2019) - 2018
- [j9]Hao Liang, Sharad Sinha, Wei Zhang:
Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 350-363 (2018) - [j8]Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang:
Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2555-2566 (2018) - [j7]Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang:
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. IEEE Trans. Multi Scale Comput. Syst. 4(2): 152-162 (2018) - [c14]Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang:
CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms. FCCM 2018: 165-172 - [c13]Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha:
A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization. FPL 2018: 139-146 - 2017
- [j6]Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang:
HeteroSim: A Heterogeneous CPU-FPGA Simulator. IEEE Comput. Archit. Lett. 16(1): 38-41 (2017) - [c12]Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang:
PAAS: A system level simulator for heterogeneous computing architectures. FPL 2017: 1-8 - [c11]Zhe Lin, Wei Zhang, Sharad Sinha:
Decision tree based hardware power monitoring for run time dynamic power management in FPGA. FPL 2017: 1-8 - [c10]Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He:
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. ICCAD 2017: 430-437 - [c9]Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang:
A hybrid approach to cache management in heterogeneous CPU-FPGA platforms. ICCAD 2017: 937-944 - 2016
- [j5]Sharad Sinha, Wei Zhang:
Low-Power FPGA Design Using Memoization-Based Approximate Computing. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2665-2678 (2016) - [c8]Mohammad Tahghighi, Sharad Sinha, Wei Zhang:
Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA. ARC 2016: 159-170 - [c7]Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang:
HeteroSim: A heterogeneous CPU-FPGA simulator. FPL 2016: 1 - [c6]Mohammad Tahghighi, Wei Zhang, Sharad Sinha:
Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing. ISVLSI 2016: 667-672 - 2015
- [c5]Hao Liang, Sharad Sinha, Rakesh Warrier, Wei Zhang:
Static hardware task placement on multi-context FPGA using hybrid genetic algorithm. FPL 2015: 1-8 - [c4]Hao Liang, Wei Zhang, Sharad Sinha, Yi-Chung Chen, Hai Li:
Hierarchical library based power estimator for versatile FPGAs. FPL 2015: 1 - 2014
- [b1]Sharad Sinha:
Intelligent high level synthesis for customization on reconfigurable platforms. Nanyang Technological University, Singapore, 2014 - [j4]Sharad Sinha, Thambipillai Srikanthan:
IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance. Int. J. Reconfigurable Comput. 2014: 418750:1-418750:17 (2014) - [j3]Sharad Sinha, Thambipillai Srikanthan:
Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis. Int. J. Reconfigurable Comput. 2014: 564924:1-564924:14 (2014) - [j2]Sharad Sinha, Udit Dhawan, Thambipillai Srikanthan:
Extended Compatibility Path Based Hardware binding: an Adaptive Algorithm for High Level synthesis of Area-Time Efficient Designs. J. Circuits Syst. Comput. 23(9) (2014) - [j1]Sharad Sinha, Thambipillai Srikanthan:
Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective. ACM Trans. Design Autom. Electr. Syst. 20(1): 5:1-5:18 (2014) - [c3]Dipanjan Bhowmik, Avijit Datta, Sharad Sinha:
A Bit-Level Block Cipher Diffusion Analysis Test - BLDAT. FICTA (1) 2014: 667-674 - 2012
- [c2]Sharad Sinha, Thambipillai Srikanthan:
Dataflow graph partitioning for high level synthesis. FPL 2012: 503-506 - 2011
- [c1]Sharad Sinha, Udit Dhawan, Siew Kei Lam, Thambipillai Srikanthan:
A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis. ISVLSI 2011: 278-283
Coauthor Index
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last updated on 2024-11-07 21:35 CET by the dblp team
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