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ORCIDNanditha P. Rao
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2020 – today
- 2024
[c10]Shubhayu Das, Nanditha P. Rao, Sharad Sinha:
ConvMap: Boosting Convolution Throughput on FPGAs with Efficient Resource Mapping. IPDPS (Workshops) 2024: 189- 2023
- [c9]Shivani Shah
, Nanditha P. Rao:
MCSim: A Multi-Core Cache Simulator Accelerated on a Resource-constrained FPGA. ACM Great Lakes Symposium on VLSI 2023: 155-158 - 2022
- [c8]Veerendra S. Devaraddi, Nanditha P. Rao:
An FPGA based Tiled Systolic Array Generator to Accelerate CNNs. DSD 2022: 316-323 - [c7]Alok Parmar, Kailash Prasad, Nanditha P. Rao, Joycee Mekie:
An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory Computing for DNNs. ISCAS 2022: 2948-2952 - [c6]Alok Parmar, Kailash Prasad, Nanditha P. Rao, Joycee Mekie:
FastMem: A Fast Architecture-aware Memory Layout Design. ISQED 2022: 120-126 - [d1]Shivani Shah, Nanditha P. Rao:
Cacheaccel_Simulator. IEEE DataPort, 2022
- 2021
- [c5]Shivani Shah, Vaibhavi Mathur, Sahithi Meenakshi Vutakuru, Kavya Borra, Nanditha P. Rao:
Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher. DSD 2021: 97-100 - [c4]Shivani Shah, Sahithi Meenakshi Vutakuru, Nanditha P. Rao:
FPGA Accelerated Parameterized Cache Simulator. ISQED 2021: 310 - [c3]Prashant Mata, Nanditha P. Rao:
Flush-Reload Attack and its Mitigation on an FPGA Based Compressed Cache Design. ISQED 2021: 535-541 - [c2]Risikesh RK, Sharad Sinha, Nanditha P. Rao:
Variable Bit-Precision Vector Extension for RISC-V Based Processors. MCSoC 2021: 114-121
2010 – 2019
- 2018
- [j1]Nanditha P. Rao, Madhav P. Desai:
Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology. Microelectron. J. 72: 86-99 (2018) - 2017
- [i3]Nanditha P. Rao, Madhav P. Desai:
Neutron-induced strike: Study of multiple node charge collection in 14nm FinFETs. CoRR abs/1706.03315 (2017) - 2016
- [i2]Nanditha P. Rao, Madhav P. Desai:
Higher likelihood of multiple bit-flips due to neutron-induced strikes on logic gates. CoRR abs/1612.08239 (2016) - 2015
- [c1]Nanditha P. Rao, Madhav P. Desai:
A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients. DSD 2015: 714-721 - 2014
- [i1]Nanditha P. Rao, Shahbaz Sarik, Madhav P. Desai:
On the likelihood of multiple bit upsets in logic circuits. CoRR abs/1401.1003 (2014)
Coauthor Index
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