"Cache-accel: FPGA Accelerated Cache Simulator with Partially ..."

Shivani Shah et al. (2021)

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DOI: 10.1109/DSD53832.2021.00024

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-15

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Shivani Shah, Vaibhavi Mathur, Sahithi Meenakshi Vutakuru, Kavya Borra, Nanditha P. Rao:
Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher. DSD 2021: 97-100

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