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ORCIDIEEE Transactions on Very Large Scale Integration Systems, Volume 32
Volume 32, Number 1, January 2024
- Jari Nurmi
, Snorre Aunet, Alireza Saberkari:
Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2022. 1-3 - Agnimesh Ghosh, Andrei Spelman, Tze Hin Cheung, Dhanashree Boopathy, Kari Stadius, Manil Dev Gomony, Mikko Valkama, Jussi Ryynänen, Marko Kosunen, Vishnu Unnikrishnan:
Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters. 4-15 - Lars Nolte, Tim Twardzik, Camille Jalier, Zhigang Huang, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf:
HW-FUTEX: Hardware-Assisted Futex Syscall. 16-29 - Christian Lanius, Tobias Gemmeke:
Fully Digital, Standard-Cell-Based Multifunction Compute-in-Memory Arrays for Genome Sequencing. 30-41 - Siavash Mowlavi, Stavros Giannakopoulos, Alexander Grabowski, Lars Svensson:
A Review of IC Drivers for VCSELs in Datacom Applications. 42-54 - Yu-Kai Huang, Saul Rodriguez:
Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications. 55-67 - Johnson Loh, Tobias Gemmeke:
Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers. 68-78 - Fredrik Feyling, Hampus Malmberg, Carsten Wulff, Hans-Andrea Loeliger, Trond Ytterdal:
Design and Analysis of the Leapfrog Control-Bounded A/D Converter. 79-88 - Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho:
Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations. 89-102 - Abdulaziz Alshaya, Sudhakar Pamarti, Christos Papavassiliou:
FPGA Crystal Oscillator Circuit Emulation Based on Wave Digital Filter. 103-115 - Aibin Yan, Litao Wang, Jie Cui, Zhengfeng Huang, Tianming Ni, Patrick Girard, Xiaoqing Wen:
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS. 116-127 - Na Bai, Xin Xiao, Yaohua Xu, Yi Wang, Liang Wang, Xinjie Zhou:
Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications. 128-136 - Pengcheng Huang, Yaohua Wang, Zhenyu Zhao, Daheng Yue:
CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing. 137-149 - Zuzana Jelcicová, Evangelia Kasapaki, Oskar Andersson, Jens Sparsø:
PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments. 150-163 - Chen Yang, Yishuo Meng, Jiawei Xi, Siwei Xiang, Jianfei Wang, Kuizhi Mei:
WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks. 164-177 - Chenghan Wang, Qinzhi Xu, Chuanjun Nie, He Cao, Jianyun Liu, Daoqing Zhang, Zhiqiang Li:
A Multiscale Anisotropic Thermal Model of Chiplet Heterogeneous Integration System. 178-189 - Shourya Gupta, Shuo Li, Benton H. Calhoun:
Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS. 190-194 - Irith Pomeranz:
Testability Evaluation for Local Design Modifications. 195-199 - Ke Chang, Qian Xing, Guoliang Jia, Yang Pu, Yan Wang, Yuxin Wang, Yanlong Zhang, Guohe Zhang:
An Improved DEM for Multibit DT ΣΔMs Based on Poles Splitting Technique and Segmented VQ. 200-204
Volume 32, Number 2, February 2024
- Lucas Compassi Severo, Tailize C. De-Oliveira, Paulo César Comassetto de Aguirre, Wilhelmus A. M. Van Noije, Alessandro Gonçalves Girardi:
Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass Filters. 205-218 - Charalampos Eleftheriadis, Georgios Chatzitsompanis, Georgios Karakonstantis:
Enabling Voltage Over-Scaling in Multiplierless DSP Architectures via Algorithm-Hardware Co-Design. 219-230 - Manuel Brosch, Matthias Probst, Matthias Glaser, Georg Sigl:
A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic. 231-244 - Sureum Choi, Daejin Han, Chanyeong Choi, Yeongkyo Seo:
Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System. 245-255 - Liang Chang, Xin Zhao, Ting Yue, Xi Yang, Chenglong Li, Shuisheng Lin, Jun Zhou:
IPOCIM: Artificial Intelligent Architecture Design Space Exploration With Scalable Ping-Pong Computing-in-Memory Macro. 256-268 - Shiwei Liu, Chen Mu, Hao Jiang, Yunzhengmao Wang, Jinshan Zhang, Feng Lin, Keji Zhou, Qi Liu, Chixiao Chen:
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. 269-282 - Junjie An, Zhidao Zhou, Linfang Wang, Wang Ye, Weizeng Li, Hanghang Gao, Zhi Li, Jinghui Tian, Yan Wang, Hongyang Hu, Jinshan Yue, Lingyan Fan, Shibing Long, Qi Liu, Chunmeng Dou:
Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge. 283-290 - Bin Li, Yunfei Yan, Yuanxin Wei, Heru Han:
Scalable and Parallel Optimization of the Number Theoretic Transform Based on FPGA. 291-304 - Tao Zhang, Md Latifur Rahman, Hadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi:
SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation. 305-318 - Tao Zhang, Mark M. Tehranipoor, Farimah Farahmandi:
TrustGuard: Standalone FPGA-Based Security Monitoring Through Power Side-Channel. 319-332 - Md. Moshiur Rahman, Swarup Bhunia:
Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection. 333-346 - Christopher Vega, Patanjali SLPSK, Swarup Bhunia:
IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering Attacks. 347-360 - Vijaypal Singh Rathor, Munesh Singh, Kshira Sagar Sahoo, Saraju P. Mohanty:
GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking. 361-371 - Zhuojun Chen, Wenhao Yang, Jinghang Chen, Zujun Wang, Ding Ding:
Improving Radiation Reliability of SRAM-Based Physical Unclonable Function With Self-Healing and Pre-Irradiation Masking Techniques. 372-381 - Jingqi Zhang, Zhiming Chen, Mingzhi Ma, Rongkun Jiang, Hongshuo Li, Weijiang Wang:
High-Performance ECC Scalar Multiplication Architecture Based on Comb Method and Low-Latency Window Recoding Algorithm. 382-395 - Run Yan, Yin Su, Hui Guo, Yashuai Lü, Jin Wang, Nong Xiao, Li Shen, Yongwen Wang, Libo Huang:
MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray Tracing. 396-400
Volume 32, Number 3, March 2024
- Jinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, Sung Kyu Lim:
A PPA Study for Heterogeneous 3-D IC Options: Monolithic, Hybrid Bonding, and Microbumping. 401-412 - Sai Pentapati, Sung Kyu Lim:
Heterogeneous Monolithic 3-D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs. 413-421 - Xiaoxiao Zheng, Mao Ye, Zhiwei Li, Yao Li, Qiuwei Wang, Yiqiang Zhao:
A CMOS AFE Array With DC Input Current Cancellation for FMCW LiDAR. 422-431 - Hongge Li, Yuhao Chen:
Hybrid Stochastic Number and Its Neural Network Computation. 432-441 - Yongqiang Zhang, Jiao Qin, Jie Han, Guangjun Xie:
Design of a Stochastic Computing Architecture for the Phansalkar Algorithm. 442-454 - Sunwoong Kim, Cameron James Norris, James I. Oelund, Rob A. Rutenbar:
Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers. 455-467 - Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi:
FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing. 468-479 - Po-Yuan Chou, Wei-Ming Chen, Shen-Iuan Liu:
A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range. 480-484 - Zhaojun Lu, Xueyan Wang, Md Tanvir Arafin, Haoxiang Yang, Zhenglin Liu, Jiliang Zhang, Gang Qu:
An RRAM-Based Computing-in-Memory Architecture and Its Application in Accelerating Transformer Inference. 485-496 - YaJuan Hui, Qingzhen Li, Leimin Wang, Cheng Liu, Deming Zhang, Xiangshui Miao:
In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays. 497-504 - Yuan Dai, Jingyuan Li, Qilong Zhu, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang:
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization. 505-518 - Si-Huang Liu, Chia-Yi Kuo, Yannan Mo, Tao Su:
An Area-Efficient, Conflict-Free, and Configurable Architecture for Accelerating NTT/INTT. 519-529 - Bofan Chen, Zhiqun Li, Wei Shi, Yan Yao, Zhi-Ying Xia, Bing-Yan Qiu, Hao Ji:
A 6-18-GHz 6-bit Full-360° Vector-Sum Phase Shifter With Low Error in 40-nm CMOS. 530-541 - Yifei Zheng, Boyu Li, Qianheng Dong, Yutao Ying, Deyuan Song, Jing Zhu, Weifeng Sun, Qinsong Qian, Long Zhang, Sheng Li, Denggui Wang, Jianjun Zhou:
A 200-V Half-Bridge Monolithic GaN Power IC With High-Speed Level Shifter and dVS/dt Noise Immunity Enhancement Structure. 542-551 - Rakesh Varma Rena, Raviteja Kammari, Vijay Shankar Pasupureddi:
A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End. 552-563 - Xingyu Wang, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara:
A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement. 564-572 - Thai-Ha Tran, Duc-Thuan Dam, Ba-Anh Dao, Van-Phuc Hoang, Cong-Kha Pham, Trong-Thuc Hoang:
Compacting Side-Channel Measurements With Amplitude Peak Location Algorithm. 573-586 - Mahsa Zareie, Kamal El-Sankary, Ezz I. El-Masry, Ximing Fu:
An Open-Loop VCO-ADC Based on a Linearized Current Control Technique. 587-591 - Kasra Ahmadi, Saeed Aghapour, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs. 592-596
Volume 32, Number 4, April 2024
- Licai Hao, Xinyi Zhang, Chenghu Dai, Qiang Zhao, Wenjuan Lu, Chunyu Peng, Yongliang Zhou, Zhiting Lin, Xiulong Wu:
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies. 597-608 - Irith Pomeranz:
Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve. 609-618 - Aswini K. Samantaray, Pranose J. Edavoor, Amol D. Rahulkar:
A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks. 619-632 - Erfan Bank Tavakoli, Michael Riera, Masudul Hassan Quraishi, Fengbo Ren:
FSpGEMM: A Framework for Accelerating Sparse General Matrix-Matrix Multiplication Using Gustavson's Algorithm on FPGAs. 633-644 - Xiao Hu, Zhihao Li, Zhongfeng Wang, Xianhui Lu:
ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption. 645-657 - Musha Ji'e, Hongxin Peng, Shukai Duan, Lidan Wang, Fengqing Zhang, Dengwei Yan:
Design and FPGA Implementation of Grid-Scroll Hamiltonian Conservative Chaotic Flows With a Line Equilibrium. 658-668 - Jia-Zhao Lin, Po-Ta Chen, Hung-Yuan Chin, Pei-Yun Tsai, Sz-Yuan Lee:
Design and Implementation of a Real-Time Imaging Processor for Spaceborne Synthetic Aperture Radar With Configurability. 669-681 - Basant Kumar Mohanty:
Memory-Efficient Multiplier-Less 2-D DWT Design Using Combined Convolution and Lifting Schemes for Wireless Visual Sensors. 695-703 - Yi-Hao Lan, Shen-Iuan Liu:
A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector. 704-713 - Changmin Song, Hoyong Jung, KyoungSeop Chang, Kwanglae Cho, Seungyong Yoon, Young-Chan Jang:
A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber. 714-727 - Ana Mitrovic, Eby G. Friedman:
Thermal Exploration of RSFQ Integrated Circuits. 728-738 - Joseph Franklin Clements, Yingjie Lao:
Reliable Hardware Watermarks for Deep Learning Systems. 752-762 - Renas Ercan, Yunjia Xia, Yunyi Zhao, Rui C. V. Loureiro, Shufan Yang, Hubin Zhao:
An Ultralow-Power Real-Time Machine Learning Based fNIRS Motion Artifacts Detection. 763-773 - Jun Liu, Songren Cheng, Tian Chen, Xi Wu, Huaguo Liang:
A Self-Biased Current Reference Source-Based Pre-Bond TSV Test Solution. 774-781 - Chenjia Xie, Zhuang Shao, Zhichao Chen, Yuan Du, Li Du:
An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction. 782-786 - Hsi-Kai Peng, Shen-Iuan Liu:
A 12.93-16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection. 787-791
Volume 32, Number 5, May 2024
- Zeju Li, Qinfan Wang, Zihan Zou, Qiao Shen, Na Xie, Hao Cai, Hao Zhang, Bo Liu:
Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications. 797-809 - Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang:
Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions. 810-822 - Daijoon Hyun, Younggwang Jung, Youngsoo Shin:
Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs. 823-834 - Li Luo, Bochang Li, Lidan Wang, Jinpei Tan, Shukai Duan, Chunxiang Zhu:
Reconfigurable Stateful Logic Circuit With Cu/CuI/Pt Memristors for In-Memory Computing. 835-847 - Chao-Yu Chen, Yan-Siou Dai, Hao-Chiao Hong:
A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM. 848-859 - Xin Zheng, Mingjun Cheng, Jiasong Chen, Huaien Gao, Xiaoming Xiong, Shuting Cai:
BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning. 860-869 - Tianyou Bao, Pengzhou He, Shi Bai, Jiafeng Xie:
TINA: TMVP-Initiated Novel Accelerator for Lightweight Ring-LWE-Based PQC. 870-882 - Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu:
Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design. 883-896 - Bo Zhang, Zeming Cheng, Massoud Pedram:
Design of a High-Performance Iterative Barrett Modular Multiplier for Crypto Systems. 897-910 - Md Toufiq Hasan Anik, Jean-Luc Danger, Sylvain Guilley, Naghmeh Karimi:
On the Resiliency of Protected Masked S-Boxes Against Template Attack in the Presence of Temperature and Aging Misalignments. 911-924 - Dongdong Xu, Xiang Wang, Qiang Hao, Jiqing Wang, Shuangjie Cui, Bo Liu:
A High-Performance Transparent Memory Data Encryption and Authentication Scheme Based on Ascon Cipher. 925-937 - Haoming Zhang, Shuowei Li, Tetsuya Iizuka:
A Single Ring-Oscillator-Based Test Structure for Timing Characterization of Dynamic Circuit. 938-951 - Isa H. Altoobaji, Ahmad Hassan, Mohamed Ali, Yves Audet, Ahmed Lakhssassi:
A Low-Power 0.68-Gbps Data Communication System for Capacitive Digital Isolator With 1.9-ns Propagation Delay. 952-956 - Likai Pei, Xiaodong Meng, Xing Li:
A Novel Digital-Controlled Current-Mode Single-Inductor-Multiple-Output Buck Converter With Individual Output Overload Protection. 957-961 - Dengquan Li, Tian Feng, Jiale Ding, Yi Shen, Shubin Liu, Zhangming Zhu:
A Wideband Input Buffer Based on Cascade Complementary Source Follower. 962-966 - Eduardo Ortega, Jonti Talukdar, Woohyun Paik, Tyler K. Bletsch, Krishnendu Chakrabarty:
Rowhammer Vulnerability of DRAMs in 3-D Integration. 967-971 - Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang:
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. 972-976
Volume 32, Number 6, June 2024
- Bingbing Ma, Wei Li, Hongtao Xu:
Analysis and Calibration of Bit Weights in SAR and Pipelined SAR ADCs Based on Code Distribution. 977-990 - Nastaran Darabi, Maeesha Binte Hashem, Hongyi Pan, Ahmet Enis Çetin, Wilfred Gomes, Amit Ranjan Trivedi:
ADC/DAC-Free Analog Acceleration of Deep Neural Networks With Frequency Transformation. 991-1003 - Tianyang Yu, Bi Wu, Ke Chen, Chenggang Yan, Weiqiang Liu:
Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization. 1004-1017 - Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Mohit Gupta, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Francky Catthoor:
An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs. 1018-1031 - Robert Balas, Alessandro Ottaviano, Luca Benini:
CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers. 1032-1044 - Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu:
Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension. 1045-1057 - Wei Xiong, Jiacheng Cao, Yaozhang Liu, Jian Wang, Jinmei Lai, Miaoqing Huang:
A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs. 1058-1071 - Zhuo Xuan, Shiwei Ren, Chengbo Xue, Guiyu Wang, Xiangnan Li:
A Hardware Acceleration of Maximum Likelihood Estimation Algorithm With Alternating Projection on FPGA. 1072-1085 - Xiao Wu, Miaoxin Wang, Jun Lin, Zhongfeng Wang:
Amoeba: An Efficient and Flexible FPGA-Based Accelerator for Arbitrary-Kernel CNNs. 1086-1099 - Yerzhan Mustafa, Selçuk Köse:
Built-In Self-Test of SFQ Circuits Using Side-Channel Leakage Information. 1100-1109 - Amisha Srivastava, Sanjay Das, Navnil Choudhury, Rafail Psiakis, Pedro Henrique Silva, Debjit Pal, Kanad Basu:
SCAR: Power Side-Channel Analysis at RTL Level. 1110-1123 - Alexandre Proulx, Jean-Yves Chouinard, Amine Miled, Paul Fortier:
Analyzing the Vulnerabilities of External SDRAM on System-on-Chip Field Programmable Gate Array Devices. 1124-1135 - Hayoung Lee, Sooryeong Lee, Sungho Kang:
RA-Aware Fail Data Collection Architecture for Cost Reduction. 1136-1149 - Amit Mazumder Shuvo, Tao Zhang, Farimah Farahmandi, Mark M. Tehranipoor:
FLAT: Layout-Aware and Security Property-Assisted Timing Fault-Injection Attack Assessment. 1150-1163 - Wenrui Liu, Jiafeng Cheng, Nengyuan Sun, Heng Sha, Zunxian Fu, Zhaokang Peng, Chunyang Wang, Caiban Sun, Pengliang Kong, Yunfeng Zhao, Yaoqiang Wang, Weize Yu:
A 128-Gbps Pipelined SM4 Circuit With Dual DPA Attack Countermeasures. 1164-1168 - Jongchan An, Seung-Myeong Yu, Gwangmyeong An, Bongsu Kim, Hyunsu Jang, Sewook Hwang, Junyoung Song:
A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit. 1169-1172
Volume 32, Number 7, July 2024
- Haoyang Shen, Deepu John, Barry Cardiff:
FEC-Aided Decision Feedback Blind Mismatch Calibration of TIADCs in Wireless Time-Varying Channel Environments. 1173-1183 - Zhifei Lu, Bowen Zhang, Xizhu Peng, Hang Liu, Xiaolei Ye, Yuzhuo Li, Yutao Peng, Yao Xiao, Wei Zhang, He Tang:
A New Artificial Neural Network-Based Calibration Mechanism for ADCs: A Time-Interleaved ADC Case Study. 1184-1194 - Siji Huang, Debajit Basak, Yanhang Chen, Qifeng Huang, Yifei Fan, Jie Yuan:
An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend. 1195-1204 - Kashif Inayat, Inayat Ullah, Jaeyong Chung:
Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration. 1205-1215 - Alireza Nahvy, Zainalabedin Navabi:
Pico-Programmable Neurons to Reduce Computations for Deep Neural Network Accelerators. 1216-1227 - Florian Hirner, Ahmet Can Mert, Sujoy Sinha Roy:
Proteus: A Pipelined NTT Architecture Generator. 1228-1238 - Ziyang Kang, Jingwei Zhu, Xun Xiao, Shiming Li, Lei Wang, De Ma, Gang Pan:
LSM-Based Hotspot Prediction and Hotspot-Aware Routing in NoC-Based Neuromorphic Processor. 1239-1252 - Shu-Yu Chang, Shi-Yu Huang:
A Check-and-Balance Scheme in Multiphase Delay-Locked Loop. 1253-1262 - Yi-Hao Lan, Shen-Iuan Liu:
A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS. 1263-1272 - Baoling Hong, Haikuo Shao, Zhongfeng Wang:
A Low Complexity Online Learning Approximate Message Passing Detector for Massive MIMO. 1273-1284 - Ashish Ranjan Shadangi, Suvra Sekhar Das, Indrajit Chakrabarti:
Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel. 1285-1296 - Bowen Xia, De-han Wang, Wenhua Chen, Fadhel M. Ghannouchi, Zhenghe Feng:
A 24-40-GHz Broadband Beamforming TRX Front-End IC With Unified Phase and Gain Control for Multiband Phased Array Systems. 1297-1310 - Md Rafid Muttaki, Md Habibur Rahman, Akshay Kulkarni, Mark M. Tehranipoor, Farimah Farahmandi:
FTC: A Universal Framework for Fault-Injection Attack Detection and Prevention. 1311-1324 - Haitong Huang, Cheng Liu, Xinghua Xue, Bo Liu, Huawei Li, Xiaowei Li:
MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing. 1325-1335 - Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty:
Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration. 1336-1349 - Morteza Yousefloo, Omid Akbari:
Design Exploration of Fault-Tolerant Deep Neural Networks Using Posit Number Representation System. 1350-1363 - Behdad Jamadi, Shiuh-Hua Wood Chiang, Armin Tajalli:
Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers. 1364-1368
Volume 32, Number 8, August 2024
- Yi-Fan Liu, Dawei Wang, Zhekang Dong, Hao Xie, Wen-Sheng Zhao:
Implementation of Multiple-Step Quantized STDP Based on Novel Memristive Synapses. 1369-1379 - Chao Li, Chen Sun, Jianyi Yang, Kai Ni, Xiao Gong, Cheng Zhuo, Xunzhao Yin:
Multibit Content Addressable Memory Design and Optimization Based on 3-D nand-Compatible IGZO Flash. 1380-1388 - Nunzio Spina, Marcello Raimondi, Alessandro Castorina, Egidio Ragonese, Giuseppe Palmisano:
A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers. 1389-1399 - Luchang He, Chenchen Xie, Zhao Han, Qingyu Wu, Houpeng Chen, Shibing Long, Xi Li, Zhitang Song:
A Power-On-Reset Circuit With Accurate Trigger-Point Voltage and Ultralow Typical Quiescent Current for Emerging Nonvolatile Memory. 1400-1408 - Shouharda Ghosh, Pramod Kumar Meher, Dwaipayan Ray, Nithin V. George:
Low Complexity Design of Logistic Distance Metric Adaptive Filter for Impulsive Noise Environments. 1409-1413 - Seyedarmin Azizi, Mahdi Nazemi, Mehdi Kamal, Massoud Pedram:
Low-Precision Mixed-Computation Models for Inference on Edge. 1414-1422 - Madhan Thirumoorthi, Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani, Mohammed A. S. Khalid:
A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2m). 1423-1435 - Runze Yu, Zhenhao Li, Xi Deng, Zhaoxu Wang, Wei Jia, Haoming Zhang, Zhenglin Liu:
iEDCL: Streamlined, False-Error-Free Error Detection and Correction Scheme in a Near-Threshold Enabled 32-bit Processor. 1436-1446 - D. R. Vasanthi, Sanampudi Gopala Krishna Reddy, Madhav Rao:
HRM: M-Term Heterogeneous Hybrid Blend Recursive Multiplier for GF(2n) Polynomial. 1447-1460 - Zijian Tang, Yongxiang Guo, Minqian Zheng, Chao Sun, Yusong Wu, Runjiu Fang, Ying Fang, Milin Zhang:
An 112-Ch Neural Signal Acquisition SoC With Full-Channel Read-Out and Processing Accelerators. 1461-1471 - Fanny Spagnolo, Stefania Perri, Massimo Vatalaro, Fabio Frustaci, Felice Crupi, Pasquale Corsonello:
Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization. 1472-1484 - Zikang Zhou, Xuyang Duan, Jun Han:
A Design Framework for Generating Energy-Efficient Accelerator on FPGA Toward Low-Level Vision. 1485-1497 - Junichi Sakamoto, Daisuke Fujimoto, Riku Anzai, Naoki Yoshida, Tsutomu Matsumoto:
High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications. 1498-1511 - Jhe-En Lin, Yi-Hao Lan, Shen-Iuan Liu:
A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker. 1512-1522 - Xu Yan, Jingyuan Zhang, Guansheng Lv, Wenhua Chen, Yongxin Guo:
Gain and Power Enhancement With Coupled Technique for a Distributed Power Amplifier in 0.25- μm GaN HEMT Technology. 1523-1534 - Jonti Talukdar, Woohyun Paik, Eduardo Ortega, Krishnendu Chakrabarty:
ALT-Lock: Logic and Timing Ambiguity-Based IP Obfuscation Against Reverse Engineering. 1535-1548 - Enlai Li, Sharad Sinha, Wei Zhang:
Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems. 1549-1553 - Loai G. Salem:
Symmetric and Multiphase-Interleaved Ladder Bucks for DC Capacitors Elimination. 1554-1558 - Xiaolu Hou, Jakub Breier, Mladen Kovacevic:
Another Look at Side-Channel-Resistant Encoding Schemes. 1559-1563 - M. Vafaieenezhad, M. B. Ghaznavi-Ghoushchi:
An Unconditional Evenly Spaced STRO With a New Mitigated Drafting Effect Muller C-Element. 1564-1568
Volume 32, Number 9, September 2024
- Tahesin Samira Delwar, Abrar Siddique, Unal Aras, Yang-Won Lee, Jee-Youl Ryu:
A μ-GA Oriented ANN-Driven: Parameter Extraction of 5G CMOS Power Amplifier. 1569-1577 - Fan Chen, Wei Li, Chuangguo Wang, Yunyou Pu, Xingyu Ma, Shijiao Dong, Yun Wang, Hongtao Xu:
Enhanced-Linearity Wideband Full-Duplex Receiver With Shared Self-Interference Canceller. 1578-1589 - Yasong Cao, Mei Wen, Zhongdi Luo, Xin Ju, Haolan Huang, Junzhong Shen, Haiyan Chen:
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core. 1590-1601 - Sergio Mazzola, Samuel Riedel, Luca Benini:
Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory Manycore Clusters. 1602-1615 - Panagiotis Chatziantoniou, Antonis Tsigkanos, Dimitris Theodoropoulos, Nektarios Kranitis, Antonis M. Paschalis:
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance. 1616-1629 - Loai G. Salem:
Analysis and Optimization of Sense-and-Set Piezoelectric Energy Harvesting Interface Circuits. 1630-1639 - Yu Qian, Liang Zhao, Fanzi Meng, Xiapeng Xu, Cheng Zhuo, Xunzhao Yin:
Enhancing ConvNets With ConvFIFO: A Crossbar PIM Architecture Based on Kernel-Stationary First-In-First-Out Dataflow. 1640-1651 - Sameen Minto, Austin Cable, Wala Saadeh:
A 206 μW Vital Signs Monitoring System on Chip for Measuring Five Vitals. 1652-1660 - Mizan Abraha Gebremicheal, Ibrahim M. Elfadel:
Secure Edge-Coded Signaling IoT Transceiver With Reduced Encryption Overhead. 1661-1671 - Meenali Janveja, Rushik Parmar, Srichandan Dash, Jan Pidanic, Gaurav Trivedi:
A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices. 1672-1683 - Samuel Coulon, Tianyou Bao, Jiafeng Xie:
FELIX: FPGA-Based Scalable and Lightweight Accelerator for Large Integer Extended GCD. 1684-1695 - Yuan-Chun Luo, Anni Lu, Yandong Luo, Sou-Chi Chang, Uygar Avci, Shimeng Yu:
Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture. 1696-1703 - Huihong Shi, Xin Cheng, Wendong Mao, Zhongfeng Wang:
P2-ViT: Power-of-Two Post-Training Quantization and Acceleration for Fully Quantized Vision Transformer. 1704-1717 - Yuan-Chun Luo, Anni Lu, Janak Sharda, Moritz Scherer, Jorge Tomás Gómez, Syed Shakib Sarwar, Ziyun Li, Reid Frederick Pinkham, Barbara De Salvo, Shimeng Yu:
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads. 1718-1725 - Xiao Li, Lin Chen, Shixi Chen, Fan Jiang, Chengeng Li, Wei Zhang, Jiang Xu:
Deep Reinforcement Learning-Based Power Management for Chiplet-Based Multicore Systems. 1726-1739 - Le Wu, Liji Wu, Xiangmin Zhang, Munkhbaatar Chinbat:
Dual-Rail Precharge Logic-Based Side-Channel Countermeasure for DNN Systolic Array. 1740-1743 - Yok Jye Tang, Xinmiao Zhang:
Low-Complexity Parallel Chien Search Architecture Based on Vandermonde Matrix Decomposition. 1744-1748 - Shan Lu, Danyu Wu, Xuan Guo, Hanbo Jia, Yong Chen, Xinyu Liu:
A 28-nm Dual-Mode Explicit Class-F₂₃ VCO With Low-Loss CM Return Path Achieving 70-400-kHz 1/f³ PN Corner Over 4.9-7.3-GHz TR. 1749-1753 - Young-Kyun Cho:
A Dual-Mode Continuous-Time Sigma-Delta Modulator With a Reconfigurable Loop Filter Based on a Single Op-Amp Resonator. 1754-1758 - Bhaskar Gaur, Himanshu Thapliyal:
Novel Optimized Designs of Modulo 2n+1 Adder for Quantum Computing. 1759-1763 - Yichen Zhang, Chaowei Tang, Yanqi Zheng, Xian Tang, Ka Nang Leung:
An Adaptive Zero-Current Detector for Single-Inductor Multiple-Output DC-DC Converter With Full-Wave Current Sensor. 1764-1768
Volume 32, Number 10, October 2024
- Xiaoning Ma, Qinzhi Xu, Chenghan Wang, He Cao, Jianyun Liu, Daoqing Zhang, Zhiqiang Li:
An Electrical-Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems. 1769-1781 - Chengzhi Xu, Xufeng Liao, Peiyuan Fu, Yongyuan Li, Lianxi Liu:
A Dual-Mode Buck Converter with Light-Load Efficiency Improvement and Seamless Mode Transition Technique. 1782-1791 - M. Ghashghai, M. B. Ghaznavi-Ghoushchi:
Design and Analysis of a New Three-Stage Feedback Amplifier Utilizing Signal Flow Graph Domain Inspection Approach. 1792-1800 - Meysam Akbari, Kea-Tiong Tang:
The Conjugated Current Mirrors: A General Enhancement in Transconductance Amplifiers. 1801-1811 - Ziliang Zhou, Min Tan:
A 20-V Pulse Driver Based on All-nMOS Charge Pump Without Reversion Loss and Overstress in 65-nm Standard CMOS Technology. 1812-1821 - Yichen Xu, Zhaoqing Wang, Jonghyun Oh, Mingoo Seok:
Model-Based Study on the Limit of the Dynamic Load Regulation Performance of a Digital Low Dropout Regulator. 1822-1829 - Pranav O. Mathews, Praveen Raj Ayyappan, Afolabi Ige, Swagat Bhattacharyya, Linhao Yang, Jennifer O. Hasler:
A 65 nm CMOS Analog Programmable Standard Cell Library for Mixed-Signal Computing. 1830-1840 - Qifeng Huang, Siji Huang, Yanhang Chen, Yifei Fan, Jie Yuan:
An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation. 1841-1851 - Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu:
Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint. 1852-1863 - Jinming Zhang, Xuyan Wang, Yaoyao Ye, Dongxu Lyu, Guojie Xiong, Ningyi Xu, Yong Lian, Guanghui He:
M2M: A Fine-Grained Mapping Framework to Accelerate Multiple DNNs on a Multi-Chiplet Architecture. 1864-1877 - Yu-Cheng Lin, Ren-Hao Chiou, Chia-Hsiang Yang:
A High-Throughput Constructive Interference Precoder for 16 × MU-MIMO Systems. 1878-1888 - Heng Zhang, Wenhe Yin, Sunan He, Yuan Du, Li Du:
An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks. 1889-1899 - Joshua Adiel Wijaya, Poki Chen, Lucky Kumar Pradhan, Ahmad Shahid Bhatti, Seiji Kajihara:
Area Efficient 0.009-mm2 28.1-ppm/°C 11.3-MHz ALL-MOS Relaxation Oscillator. 1900-1907 - Youming Zhang, Xusheng Tang, Tonglu Jiao, Peng Liu, Jingchen Liu:
Design of Octave Tuning Range LC VCO With Ultralow KVCO Using Frequency-Dependent Implicit Capacitance Neutralization Technique. 1908-1918 - Yankun Zhu, Pingqiang Zhou:
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies. 1919-1929 - Luchang He, Chenchen Xie, Qingyu Wu, Siqiu Xu, Houpeng Chen, Xing Ding, Xi Li, Zhitang Song:
A Low-Cost Quadruple-Node-Upsets Resilient Latch Design. 1930-1939 - Yuyang Li, Vijay Shankaran Vivekanand, Rajkumar Kubendran, Inhee Lee:
Dynamic Neural Fields Accelerator Design for a Millimeter-Scale Tracking System. 1940-1944 - Xian Lin, Heming Liu, Xin Zheng, Huaien Gao, Shuting Cai, Xiaoming Xiong:
FPUx: High-Performance Floating-Point Support for Cost-Constrained RISC-V Cores. 1945-1949 - Hayoung Lee, Jongho Park, Sungho Kang:
An Area-Efficient Systolic Array Redundancy Architecture for Reliable AI Accelerator. 1950-1954 - Mehdi Saberi, Hossein Yaghoobzadeh Shadmehri, Mohammad Tavakkoli Ghouchani, Alexandre Schmid:
A High-Precision and High-Dynamic-Range Current-Mode WTA Circuit for Low-Supply-Voltage Applications. 1955-1958 - Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Kwen-Siong Chong, Bah-Hwee Gwee:
Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine. 1959-1963 - Fan Li, Yunqi Guan, Wen Bin Ye:
A Hardware and Software Co-Design for Energy-Efficient Neural Network Accelerator With Multiplication-Less Folded-Accumulative PE for Radar-Based Hand Gesture Recognition. 1964-1968
Volume 32, Number 11, November 2024
- Vassilis Alimisis, Emmanouil Anastasios Serlis, Andreas Papathanasiou, Nikolaos P. Eleftheriou, Paul P. Sotiriadis:
Power-Efficient Analog Hardware Architecture of the Learning Vector Quantization Algorithm for Brain Tumor Classification. 1969-1982 - Yanhang Chen, Siji Huang, Qifeng Huang, Yifei Fan, Jie Yuan:
The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution SAR ADCs. 1983-1992 - Yu Lu, Xiaowu Cai, Jian Lu, Longli Pan, Jianying Dang, Yafei Xie, Xupeng Wang, Bo Li:
A nMOS-R Cross-Coupled Level Shifter With High dV/dt Noise Immunity for 600-V High-Voltage Gate Driver IC. 1993-2000 - Xiang Yan, Kefan Qin, Xinyue Zheng, Weibo Hu, Wei Ma, Haitao Cui:
A Two-Channel Interleaved ADC With Fast-Converging Foreground Time Calibration and Comparison-Based Control Logic. 2001-2011 - Jafar Vafaei, Omid Akbari:
HPR-Mul: An Area and Energy-Efficient High-Precision Redundancy Multiplier by Approximate Computing. 2012-2022 - Duy-Thanh Nguyen, Abhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda:
MCAIMem: A Mixed SRAM and eDRAM Cell for Area and Energy-Efficient On-Chip AI Memory. 2023-2036 - Zipeng Fan, Sanqian Wang, Xueting Pu, Yuting Cong, Yuan Liu, Xiubao Sui, Qian Chen:
DLB-CNet: Difference Learning-Based Convolution Network for Building Change Detection. 2037-2045 - Arunkumar P. Chavan, Shrish Shrinath Vaidya, Sanket M. Mantrashetti, Abhishek Gurunath Dastikopp, Kishan S. Murthy, H. V. Ravish Aradhya, Prakash Pawar:
A Novel TriNet Architecture for Enhanced Analog IC Design Automation. 2046-2059 - Mitchell Cooke, Nicola Nicolici:
Thresholding Decision-Directed Descent (T3D): A Tuning Solution for DDR5 DRAM DFEs. 2060-2073 - Tobias Schirmer, Simon Buhr, Felix Burkhardt, Florian Protze, Frank Ellinger:
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control. 2074-2084 - Dongrui Li, Ming Ming Wong, Yi Sheng Chong, Jun Zhou, Mohit Upadhyay, Ananta Narayanan Balaji, Aarthy Mani, Weng-Fai Wong, Li-Shiuan Peh, Anh Tuan Do, Bo Wang:
1.63 pJ/SOP Neuromorphic Processor With Integrated Partial Sum Routers for In-Network Computing. 2085-2092 - Li-De Chen, Li-Qun Weng, Hao-Chien Cheng, An-Yu Cheng, Kai-Ping Lin, Chao-Tsung Huang:
VLSI Design of Light-Field Factorization for Dual-Layer Factored Display. 2093-2106 - Hossein Rezaei, Elham Abbasi, Nandana Rajatheva, Matti Latva-aho:
Unrolled, Pipelined, and Stage-Folded Architectures for Encoding of Multi-Kernel Polar Codes. 2107-2120 - Xiaoyong Song, Zhichuan Guo:
An Implementation of Reconfigurable Match Table for FPGA-Based Programmable Switches. 2121-2134 - Yang Zhou, Wenjie Wang, Longbin Zhu, Zhengtao Zhu, Risheng Su, Jianan Zheng, Siyuan Xie, Jihong Li, Fanyi Meng, Zhijun Zhou, Keping Wang:
A Second-Order Noise Shaping SAR ADC With Parallel Multiresidual Integrator. 2135-2138 - Shin-Chi Lai, Szu-Ting Wang, Yi-Chang Zhu, Ying-Hsiu Hung, Jeng-Dao Lee, Wei-Da Chen:
High-Accuracy and Low-Multiplication Recursive Discrete Cosine Transform Algorithm Design and Its Realization in Mel-Scale Frequency Cepstral Coefficients. 2139-2143 - Leandro Mateus Giacomini Rocha, Refik Bilgic, Mohamed Naeim, Sudipta Das, Herman Oprins, Amirreza Yousefzadeh, Mario Konijnenburg, Dragomir Milojevic, James Myers, Julien Ryckaert, Dwaipayan Biswas:
Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures. 2144-2148 - Thockchom Birjit Singha, Basa Sanjana, Titu Mary Ignatius, Roy Paily Palathinkal, Shaik Rafi Ahamed:
Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks. 2149-2153 - Kasra Ahmadi, Saeed Aghapour, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder. 2154-2158 - Irith Pomeranz, Yervant Zorian:
Functionally Possible Path Delay Faults With High Functional Switching Activity. 2159-2163 - Xin Si, Fangyuan Dong, Shengnan He, Yuhui Shi, Anran Yin, Hui Gao, Xiang Li:
A 28 nm 16-kb Sign-Extension-Less Digital-Compute-in-Memory Macro With Extension-Friendly Compute Units and Accuracy-Adjustable Adder-Tree. 2164-2168
Volume 32, Number 12, December 2024
- Jari Nurmi, Snorre Aunet, Alireza Saberkari:
Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2023. 2169-2172 - Patrick Fath, Harald Pretl:
A 370-nW Bio-AFE With 2.9-μ Vrms Input Noise in an Octa-Channel System-in-Package for Multimode Bio-Signal Acquisition. 2173-2185 - Kimi Jokiniemi, Kaisa Ryynänen, Joni Vähä, Elmo Kankkunen, Kari Stadius, Jussi Ryynänen:
55-100-GHz Enhanced Gilbert Cell Mixer Design in 22-nm FDSOI CMOS. 2186-2197 - Jere Rusanen, Negar Shabanzadeh, Aarno Pärssinen, Timo Rahkonen, Janne P. Aikio:
Improving a Ka-Band Integrated Balanced Power Amplifier Performance by Compensating Quadrature Hybrid Mismatch Effects. 2198-2209 - Ko-Hong Lin, Ont-Derh Lin, Shi-Yu Huang, Duo Sheng:
Low-Jitter Frequency Doubling Circuit Supporting Higher-Speed BISG and Aging Sensing in a Chiplet-Based Design Environment. 2210-2219 - Ahmed M. Mohey, Jelin Leslin, Gaurav Singh, Marko Kosunen, Jussi Ryynänen, Martin Andraud:
A 22-nm All-Digital Time-Domain Neural Network Accelerator for Precision In-Sensor Processing. 2220-2231 - Negar Shabanzadeh, Aarno Pärssinen, Timo Rahkonen:
A Study on Nonlinearity in Mixers Using a Time-Varying Volterra-Based Distortion Contribution Analysis Tool. 2232-2242 - Francesco Gagliardi, Danilo Scintu, Massimo Piotto, Paolo Bruschi, Michele Dei:
Static-Linearity Enhancement Techniques for Digital-to-Analog Converters Exploiting Optimal Arrangements of Unit Elements. 2243-2256 - Topi Leppänen, Leevi Leppänen, Joonas Multanen, Pekka Jääskeläinen:
Bitstream Database-Driven FPGA Programming Flow Based on Standard OpenCL. 2257-2268 - Henri Lunnikivi, Roni Hämäläinen, Timo D. Hämäläinen:
Keelhaul: Processor-Driven Chip Connectivity and Memory Map Metadata Validator for Large Systems-on-Chip. 2269-2280 - Casper Cromjongh, Yongding Tian, H. Peter Hofstee, Zaid Al-Ars:
Hardware-Accelerator Design by Composition: Dataflow Component Interfaces With Tydi-Chisel. 2281-2292 - Zilin Wang, Yi Zhong, Zehong Ou, Youming Yang, Shuo Feng, Guang Chen, Xiaoxin Cui, Song Jia, Yuan Wang:
Marmotini: A Weight Density Adaptation Architecture With Hybrid Compression Method for Spiking Neural Network. 2293-2302 - Ramiro Taco, Esteban Garzón, Robert Hanhan, Adam Teman, Leonid Yavits, Marco Lanuzza:
Designing Precharge-Free Energy-Efficient Content-Addressable Memories. 2303-2314 - Lizhou Wu, Haozhe Zhu, Jiapei Zheng, Mengjie Li, Yinuo Cheng, Qi Liu, Xiaoyang Zeng, Chixiao Chen:
Hi-NeRF: A Multicore NeRF Accelerator With Hierarchical Empty Space Skipping for Edge 3-D Rendering. 2315-2326 - Daehyeon Lee, Junghee Lee, Younggiu Jung, Janghyuk Kauh, Taigon Song:
Robust Hardware Trojan Detection Method by Unsupervised Learning of Electromagnetic Signals. 2327-2340 - Thai-Ha Tran, Ba-Anh Dao, Duc-Hung Le, Van-Phuc Hoang, Trong-Thuc Hoang, Cong-Kha Pham:
Spread Spectrum-Based Countermeasures for Cryptographic RISC-V SoC. 2341-2354 - Anshaj Shrivastava, Gaurab Banerjee:
Analog Probe Module (APM) for Enhanced IC Observability: From Concept to Application. 2355-2367 - Yao Li, Junfeng Geng, Mao Ye, Jiaji He, Xiaoxiao Zheng, Qiuwei Wang, Yiqiang Zhao:
A CMOS Readout Circuit for Resistive Tactile Sensor Array Using Crosstalk Suppression and Nonuniformity Compensation Techniques. 2368-2376 - Xu Fang, Xiaofeng Zhao:
A Post-Bond ILV Test Method in Monolithic 3-D ICs. 2377-2388 - Feiran Liu, Anran Yin, Chen Xue, Bo Wang, Zhongyuan Feng, Han Liu, Xiang Li, Hui Gao, Tianzhu Xiong, Xin Si:
A 22-nm 264-GOPS/mm2 6T SRAM and Proportional Current Compute Cell-Based Computing-in-Memory Macro for CNNs. 2389-2393 - Andres Ayes, Eby G. Friedman:
Quasi-Adiabatic Clock Networks in 3-D Voltage Stacked Systems. 2394-2397 - Byeong Yong Kong:
Low-Latency PAPR Reduction Architecture for Discrete Multitone Based on Approximate Midrange. 2398-2402 - Riccardo Della Sala, Davide Bellizia, Giuseppe Scotti:
Unveiling the True Power of the Latched Ring Oscillator for a Unified PUF and TRNG Architecture. 2403-2407
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